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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity HeaderBuilder is
27 generic(
28 Data_sz : integer := 32);
29 port(
30 clkm : in std_logic;
31 rstn : in std_logic;
32
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
37 Valid : out std_logic;
38
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
42
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 emptyOUT : out std_logic;
45 RenIN : in std_logic;
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
49 header_ack : in std_logic
50 );
51 end entity;
52
53
54 architecture ar_HeaderBuilder of HeaderBuilder is
55
56 signal Matrix_Param : std_logic_vector(3 downto 0);
57 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
59 signal MAX : integer;
60
61
62 begin
63
64 process (clkm,rstn)
65 begin
66 if(rstn='0')then
67 Valid <= '0';
68 Write_reg <= '0';
69 Data_cpt <= 0;
70 MAX <= 0;
71
72
73 elsif(clkm' event and clkm='1')then
74 Write_reg <= Matrix_Write;
75
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 MAX <= 128;
78 else
79 MAX <= 256;
80 end if;
81
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
85 Valid <= '1';
86 header_val <= '1';
87 else
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
90 end if;
91 end if;
92
93 if(header_ack = '1')then
94 header_val <= '0';
95 end if;
96
97 end if;
98 end process;
99
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
104
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107
108 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
109
110 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
32 package lpp_Header is
33
34 component HeaderBuilder is
35 generic(
36 Data_sz : integer := 32);
37 port(
38 clkm : in std_logic;
39 rstn : in std_logic;
40
41 pong : in std_logic;
42 Statu : in std_logic_vector(3 downto 0);
43 Matrix_Type : in std_logic_vector(1 downto 0);
44 Matrix_Write : in std_logic;
45 Valid : out std_logic;
46
47 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
48 emptyIN : in std_logic_vector(1 downto 0);
49 RenOUT : out std_logic_vector(1 downto 0);
50
51 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
52 emptyOUT : out std_logic;
53 RenIN : in std_logic;
54
55 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
56 header_val : out std_logic;
57 header_ack : in std_logic
58 );
59 end component;
60
61 end; No newline at end of file
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1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 library ieee;
21 library ieee;
22 use ieee.std_logic_1164.all;
22 use ieee.std_logic_1164.all;
23 library grlib;
23 library grlib;
24 use grlib.amba.all;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
25 use grlib.stdlib.all;
26 library techmap;
26 library techmap;
27 use techmap.gencomp.all;
27 use techmap.gencomp.all;
28 library gaisler;
28 library gaisler;
29 use gaisler.memctrl.all;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
32 use gaisler.misc.all;
33 library esa;
33 library esa;
34 use esa.memoryctrl.all;
34 use esa.memoryctrl.all;
35 use work.config.all;
35 use work.config.all;
36 library lpp;
36 library lpp;
37 use lpp.lpp_amba.all;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
48 use lpp.lpp_demux.all;
49 use lpp.lpp_top_lfr_pkg.all;
49 use lpp.lpp_top_lfr_pkg.all;
50
50
51 entity leon3mp is
51 entity leon3mp is
52 generic (
52 generic (
53 fabtech : integer := CFG_FABTECH;
53 fabtech : integer := CFG_FABTECH;
54 memtech : integer := CFG_MEMTECH;
54 memtech : integer := CFG_MEMTECH;
55 padtech : integer := CFG_PADTECH;
55 padtech : integer := CFG_PADTECH;
56 clktech : integer := CFG_CLKTECH;
56 clktech : integer := CFG_CLKTECH;
57 disas : integer := CFG_DISAS; -- Enable disassembly to console
57 disas : integer := CFG_DISAS; -- Enable disassembly to console
58 dbguart : integer := CFG_DUART; -- Print UART on console
58 dbguart : integer := CFG_DUART; -- Print UART on console
59 pclow : integer := CFG_PCLOW
59 pclow : integer := CFG_PCLOW
60 );
60 );
61 port (
61 port (
62 clk50MHz : in std_ulogic;
62 clk50MHz : in std_ulogic;
63 reset : in std_ulogic;
63 reset : in std_ulogic;
64 ramclk : out std_logic;
64 ramclk : out std_logic;
65
65
66 ahbrxd : in std_ulogic; -- DSU rx data
66 ahbrxd : in std_ulogic; -- DSU rx data
67 ahbtxd : out std_ulogic; -- DSU tx data
67 ahbtxd : out std_ulogic; -- DSU tx data
68 dsubre : in std_ulogic;
68 dsubre : in std_ulogic;
69 dsuact : out std_ulogic;
69 dsuact : out std_ulogic;
70 urxd1 : in std_ulogic; -- UART1 rx data
70 urxd1 : in std_ulogic; -- UART1 rx data
71 utxd1 : out std_ulogic; -- UART1 tx data
71 utxd1 : out std_ulogic; -- UART1 tx data
72 errorn : out std_ulogic;
72 errorn : out std_ulogic;
73
73
74 address : out std_logic_vector(18 downto 0);
74 address : out std_logic_vector(18 downto 0);
75 data : inout std_logic_vector(31 downto 0);
75 data : inout std_logic_vector(31 downto 0);
76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
77
77
78 nBWa : out std_logic;
78 nBWa : out std_logic;
79 nBWb : out std_logic;
79 nBWb : out std_logic;
80 nBWc : out std_logic;
80 nBWc : out std_logic;
81 nBWd : out std_logic;
81 nBWd : out std_logic;
82 nBWE : out std_logic;
82 nBWE : out std_logic;
83 nADSC : out std_logic;
83 nADSC : out std_logic;
84 nADSP : out std_logic;
84 nADSP : out std_logic;
85 nADV : out std_logic;
85 nADV : out std_logic;
86 nGW : out std_logic;
86 nGW : out std_logic;
87 nCE1 : out std_logic;
87 nCE1 : out std_logic;
88 CE2 : out std_logic;
88 CE2 : out std_logic;
89 nCE3 : out std_logic;
89 nCE3 : out std_logic;
90 nOE : out std_logic;
90 nOE : out std_logic;
91 MODE : out std_logic;
91 MODE : out std_logic;
92 SSRAM_CLK : out std_logic;
92 SSRAM_CLK : out std_logic;
93 ZZ : out std_logic;
93 ZZ : out std_logic;
94 ---------------------------------------------------------------------
94 ---------------------------------------------------------------------
95 --- AJOUT TEST ------------------------In/Out-----------------------
95 --- AJOUT TEST ------------------------In/Out-----------------------
96 ---------------------------------------------------------------------
96 ---------------------------------------------------------------------
97 -- UART
97 -- UART
98 UART_RXD : in std_logic;
98 UART_RXD : in std_logic;
99 UART_TXD : out std_logic;
99 UART_TXD : out std_logic;
100 -- ACQ
100 -- ACQ
101 CNV_CH1 : OUT STD_LOGIC;
101 CNV_CH1 : OUT STD_LOGIC;
102 SCK_CH1 : OUT STD_LOGIC;
102 SCK_CH1 : OUT STD_LOGIC;
103 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
103 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
104 Bias_Fails : out std_logic;
104 Bias_Fails : out std_logic;
105 -- ADC
105 -- ADC
106 -- ADC_in : in AD7688_in(4 downto 0);
106 -- ADC_in : in AD7688_in(4 downto 0);
107 -- ADC_out : out AD7688_out;
107 -- ADC_out : out AD7688_out;
108
108
109 -- CNA
109 -- CNA
110 -- DAC_SYNC : out std_logic;
110 -- DAC_SYNC : out std_logic;
111 -- DAC_SCLK : out std_logic;
111 -- DAC_SCLK : out std_logic;
112 -- DAC_DATA : out std_logic;
112 -- DAC_DATA : out std_logic;
113 -- Diver
113 -- Diver
114 SPW1_EN : out std_logic;
114 SPW1_EN : out std_logic;
115 SPW2_EN : out std_logic;
115 SPW2_EN : out std_logic;
116 TEST : out std_logic_vector(3 downto 0);
116 TEST : out std_logic_vector(3 downto 0);
117
117
118 BP : in std_logic;
118 BP : in std_logic;
119 ---------------------------------------------------------------------
119 ---------------------------------------------------------------------
120 led : out std_logic_vector(1 downto 0)
120 led : out std_logic_vector(1 downto 0)
121 );
121 );
122 end;
122 end;
123
123
124 architecture Behavioral of leon3mp is
124 architecture Behavioral of leon3mp is
125
125
126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
127 CFG_GRETH+CFG_AHB_JTAG;
127 CFG_GRETH+CFG_AHB_JTAG;
128 constant maxahbm : integer := maxahbmsp;
128 constant maxahbm : integer := maxahbmsp;
129
129
130 --Clk & Rst gοΏ½nοΏ½
130 --Clk & Rst gοΏ½nοΏ½
131 signal vcc : std_logic_vector(4 downto 0);
131 signal vcc : std_logic_vector(4 downto 0);
132 signal gnd : std_logic_vector(4 downto 0);
132 signal gnd : std_logic_vector(4 downto 0);
133 signal resetnl : std_ulogic;
133 signal resetnl : std_ulogic;
134 signal clk2x : std_ulogic;
134 signal clk2x : std_ulogic;
135 signal lclk : std_ulogic;
135 signal lclk : std_ulogic;
136 signal lclk2x : std_ulogic;
136 signal lclk2x : std_ulogic;
137 signal clkm : std_ulogic;
137 signal clkm : std_ulogic;
138 signal rstn : std_ulogic;
138 signal rstn : std_ulogic;
139 signal rstraw : std_ulogic;
139 signal rstraw : std_ulogic;
140 signal pciclk : std_ulogic;
140 signal pciclk : std_ulogic;
141 signal sdclkl : std_ulogic;
141 signal sdclkl : std_ulogic;
142 signal cgi : clkgen_in_type;
142 signal cgi : clkgen_in_type;
143 signal cgo : clkgen_out_type;
143 signal cgo : clkgen_out_type;
144 --- AHB / APB
144 --- AHB / APB
145 signal apbi : apb_slv_in_type;
145 signal apbi : apb_slv_in_type;
146 signal apbo : apb_slv_out_vector := (others => apb_none);
146 signal apbo : apb_slv_out_vector := (others => apb_none);
147 signal ahbsi : ahb_slv_in_type;
147 signal ahbsi : ahb_slv_in_type;
148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
149 signal ahbmi : ahb_mst_in_type;
149 signal ahbmi : ahb_mst_in_type;
150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
151 --UART
151 --UART
152 signal ahbuarti : uart_in_type;
152 signal ahbuarti : uart_in_type;
153 signal ahbuarto : uart_out_type;
153 signal ahbuarto : uart_out_type;
154 signal apbuarti : uart_in_type;
154 signal apbuarti : uart_in_type;
155 signal apbuarto : uart_out_type;
155 signal apbuarto : uart_out_type;
156 --MEM CTRLR
156 --MEM CTRLR
157 signal memi : memory_in_type;
157 signal memi : memory_in_type;
158 signal memo : memory_out_type;
158 signal memo : memory_out_type;
159 signal wpo : wprot_out_type;
159 signal wpo : wprot_out_type;
160 signal sdo : sdram_out_type;
160 signal sdo : sdram_out_type;
161 --IRQ
161 --IRQ
162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
164 --Timer
164 --Timer
165 signal gpti : gptimer_in_type;
165 signal gpti : gptimer_in_type;
166 signal gpto : gptimer_out_type;
166 signal gpto : gptimer_out_type;
167 --GPIO
167 --GPIO
168 signal gpioi : gpio_in_type;
168 signal gpioi : gpio_in_type;
169 signal gpioo : gpio_out_type;
169 signal gpioo : gpio_out_type;
170 --DSU
170 --DSU
171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
173 signal dsui : dsu_in_type;
173 signal dsui : dsu_in_type;
174 signal dsuo : dsu_out_type;
174 signal dsuo : dsu_out_type;
175
175
176 ---------------------------------------------------------------------
176 ---------------------------------------------------------------------
177 --- AJOUT TEST ------------------------Signaux----------------------
177 --- AJOUT TEST ------------------------Signaux----------------------
178 ---------------------------------------------------------------------
178 ---------------------------------------------------------------------
179 -- FIFOs
179 -- FIFOs
180 signal FifoF0_Empty : std_logic_vector(4 downto 0);
180 signal FifoF0_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0_Data : std_logic_vector(79 downto 0);
181 signal FifoF0_Data : std_logic_vector(79 downto 0);
182 signal FifoF1_Empty : std_logic_vector(4 downto 0);
182 signal FifoF1_Empty : std_logic_vector(4 downto 0);
183 signal FifoF1_Data : std_logic_vector(79 downto 0);
183 signal FifoF1_Data : std_logic_vector(79 downto 0);
184 signal FifoF3_Empty : std_logic_vector(4 downto 0);
184 signal FifoF3_Empty : std_logic_vector(4 downto 0);
185 signal FifoF3_Data : std_logic_vector(79 downto 0);
185 signal FifoF3_Data : std_logic_vector(79 downto 0);
186
186
187 signal FifoINT_Full : std_logic_vector(4 downto 0);
187 signal FifoINT_Full : std_logic_vector(4 downto 0);
188 signal FifoINT_Data : std_logic_vector(79 downto 0);
188 signal FifoINT_Data : std_logic_vector(79 downto 0);
189
189
190 signal FifoOUT_Full : std_logic_vector(1 downto 0);
190 signal FifoOUT_Full : std_logic_vector(1 downto 0);
191
191
192 -- MATRICE SPECTRALE
192 -- MATRICE SPECTRALE
193 signal SM_FlagError : std_logic;
193 signal SM_FlagError : std_logic;
194 signal SM_Pong : std_logic;
194 signal SM_Pong : std_logic;
195 signal SM_Read : std_logic_vector(4 downto 0);
195 signal SM_Read : std_logic_vector(4 downto 0);
196 signal SM_Write : std_logic_vector(1 downto 0);
196 signal SM_Write : std_logic_vector(1 downto 0);
197 signal SM_ReUse : std_logic_vector(4 downto 0);
198 signal SM_Param : std_logic_vector(3 downto 0);
197 signal SM_Data : std_logic_vector(63 downto 0);
199 signal SM_Data : std_logic_vector(63 downto 0);
198
200
199 signal Dma_acq : std_logic;
201 signal Dma_acq : std_logic;
200
202
201 -- FFT
203 -- FFT
202 signal FFT_Load : std_logic;
204 signal FFT_Load : std_logic;
203 signal FFT_Read : std_logic_vector(4 downto 0);
205 signal FFT_Read : std_logic_vector(4 downto 0);
204 signal FFT_Write : std_logic_vector(4 downto 0);
206 signal FFT_Write : std_logic_vector(4 downto 0);
205 signal FFT_ReUse : std_logic_vector(4 downto 0);
207 signal FFT_ReUse : std_logic_vector(4 downto 0);
206 signal FFT_Data : std_logic_vector(79 downto 0);
208 signal FFT_Data : std_logic_vector(79 downto 0);
207
209
208 -- DEMUX
210 -- DEMUX
209 signal DEMU_Read : std_logic_vector(14 downto 0);
211 signal DEMU_Read : std_logic_vector(14 downto 0);
210 signal DEMU_Empty : std_logic_vector(4 downto 0);
212 signal DEMU_Empty : std_logic_vector(4 downto 0);
211 signal DEMU_Data : std_logic_vector(79 downto 0);
213 signal DEMU_Data : std_logic_vector(79 downto 0);
212
214
213 -- ACQ
215 -- ACQ
214
215 signal sample_val : STD_LOGIC;
216 signal sample_val : STD_LOGIC;
216 signal sample : Samples(8-1 DOWNTO 0);
217 signal sample : Samples(8-1 DOWNTO 0);
217
218
218 signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
220 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
220 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
222 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
222 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224
225
225 -- ADC
226 -- ADC
226 --signal SmplClk : std_logic;
227 --signal SmplClk : std_logic;
227 --signal ADC_DataReady : std_logic;
228 --signal ADC_DataReady : std_logic;
228 --signal ADC_SmplOut : Samples_out(4 downto 0);
229 --signal ADC_SmplOut : Samples_out(4 downto 0);
229 --signal enableADC : std_logic;
230 --signal enableADC : std_logic;
230 --
231 --
231 --signal WG_Write : std_logic_vector(4 downto 0);
232 --signal WG_Write : std_logic_vector(4 downto 0);
232 --signal WG_ReUse : std_logic_vector(4 downto 0);
233 --signal WG_ReUse : std_logic_vector(4 downto 0);
233 --signal WG_DATA : std_logic_vector(79 downto 0);
234 --signal WG_DATA : std_logic_vector(79 downto 0);
234 --signal s_out : std_logic_vector(79 downto 0);
235 --signal s_out : std_logic_vector(79 downto 0);
235 --
236 --
236 --signal fuller : std_logic_vector(4 downto 0);
237 --signal fuller : std_logic_vector(4 downto 0);
237 --signal reader : std_logic_vector(4 downto 0);
238 --signal reader : std_logic_vector(4 downto 0);
238 --signal try : std_logic_vector(1 downto 0);
239 --signal try : std_logic_vector(1 downto 0);
239 --signal TXDint : std_logic;
240 --signal TXDint : std_logic;
240 --
241 --
241 ---- IIR Filter
242 ---- IIR Filter
242 --signal sample_clk_out : std_logic;
243 --signal sample_clk_out : std_logic;
243 --
244 --
244 --signal Rd : std_logic_vector(0 downto 0);
245 --signal Rd : std_logic_vector(0 downto 0);
245 --signal Ept : std_logic_vector(4 downto 0);
246 --signal Ept : std_logic_vector(4 downto 0);
246 --
247 --
247 --signal Bwr : std_logic_vector(0 downto 0);
248 --signal Bwr : std_logic_vector(0 downto 0);
248 --signal Bre : std_logic_vector(0 downto 0);
249 --signal Bre : std_logic_vector(0 downto 0);
249 --signal DataTMP : std_logic_vector(15 downto 0);
250 --signal DataTMP : std_logic_vector(15 downto 0);
250 --signal FullUp : std_logic_vector(0 downto 0);
251 --signal FullUp : std_logic_vector(0 downto 0);
251 --signal EmptyUp : std_logic_vector(0 downto 0);
252 --signal EmptyUp : std_logic_vector(0 downto 0);
252 --signal FullDown : std_logic_vector(0 downto 0);
253 --signal FullDown : std_logic_vector(0 downto 0);
253 --signal EmptyDown : std_logic_vector(0 downto 0);
254 --signal EmptyDown : std_logic_vector(0 downto 0);
254 ---------------------------------------------------------------------
255 ---------------------------------------------------------------------
255 constant IOAEN : integer := CFG_CAN;
256 constant IOAEN : integer := CFG_CAN;
256 constant boardfreq : integer := 50000;
257 constant boardfreq : integer := 50000;
257
258
258 begin
259 begin
259
260
260 ---------------------------------------------------------------------
261 ---------------------------------------------------------------------
261 --- AJOUT TEST -------------------------------------IPs-------------
262 --- AJOUT TEST -------------------------------------IPs-------------
262 ---------------------------------------------------------------------
263 ---------------------------------------------------------------------
263 led(1 downto 0) <= gpio(1 downto 0);
264 led(1 downto 0) <= gpio(1 downto 0);
264
265
265 --- COM USB ---------------------------------------------------------
266 --- COM USB ---------------------------------------------------------
266 -- MemIn0 : APB_FifoWrite
267 -- MemIn0 : APB_FifoWrite
267 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
268 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
268 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
269 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
269 --
270 --
270 -- BUF0 : APB_USB
271 -- BUF0 : APB_USB
271 -- generic map (6,6,DataMax => 1024)
272 -- generic map (6,6,DataMax => 1024)
272 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
273 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
273 --
274 --
274 -- MemOut0 : APB_FifoRead
275 -- MemOut0 : APB_FifoRead
275 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
276 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
276 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
277 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
277 --
278 --
278 --slrd <= usb_Read;
279 --slrd <= usb_Read;
279 --slwr <= usb_Write;
280 --slwr <= usb_Write;
280
281
281 --- CNA -------------------------------------------------------------
282 --- CNA -------------------------------------------------------------
282
283
283 -- CONV : APB_CNA
284 -- CONV : APB_CNA
284 -- generic map (5,5)
285 -- generic map (5,5)
285 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
286 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
286
287
287 --TEST(0) <= SmplClk;
288 --TEST(0) <= SmplClk;
288 --TEST(1) <= WG_Write(0);
289 --TEST(1) <= WG_Write(0);
289 --TEST(2) <= Fuller(0);
290 --TEST(2) <= Fuller(0);
290 --TEST(3) <= s_out(s_out'length-1);
291 --TEST(3) <= s_out(s_out'length-1);
291
292
292
293
293 --SPW1_EN <= '1';
294 --SPW1_EN <= '1';
294 --SPW2_EN <= '0';
295 --SPW2_EN <= '0';
295
296
296 --- CAN -------------------------------------------------------------
297 --- CAN -------------------------------------------------------------
297
298
298 -- Divider : Clk_divider
299 -- Divider : Clk_divider
299 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
300 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
300 -- Port map(clkm,rstn,SmplClk);
301 -- Port map(clkm,rstn,SmplClk);
301 --
302 --
302 -- ADC : AD7688_drvr
303 -- ADC : AD7688_drvr
303 -- generic map (ChanelCount => 5, clkkHz => 24_576)
304 -- generic map (ChanelCount => 5, clkkHz => 24_576)
304 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
305 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
305 --
306 --
306 -- WG : WriteGen_ADC
307 -- WG : WriteGen_ADC
307 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
308 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
308 --
309 --
309 --enableADC <= gpio(0);
310 --enableADC <= gpio(0);
310
311
311 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
312 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
312 --
313 --
313 --
314 --
314 -- MemIn1 : APB_FIFO
315 -- MemIn1 : APB_FIFO
315 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
316 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
316 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
317 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
317
318
318 DIGITAL_acquisition : ADS7886_drvr
319 -- DIGITAL_acquisition : ADS7886_drvr
319 GENERIC MAP (
320 -- GENERIC MAP (
320 ChanelCount => 8,
321 -- ChanelCount => 8,
321 ncycle_cnv_high => 79,
322 -- ncycle_cnv_high => 79,
322 ncycle_cnv => 500)
323 -- ncycle_cnv => 500)
323 PORT MAP (
324 -- PORT MAP (
324 cnv_clk => clk50MHz, --
325 -- cnv_clk => clk50MHz, --
325 cnv_rstn => rstn, --
326 -- cnv_rstn => rstn, --
326 cnv_run => '1', --
327 -- cnv_run => '1', --
327 cnv => CNV_CH1, --
328 -- cnv => CNV_CH1, --
328 clk => clkm, --
329 -- clk => clkm, --
329 rstn => rstn, --
330 -- rstn => rstn, --
330 sck => SCK_CH1, --
331 -- sck => SCK_CH1, --
331 sdo => SDO_CH1, --
332 -- sdo => SDO_CH1, --
332 sample => sample,
333 -- sample => sample,
333 sample_val => sample_val);
334 -- sample_val => sample_val);
334 --
335 --
335 TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
336 --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
336 TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0);
337 --TopACQ_DataF0 <= E & D & C & B & A;
338
337 --
339 --
338 TEST(0) <= TopACQ_WenF0(1);
340 --TEST(0) <= TopACQ_WenF0(1);
339 TEST(1) <= SDO_CH1(1);
341 --TEST(1) <= SDO_CH1(1);
340 --
341 --
342 --
342 --
343 --process(clkm,rstn)
343 --process(clkm,rstn)
344 --begin
344 --begin
345 -- if(rstn='0')then
345 -- if(rstn='0')then
346 -- TopACQ_WenF0a <= (others => '1');
346 -- TopACQ_WenF0a <= (others => '1');
347 --
347 --
348 -- elsif(clkm'event and clkm='1')then
348 -- elsif(clkm'event and clkm='1')then
349 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
349 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
350 --
350 --
351 -- end if;
351 -- end if;
352 --end process;
352 --end process;
353
353
354 -- TopACQ : lpp_top_acq
354 TopACQ : lpp_top_acq
355 -- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
355 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
356
356
357 Bias_Fails <= '0';
357 Bias_Fails <= '0';
358 --- FIFO IN -------------------------------------------------------------
358 --- FIFO IN -------------------------------------------------------------
359
359
360 MemOut : APB_FIFO
360 -- MemOut : APB_FIFO
361 generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
361 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
362 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
362 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 -- Memf0 : lppFIFOxN
363 Memf0 : lppFIFOxN
364 -- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
364 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 -- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
365 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
366
366
367 Memf1 : lppFIFOxN
367 Memf1 : lppFIFOxN
368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
369 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
369 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
370
370
371 Memf3 : lppFIFOxN
371 Memf3 : lppFIFOxN
372 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
372 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
373 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
373 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
374
374
375 --- DEMUX -------------------------------------------------------------
375 --- DEMUX -------------------------------------------------------------
376
376
377 DEMU0 : DEMUX
377 DEMU0 : DEMUX
378 generic map(Data_sz => 16)
378 generic map(Data_sz => 16)
379 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
379 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
380
380
381 --- FFT -------------------------------------------------------------
381 --- FFT -------------------------------------------------------------
382
382
383 -- MemIn : APB_FIFO
383 -- MemIn : APB_FIFO
384 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
384 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
386
386
387 FFT0 : FFT
387 FFT0 : FFT
388 generic map(Data_sz => 16,NbData => 256)
388 generic map(Data_sz => 16,NbData => 256)
389 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
389 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
390
390
391 ----- LINK MEMORY -------------------------------------------------------
391 ----- LINK MEMORY -------------------------------------------------------
392
392
393 -- MemOut : APB_FIFO
393 -- MemOut : APB_FIFO
394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
395 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
395 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
396
396
397 MemInt : lppFIFOxN
397 MemInt : lppFIFOxN
398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
399 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
399 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
400 --
400 --
401 -- MemIn : APB_FIFO
401 -- MemIn : APB_FIFO
402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
403 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
403 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
404
404
405 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
405 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
406
406
407 SM0 : MatriceSpectrale
407 SM0 : MatriceSpectrale
408 generic map(Input_SZ => 16,Result_SZ => 32)
408 generic map(Input_SZ => 16,Result_SZ => 32)
409 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
409 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
410
410
411 Dma_acq <= '1';
411 Dma_acq <= '1';
412
412
413 -- MemOut : APB_FIFO
413 MemOut : APB_FIFO
414 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
414 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
415 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
415 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
416
416
417 ----- FIFO -------------------------------------------------------------
417 ----- FIFO -------------------------------------------------------------
418
418
419 Memtest : APB_FIFO
419 Memtest : APB_FIFO
420 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
420 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
421 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
421 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
422
422
423 --***************************************TEST DEMI-FIFO********************************************************************************
423 --***************************************TEST DEMI-FIFO********************************************************************************
424 -- MemIn : APB_FIFO
424 -- MemIn : APB_FIFO
425 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
425 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
426 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
426 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
427 --
427 --
428 -- Pont : Bridge
428 -- Pont : Bridge
429 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
429 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
430 --
430 --
431 -- MemOut : APB_FIFO
431 -- MemOut : APB_FIFO
432 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
432 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
433 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
433 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
434 --*************************************************************************************************************************************
434 --*************************************************************************************************************************************
435
435
436 --- UART -------------------------------------------------------------
436 --- UART -------------------------------------------------------------
437
437
438 COM0 : APB_UART
438 COM0 : APB_UART
439 generic map (pindex => 4, paddr => 4)
439 generic map (pindex => 4, paddr => 4)
440 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
440 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
441
441
442 --- DELAY ------------------------------------------------------------
442 --- DELAY ------------------------------------------------------------
443
443
444 -- Delay0 : APB_Delay
444 -- Delay0 : APB_Delay
445 -- generic map (pindex => 4, paddr => 4)
445 -- generic map (pindex => 4, paddr => 4)
446 -- port map (clkm,rstn,apbi,apbo(4));
446 -- port map (clkm,rstn,apbi,apbo(4));
447
447
448 --- IIR Filter -------------------------------------------------------
448 --- IIR Filter -------------------------------------------------------
449 --Test(0) <= sample_clk_out;
449 --Test(0) <= sample_clk_out;
450 --
450 --
451 --
451 --
452 -- IIR1: APB_IIR_Filter
452 -- IIR1: APB_IIR_Filter
453 -- generic map(
453 -- generic map(
454 -- tech => CFG_MEMTECH,
454 -- tech => CFG_MEMTECH,
455 -- pindex => 8,
455 -- pindex => 8,
456 -- paddr => 8,
456 -- paddr => 8,
457 -- Sample_SZ => Sample_SZ,
457 -- Sample_SZ => Sample_SZ,
458 -- ChanelsCount => ChanelsCount,
458 -- ChanelsCount => ChanelsCount,
459 -- Coef_SZ => Coef_SZ,
459 -- Coef_SZ => Coef_SZ,
460 -- CoefCntPerCel => CoefCntPerCel,
460 -- CoefCntPerCel => CoefCntPerCel,
461 -- Cels_count => Cels_count,
461 -- Cels_count => Cels_count,
462 -- virgPos => virgPos
462 -- virgPos => virgPos
463 -- )
463 -- )
464 -- port map(
464 -- port map(
465 -- rst => rstn,
465 -- rst => rstn,
466 -- clk => clkm,
466 -- clk => clkm,
467 -- apbi => apbi,
467 -- apbi => apbi,
468 -- apbo => apbo(8),
468 -- apbo => apbo(8),
469 -- sample_clk_out => sample_clk_out,
469 -- sample_clk_out => sample_clk_out,
470 -- GOtest => Test(1),
470 -- GOtest => Test(1),
471 -- CoefsInitVal => (others => '1')
471 -- CoefsInitVal => (others => '1')
472 -- );
472 -- );
473 ----------------------------------------------------------------------
473 ----------------------------------------------------------------------
474
474
475 ----------------------------------------------------------------------
475 ----------------------------------------------------------------------
476 --- Reset and Clock generation -------------------------------------
476 --- Reset and Clock generation -------------------------------------
477 ----------------------------------------------------------------------
477 ----------------------------------------------------------------------
478
478
479 vcc <= (others => '1'); gnd <= (others => '0');
479 vcc <= (others => '1'); gnd <= (others => '0');
480 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
480 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
481
481
482 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
482 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
483
483
484
484
485 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
485 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
486
486
487 clkgen0 : clkgen -- clock generator
487 clkgen0 : clkgen -- clock generator
488 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
488 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
489 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
489 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
490 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
490 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
491
491
492 ramclk <= clkm;
492 ramclk <= clkm;
493 process(lclk2x)
493 process(lclk2x)
494 begin
494 begin
495 if lclk2x'event and lclk2x = '1' then
495 if lclk2x'event and lclk2x = '1' then
496 lclk <= not lclk;
496 lclk <= not lclk;
497 end if;
497 end if;
498 end process;
498 end process;
499
499
500 ----------------------------------------------------------------------
500 ----------------------------------------------------------------------
501 --- LEON3 processor / DSU / IRQ ------------------------------------
501 --- LEON3 processor / DSU / IRQ ------------------------------------
502 ----------------------------------------------------------------------
502 ----------------------------------------------------------------------
503
503
504 l3 : if CFG_LEON3 = 1 generate
504 l3 : if CFG_LEON3 = 1 generate
505 cpu : for i in 0 to CFG_NCPU-1 generate
505 cpu : for i in 0 to CFG_NCPU-1 generate
506 u0 : leon3s -- LEON3 processor
506 u0 : leon3s -- LEON3 processor
507 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
507 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
508 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
508 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
509 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
509 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
510 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
510 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
511 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
511 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
512 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
512 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
513 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
513 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
514 irqi(i), irqo(i), dbgi(i), dbgo(i));
514 irqi(i), irqo(i), dbgi(i), dbgo(i));
515 end generate;
515 end generate;
516 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
516 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
517
517
518 dsugen : if CFG_DSU = 1 generate
518 dsugen : if CFG_DSU = 1 generate
519 dsu0 : dsu3 -- LEON3 Debug Support Unit
519 dsu0 : dsu3 -- LEON3 Debug Support Unit
520 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
520 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
521 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
521 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
522 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
522 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
523 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
523 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
524 dsui.enable <= '1';
524 dsui.enable <= '1';
525 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
525 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
526 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
526 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
527 end generate;
527 end generate;
528 end generate;
528 end generate;
529
529
530 nodsu : if CFG_DSU = 0 generate
530 nodsu : if CFG_DSU = 0 generate
531 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
531 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
532 end generate;
532 end generate;
533
533
534 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
534 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
535 irqctrl0 : irqmp -- interrupt controller
535 irqctrl0 : irqmp -- interrupt controller
536 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
536 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
537 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
537 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
538 end generate;
538 end generate;
539 irq3 : if CFG_IRQ3_ENABLE = 0 generate
539 irq3 : if CFG_IRQ3_ENABLE = 0 generate
540 x : for i in 0 to CFG_NCPU-1 generate
540 x : for i in 0 to CFG_NCPU-1 generate
541 irqi(i).irl <= "0000";
541 irqi(i).irl <= "0000";
542 end generate;
542 end generate;
543 apbo(2) <= apb_none;
543 apbo(2) <= apb_none;
544 end generate;
544 end generate;
545
545
546 ----------------------------------------------------------------------
546 ----------------------------------------------------------------------
547 --- Memory controllers ---------------------------------------------
547 --- Memory controllers ---------------------------------------------
548 ----------------------------------------------------------------------
548 ----------------------------------------------------------------------
549
549
550 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
550 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
551 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
551 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
552
552
553 memi.brdyn <= '1'; memi.bexcn <= '1';
553 memi.brdyn <= '1'; memi.bexcn <= '1';
554 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
554 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
555
555
556 bdr : for i in 0 to 3 generate
556 bdr : for i in 0 to 3 generate
557 data_pad : iopadv generic map (tech => padtech, width => 8)
557 data_pad : iopadv generic map (tech => padtech, width => 8)
558 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
558 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
559 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
559 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
560 end generate;
560 end generate;
561
561
562
562
563 addr_pad : outpadv generic map (width => 19, tech => padtech)
563 addr_pad : outpadv generic map (width => 19, tech => padtech)
564 port map (address, memo.address(20 downto 2));
564 port map (address, memo.address(20 downto 2));
565
565
566
566
567 SSRAM_0:entity ssram_plugin
567 SSRAM_0:entity ssram_plugin
568 generic map (tech => padtech)
568 generic map (tech => padtech)
569 port map
569 port map
570 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
570 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
571
571
572 ----------------------------------------------------------------------
572 ----------------------------------------------------------------------
573 --- AHB CONTROLLER -------------------------------------------------
573 --- AHB CONTROLLER -------------------------------------------------
574 ----------------------------------------------------------------------
574 ----------------------------------------------------------------------
575
575
576 ahb0 : ahbctrl -- AHB arbiter/multiplexer
576 ahb0 : ahbctrl -- AHB arbiter/multiplexer
577 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
577 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
578 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
578 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
579 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
579 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
580 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
580 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
581
581
582 ----------------------------------------------------------------------
582 ----------------------------------------------------------------------
583 --- AHB UART -------------------------------------------------------
583 --- AHB UART -------------------------------------------------------
584 ----------------------------------------------------------------------
584 ----------------------------------------------------------------------
585
585
586 dcomgen : if CFG_AHB_UART = 1 generate
586 dcomgen : if CFG_AHB_UART = 1 generate
587 dcom0: ahbuart -- Debug UART
587 dcom0: ahbuart -- Debug UART
588 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
588 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
589 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
589 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
590 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
590 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
591 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
591 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
592 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
592 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
593 end generate;
593 end generate;
594 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
594 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
595
595
596 ----------------------------------------------------------------------
596 ----------------------------------------------------------------------
597 --- APB Bridge -----------------------------------------------------
597 --- APB Bridge -----------------------------------------------------
598 ----------------------------------------------------------------------
598 ----------------------------------------------------------------------
599
599
600 apb0 : apbctrl -- AHB/APB bridge
600 apb0 : apbctrl -- AHB/APB bridge
601 generic map (hindex => 1, haddr => CFG_APBADDR)
601 generic map (hindex => 1, haddr => CFG_APBADDR)
602 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
602 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
603
603
604 ----------------------------------------------------------------------
604 ----------------------------------------------------------------------
605 --- GPT Timer ------------------------------------------------------
605 --- GPT Timer ------------------------------------------------------
606 ----------------------------------------------------------------------
606 ----------------------------------------------------------------------
607
607
608 gpt : if CFG_GPT_ENABLE /= 0 generate
608 gpt : if CFG_GPT_ENABLE /= 0 generate
609 timer0 : gptimer -- timer unit
609 timer0 : gptimer -- timer unit
610 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
610 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
611 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
611 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
612 nbits => CFG_GPT_TW)
612 nbits => CFG_GPT_TW)
613 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
613 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
614 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
614 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
615 -- led(4) <= gpto.wdog;
615 -- led(4) <= gpto.wdog;
616 end generate;
616 end generate;
617 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
617 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
618
618
619
619
620 ----------------------------------------------------------------------
620 ----------------------------------------------------------------------
621 --- APB UART -------------------------------------------------------
621 --- APB UART -------------------------------------------------------
622 ----------------------------------------------------------------------
622 ----------------------------------------------------------------------
623
623
624 ua1 : if CFG_UART1_ENABLE /= 0 generate
624 ua1 : if CFG_UART1_ENABLE /= 0 generate
625 uart1 : apbuart -- UART 1
625 uart1 : apbuart -- UART 1
626 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
626 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
627 fifosize => CFG_UART1_FIFO)
627 fifosize => CFG_UART1_FIFO)
628 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
628 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
629 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
629 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
630 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
630 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
631 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
631 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
632 end generate;
632 end generate;
633 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
633 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
634
634
635 ----------------------------------------------------------------------
635 ----------------------------------------------------------------------
636 --- GPIO -----------------------------------------------------------
636 --- GPIO -----------------------------------------------------------
637 ----------------------------------------------------------------------
637 ----------------------------------------------------------------------
638
638
639 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
639 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
640 grgpio0: grgpio
640 grgpio0: grgpio
641 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
641 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
642 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
642 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
643
643
644 pio_pads : for i in 0 to 6 generate
644 pio_pads : for i in 0 to 6 generate
645 pio_pad : iopad generic map (tech => padtech)
645 pio_pad : iopad generic map (tech => padtech)
646 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
646 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
647 end generate;
647 end generate;
648 end generate;
648 end generate;
649
649
650
650
651 end Behavioral; No newline at end of file
651 end Behavioral;
Show file before | Show file after | Hide comments
@@ -1,149 +1,170
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity DEMUX is
26 entity DEMUX is
27 generic(
27 generic(
28 Data_sz : integer range 1 to 32 := 16);
28 Data_sz : integer range 1 to 32 := 16);
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 Read : in std_logic_vector(4 downto 0);
33 Read : in std_logic_vector(4 downto 0);
34 Load : in std_logic;
34 Load : in std_logic;
35
35
36 EmptyF0 : in std_logic_vector(4 downto 0);
36 EmptyF0 : in std_logic_vector(4 downto 0);
37 EmptyF1 : in std_logic_vector(4 downto 0);
37 EmptyF1 : in std_logic_vector(4 downto 0);
38 EmptyF2 : in std_logic_vector(4 downto 0);
38 EmptyF2 : in std_logic_vector(4 downto 0);
39
39
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
43
43
44 WorkFreq : out std_logic_vector(1 downto 0);
44 Read_DEMUX : out std_logic_vector(14 downto 0);
45 Read_DEMUX : out std_logic_vector(14 downto 0);
45 Empty : out std_logic_vector(4 downto 0);
46 Empty : out std_logic_vector(4 downto 0);
46 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
47 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
47 );
48 );
48 end entity;
49 end entity;
49
50
50
51
51 architecture ar_DEMUX of DEMUX is
52 architecture ar_DEMUX of DEMUX is
52
53
53 type etat is (eX,e0,e1,e2,e3);
54 type etat is (eX,e0,e1,e2,e3);
54 signal ect : etat;
55 signal ect : etat;
55
56
56
57
57 signal load_reg : std_logic;
58 signal load_reg : std_logic;
58 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
59 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
59
60
60 signal Countf0 : integer;
61 signal Countf0 : integer;
61 signal Countf1 : integer;
62 signal Countf1 : integer;
63 signal i : integer;
62
64
63 begin
65 begin
64 process(clk,rstn)
66 process(clk,rstn)
65 begin
67 begin
66 if(rstn='0')then
68 if(rstn='0')then
67 ect <= e0;
69 ect <= e0;
68 load_reg <= '0';
70 load_reg <= '0';
69 Countf0 <= 5;
71 Countf0 <= 0;
70 Countf1 <= 0;
72 Countf1 <= 0;
73 i <= 0;
71
74
72 elsif(clk'event and clk='1')then
75 elsif(clk'event and clk='1')then
73 load_reg <= Load;
76 load_reg <= Load;
74
77
75 case ect is
78 case ect is
76
79
77 when e0 =>
80 when e0 =>
78 if(load_reg = '1' and Load = '0')then
81 if(load_reg = '1' and Load = '0')then
79 if(Countf0 = 24)then
82 if(Countf0 = 24)then
80 Countf0 <= 0;
83 Countf0 <= 0;
81 ect <= e1;
84 ect <= e1;
82 else
85 else
83 Countf0 <= Countf0 + 1;
86 Countf0 <= Countf0 + 1;
84 ect <= e0;
87 ect <= e0;
85 end if;
88 end if;
86 end if;
89 end if;
87
90
88 when e1 =>
91 when e1 =>
89 if(load_reg = '1' and Load = '0')then
92 if(load_reg = '1' and Load = '0')then
90 if(Countf1 = 74)then
93 if(Countf1 = 74)then
91 Countf1 <= 0;
94 Countf1 <= 0;
92 ect <= e2;
95 ect <= e2;
93 else
96 else
94 Countf1 <= Countf1 + 1;
97 Countf1 <= Countf1 + 1;
95 ect <= e0;
98 if(i=4)then
99 i <= 0;
100 ect <= e0;
101 else
102 i <= i+1;
103 ect <= e1;
104 end if;
96 end if;
105 end if;
97 end if;
106 end if;
98
107
99 when e2 =>
108 when e2 =>
100 if(load_reg = '1' and Load = '0')then
109 if(load_reg = '1' and Load = '0')then
101 ect <= e0;
110 if(i=4)then
111 i <= 0;
112 ect <= e0;
113 else
114 i <= i+1;
115 ect <= e2;
116 end if;
102 end if;
117 end if;
103
118
104 when others =>
119 when others =>
105 null;
120 null;
106
121
107 end case;
122 end case;
108 end if;
123 end if;
109 end process;
124 end process;
110
125
111 with ect select
126 with ect select
112 Empty <= EmptyF0 when e0,
127 Empty <= EmptyF0 when e0,
113 EmptyF1 when e1,
128 EmptyF1 when e1,
114 EmptyF2 when e2,
129 EmptyF2 when e2,
115 (others => '1') when others;
130 (others => '1') when others;
116
131
117 with ect select
132 with ect select
118 Data <= DataF0 when e0,
133 Data <= DataF0 when e0,
119 DataF1 when e1,
134 DataF1 when e1,
120 DataF2 when e2,
135 DataF2 when e2,
121 (others => '0') when others;
136 (others => '0') when others;
122
137
123 with ect select
138 with ect select
124 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
139 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
125 Dummy_Read & Read & Dummy_Read when e1,
140 Dummy_Read & Read & Dummy_Read when e1,
126 Read & Dummy_Read & Dummy_Read when e2,
141 Read & Dummy_Read & Dummy_Read when e2,
127 (others => '1') when others;
142 (others => '1') when others;
128
143
144 with ect select
145 WorkFreq <= "01" when e0,
146 "10" when e1,
147 "11" when e2,
148 "00" when others;
149
129 end architecture;
150 end architecture;
130
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@@ -1,58 +1,59
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
31
32 package lpp_demux is
32 package lpp_demux is
33
33
34 component DEMUX is
34 component DEMUX is
35 generic(
35 generic(
36 Data_sz : integer range 1 to 32 := 16);
36 Data_sz : integer range 1 to 32 := 16);
37 port(
37 port(
38 clk : in std_logic;
38 clk : in std_logic;
39 rstn : in std_logic;
39 rstn : in std_logic;
40
40
41 Read : in std_logic_vector(4 downto 0);
41 Read : in std_logic_vector(4 downto 0);
42 Load : in std_logic;
42 Load : in std_logic;
43
43
44 EmptyF0 : in std_logic_vector(4 downto 0);
44 EmptyF0 : in std_logic_vector(4 downto 0);
45 EmptyF1 : in std_logic_vector(4 downto 0);
45 EmptyF1 : in std_logic_vector(4 downto 0);
46 EmptyF2 : in std_logic_vector(4 downto 0);
46 EmptyF2 : in std_logic_vector(4 downto 0);
47
47
48 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
48 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
49 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
49 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
51
51
52 WorkFreq : out std_logic_vector(1 downto 0);
52 Read_DEMUX : out std_logic_vector(14 downto 0);
53 Read_DEMUX : out std_logic_vector(14 downto 0);
53 Empty : out std_logic_vector(4 downto 0);
54 Empty : out std_logic_vector(4 downto 0);
54 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
55 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
55 );
56 );
56 end component;
57 end component;
57
58
58 end; No newline at end of file
59 end;
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