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Change ncycle_cnv param of top_ad_conv_ADS7886_v2 (ADC driver) from 250 to 249
pellion -
r300:15500bb8cd46 WaveFormPicker-0-0-F (MINI-LFR) JC
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@@ -1,23 +1,23
1 1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
2 2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3 3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4 4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5 5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6 6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8 8
9 9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10 10
11 11 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
12 12
13 13 vcom -quiet -93 -work lpp testbench_package.vhd
14 14
15 15 vcom -quiet -93 -work work tb_waveform.vhd
16 16
17 17 vsim work.testbench
18 18
19 19 log -r *
20 20
21 do tb_waveform.do
21 do wave_waveform_longsim.do
22 22
23 run -all
23 run 500 ms
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@@ -1,496 +1,591
1 1 ------------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design test bench
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 ------------------------------------------------------------------------------
5 5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 7 --
8 8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 10 -- IN ADVANCE IN WRITING.
11 11 ------------------------------------------------------------------------------
12 12
13 13 LIBRARY ieee;
14 14 USE ieee.std_logic_1164.ALL;
15 15
16 16 --LIBRARY std;
17 17 --USE std.textio.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 LIBRARY gaisler;
23 23 USE gaisler.memctrl.ALL;
24 24 USE gaisler.leon3.ALL;
25 25 USE gaisler.uart.ALL;
26 26 USE gaisler.misc.ALL;
27 27 USE gaisler.libdcom.ALL;
28 28 USE gaisler.sim.ALL;
29 29 USE gaisler.jtagtst.ALL;
30 30 USE gaisler.misc.ALL;
31 31 LIBRARY techmap;
32 32 USE techmap.gencomp.ALL;
33 33 LIBRARY esa;
34 34 USE esa.memoryctrl.ALL;
35 35 --LIBRARY micron;
36 36 --USE micron.components.ALL;
37 37 LIBRARY lpp;
38 38 USE lpp.lpp_waveform_pkg.ALL;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.testbench_package.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL;
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.CY7C1061DV33_pkg.ALL;
46 46
47 47 ENTITY testbench IS
48 48 END;
49 49
50 50 ARCHITECTURE behav OF testbench IS
51 51 -- REG ADDRESS
52 52 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
53 53 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
54 54 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
55 55 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
56 56 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
57 57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
58 58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
59 59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
60 60 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
61 61 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
62 62 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
63 63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
64 64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
65 65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
66 66 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
67 67 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
68 68 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
69 69 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
70 70 -- RAM ADDRESS
71 71 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
72 72 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
73 73 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
74 74 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
75 75
76 76
77 77 -- Common signal
78 78 SIGNAL clk49_152MHz : STD_LOGIC := '0';
79 79 SIGNAL clk25MHz : STD_LOGIC := '0';
80 80 SIGNAL rstn : STD_LOGIC := '0';
81 81
82 82 -- ADC interface
83 83 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
84 84 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
85 85 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
86 86
87 87 -- AD Converter RHF1401
88 88 SIGNAL sample : Samples14v(7 DOWNTO 0);
89 89 SIGNAL sample_val : STD_LOGIC;
90 90
91 91 -- AHB/APB SIGNAL
92 92 SIGNAL apbi : apb_slv_in_type;
93 93 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
94 94 SIGNAL ahbsi : ahb_slv_in_type;
95 95 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
96 96 SIGNAL ahbmi : ahb_mst_in_type;
97 97 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
98 98
99 99 SIGNAL bias_fail_bw : STD_LOGIC;
100 100
101 101 -----------------------------------------------------------------------------
102 102 -- LPP_WAVEFORM
103 103 -----------------------------------------------------------------------------
104 104 CONSTANT data_size : INTEGER := 96;
105 105 CONSTANT nb_burst_available_size : INTEGER := 50;
106 106 CONSTANT nb_snapshot_param_size : INTEGER := 2;
107 107 CONSTANT delta_vector_size : INTEGER := 2;
108 108 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
109 109
110 110 SIGNAL reg_run : STD_LOGIC;
111 111 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
112 112 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 113 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 115 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 116 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 SIGNAL enable_f0 : STD_LOGIC;
118 118 SIGNAL enable_f1 : STD_LOGIC;
119 119 SIGNAL enable_f2 : STD_LOGIC;
120 120 SIGNAL enable_f3 : STD_LOGIC;
121 121 SIGNAL burst_f0 : STD_LOGIC;
122 122 SIGNAL burst_f1 : STD_LOGIC;
123 123 SIGNAL burst_f2 : STD_LOGIC;
124 124 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
125 125 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 126 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 127 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 128 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 129 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
130 130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 132 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 SIGNAL data_f0_in_valid : STD_LOGIC;
134 134 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 135 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 SIGNAL data_f1_in_valid : STD_LOGIC;
137 137 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 139 SIGNAL data_f2_in_valid : STD_LOGIC;
140 140 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 142 SIGNAL data_f3_in_valid : STD_LOGIC;
143 143 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 144 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 145 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 146 SIGNAL data_f0_data_out_valid : STD_LOGIC;
147 147 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
148 148 SIGNAL data_f0_data_out_ack : STD_LOGIC;
149 149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 153 SIGNAL data_f1_data_out_ack : STD_LOGIC;
154 154 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 156 SIGNAL data_f2_data_out_valid : STD_LOGIC;
157 157 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
158 158 SIGNAL data_f2_data_out_ack : STD_LOGIC;
159 159 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 SIGNAL data_f3_data_out_valid : STD_LOGIC;
162 162 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
163 163 SIGNAL data_f3_data_out_ack : STD_LOGIC;
164 164
165 165 --MEM CTRLR
166 166 SIGNAL memi : memory_in_type;
167 167 SIGNAL memo : memory_out_type;
168 168 SIGNAL wpo : wprot_out_type;
169 169 SIGNAL sdo : sdram_out_type;
170 170
171 171 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
172 172 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 173 SIGNAL nSRAM_BE0 : STD_LOGIC;
174 174 SIGNAL nSRAM_BE1 : STD_LOGIC;
175 175 SIGNAL nSRAM_BE2 : STD_LOGIC;
176 176 SIGNAL nSRAM_BE3 : STD_LOGIC;
177 177 SIGNAL nSRAM_WE : STD_LOGIC;
178 178 SIGNAL nSRAM_CE : STD_LOGIC;
179 179 SIGNAL nSRAM_OE : STD_LOGIC;
180 180
181 181 CONSTANT padtech : INTEGER := inferred;
182 182 SIGNAL not_ramsn_0 : STD_LOGIC;
183 183
184 184 -----------------------------------------------------------------------------
185 185 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL read_buffer : STD_LOGIC;
187 187 -----------------------------------------------------------------------------
188 188 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
189 189 SIGNAL state_read_buffer_on_going : STD_LOGIC;
190 CONSTANT hindex : INTEGER := 1;
191 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
192 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
193 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
194 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
195
196 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200
201 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
202 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
203 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
204
205 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
208
209 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
210 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212
213 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
214 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216
217 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
218 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220
221 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
222 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 -----------------------------------------------------------------------------
225
226 SIGNAL current_data : INTEGER;
227 SIGNAL LIMIT_DATA : INTEGER := 194;
228
229 SIGNAL read_buffer_temp : STD_LOGIC;
230 SIGNAL read_buffer_temp_2 : STD_LOGIC;
231
190 232
191 233 BEGIN
192 234
193 235 -----------------------------------------------------------------------------
194 236
195 237 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
196 238 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
197 239
198 240 -----------------------------------------------------------------------------
199 241
200 242 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
201 243 TestModule_RHF1401_1 : TestModule_RHF1401
202 244 GENERIC MAP (
203 245 freq => 24*(I+1),
204 246 amplitude => 8000/(I+1),
205 247 impulsion => 0)
206 248 PORT MAP (
207 249 ADC_smpclk => ADC_smpclk,
208 250 ADC_OEB_bar => ADC_OEB_bar_CH(I),
209 251 ADC_data => ADC_data);
210 252 END GENERATE MODULE_RHF1401;
211 253
212 254 -----------------------------------------------------------------------------
213 255
214 256 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
215 257 GENERIC MAP (
216 258 ChanelCount => 8,
217 259 ncycle_cnv_high => 79,
218 260 ncycle_cnv => 500)
219 261 PORT MAP (
220 262 cnv_clk => clk49_152MHz,
221 263 cnv_rstn => rstn,
222 264 cnv => ADC_smpclk,
223 265 clk => clk25MHz,
224 266 rstn => rstn,
225 267 ADC_data => ADC_data,
226 268 ADC_nOE => ADC_OEB_bar_CH,
227 269 sample => sample,
228 270 sample_val => sample_val);
229 271
230 272 -----------------------------------------------------------------------------
231 273
232 274 lpp_lfr_1 : lpp_lfr
233 275 GENERIC MAP (
234 276 Mem_use => use_CEL, -- use_RAM
235 277 nb_data_by_buffer_size => 32,
236 278 nb_word_by_buffer_size => 30,
237 279 nb_snapshot_param_size => 32,
238 280 delta_vector_size => 32,
239 281 delta_vector_size_f0_2 => 32,
240 282 pindex => INDEX_WAVEFORM_PICKER,
241 283 paddr => ADDR_WAVEFORM_PICKER,
242 284 pmask => 16#fff#,
243 285 pirq_ms => 6,
244 286 pirq_wfp => 14,
245 287 hindex => 0,
246 288 top_lfr_version => X"000001")
247 289 PORT MAP (
248 290 clk => clk25MHz,
249 291 rstn => rstn,
250 292 sample_B => sample(2 DOWNTO 0),
251 293 sample_E => sample(7 DOWNTO 3),
252 294 sample_val => sample_val,
253 295 apbi => apbi,
254 296 apbo => apbo(15),
255 297 ahbi => ahbmi,
256 298 ahbo => ahbmo(0),
257 299 coarse_time => coarse_time,
258 300 fine_time => fine_time,
259 301 data_shaping_BW => bias_fail_bw);
260 302
261 303 -----------------------------------------------------------------------------
262 304 --- AHB CONTROLLER -------------------------------------------------
263 305 ahb0 : ahbctrl -- AHB arbiter/multiplexer
264 306 GENERIC MAP (defmast => 0, split => 0,
265 307 rrobin => 1, ioaddr => 16#FFF#,
266 308 ioen => 0, nahbm => 2, nahbs => 1)
267 309 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
268 310
269 311 --- AHB RAM ----------------------------------------------------------
270 312 --ahbram0 : ahbram
271 313 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
272 314 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
273 315 --ahbram1 : ahbram
274 316 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
275 317 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
276 318 --ahbram2 : ahbram
277 319 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
278 320 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
279 321 --ahbram3 : ahbram
280 322 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
281 323 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
282 324
283 325 -----------------------------------------------------------------------------
284 326 ----------------------------------------------------------------------
285 327 --- Memory controllers ---------------------------------------------
286 328 ----------------------------------------------------------------------
287 329 memctrlr : mctrl GENERIC MAP (
288 330 hindex => 0,
289 331 pindex => 0,
290 332 paddr => 0,
291 333 srbanks => 1
292 334 )
293 335 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
294 336
295 337 memi.brdyn <= '1';
296 338 memi.bexcn <= '1';
297 339 memi.writen <= '1';
298 340 memi.wrn <= "1111";
299 341 memi.bwidth <= "10";
300 342
301 343 bdr : FOR i IN 0 TO 3 GENERATE
302 344 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
303 345 PORT MAP (
304 346 data(31-i*8 DOWNTO 24-i*8),
305 347 memo.data(31-i*8 DOWNTO 24-i*8),
306 348 memo.bdrive(i),
307 349 memi.data(31-i*8 DOWNTO 24-i*8));
308 350 END GENERATE;
309 351
310 352 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
311 353 PORT MAP (address, memo.address(21 DOWNTO 2));
312 354
313 355 not_ramsn_0 <= NOT(memo.ramsn(0));
314 356
315 357 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
316 358 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
317 359 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
318 360 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
319 361 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
320 362 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
321 363 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
322 364
323 365 async_1Mx16_0: CY7C1061DV33
324 366 GENERIC MAP (
325 367 ADDR_BITS => 20,
326 368 DATA_BITS => 16,
327 369 depth => 1048576,
328 370 TimingInfo => TRUE,
329 371 TimingChecks => '1')
330 372 PORT MAP (
331 373 CE1_b => '0',
332 374 CE2 => nSRAM_CE,
333 375 WE_b => nSRAM_WE,
334 376 OE_b => nSRAM_OE,
335 377 BHE_b => nSRAM_BE1,
336 378 BLE_b => nSRAM_BE0,
337 379 A => address,
338 380 DQ => data(15 DOWNTO 0));
339 381
340 382 async_1Mx16_1: CY7C1061DV33
341 383 GENERIC MAP (
342 384 ADDR_BITS => 20,
343 385 DATA_BITS => 16,
344 386 depth => 1048576,
345 387 TimingInfo => TRUE,
346 388 TimingChecks => '1')
347 389 PORT MAP (
348 390 CE1_b => '0',
349 391 CE2 => nSRAM_CE,
350 392 WE_b => nSRAM_WE,
351 393 OE_b => nSRAM_OE,
352 394 BHE_b => nSRAM_BE3,
353 395 BLE_b => nSRAM_BE2,
354 396 A => address,
355 397 DQ => data(31 DOWNTO 16));
356 398
357 399
358 400
359 401 -----------------------------------------------------------------------------
360 402
361 403 WaveGen_Proc : PROCESS
362 404 BEGIN
363 405
364 406 -- insert signal assignments here
365 407 WAIT UNTIL clk25MHz = '1';
366 408 rstn <= '0';
367 409 apbi.psel(15) <= '0';
368 410 apbi.pwrite <= '0';
369 411 apbi.penable <= '0';
370 412 apbi.paddr <= (OTHERS => '0');
371 413 apbi.pwdata <= (OTHERS => '0');
372 414 fine_time <= (OTHERS => '0');
373 415 coarse_time <= (OTHERS => '0');
374 416 WAIT UNTIL clk25MHz = '1';
375 417 -- ahbmi.HGRANT(2) <= '1';
376 418 -- ahbmi.HREADY <= '1';
377 419 -- ahbmi.HRESP <= HRESP_OKAY;
378 420
379 421 WAIT UNTIL clk25MHz = '1';
380 422 WAIT UNTIL clk25MHz = '1';
381 423 rstn <= '1';
382 424 WAIT UNTIL clk25MHz = '1';
383 425 WAIT UNTIL clk25MHz = '1';
384 426 ---------------------------------------------------------------------------
385 427 -- CONFIGURATION STEP
386 428 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
387 429 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
388 430 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
389 431 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
390 432
391 433 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020"
392 434 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
393 435 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
394 436 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
395 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000060");--"00000001"
437 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
396 438
397 439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
398 440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
399 441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
400 442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2");
401 443
402 444
403 445 WAIT UNTIL clk25MHz = '1';
404 446 WAIT UNTIL clk25MHz = '1';
405 447 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
406 448 WAIT UNTIL clk25MHz = '1';
407 449 WAIT UNTIL clk25MHz = '1';
408 450 WAIT UNTIL clk25MHz = '1';
409 451 WAIT UNTIL clk25MHz = '1';
410 452 WAIT UNTIL clk25MHz = '1';
411 453 WAIT UNTIL clk25MHz = '1';
412 454 WAIT FOR 1 us;
413 455 coarse_time <= X"00000001";
414 456
415 457 WAIT UNTIL clk25MHz = '1';
416 458
417 read_buffer <= '0';
418 459 while_loop: WHILE run_test_waveform_picker = '1' LOOP
419 460 WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1';
420 461 APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status);
462
421 463 IF status(2 DOWNTO 0) = "111" THEN
422 464 APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000");
423 read_buffer <= '1';
424 465 END IF;
425 466 WAIT UNTIL clk25MHz = '1';
426 read_buffer <= '0';
427 467 END LOOP while_loop;
428 468
429 469
430 470 ---------------------------------------------------------------------------
431 471 -- RUN STEP
432 472 WAIT FOR 20000 ms;
433 473 REPORT "*** END simulation ***" SEVERITY failure;
434 474 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
435 475 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
436 476 --WAIT FOR 10 us;
437 477 --WAIT UNTIL clk25MHz = '1';
438 478 --WAIT UNTIL clk25MHz = '1';
439 479 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
440 480 --WAIT UNTIL clk25MHz = '1';
441 481 --coarse_time <= X"00000010";
442 482 --WAIT FOR 100 ms;
443 483 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
444 484 --WAIT FOR 10 us;
445 485 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
446 486 --WAIT FOR 200 ms;
447 487 --REPORT "*** END simulation ***" SEVERITY failure;
448 488
449 489
490
450 491 WAIT;
451 492
452 493 END PROCESS WaveGen_Proc;
453 494 -----------------------------------------------------------------------------
454 495
455 -----------------------------------------------------------------------------
456 -- IRQ
457 -----------------------------------------------------------------------------
496 read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0';
458 497 PROCESS (clk25MHz, rstn)
459 498 BEGIN -- PROCESS
460 499 IF rstn = '0' THEN -- asynchronous reset (active low)
500 read_buffer <= '0';
501 read_buffer_temp_2 <= '0';
502 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
503 read_buffer_temp_2 <= read_buffer_temp;
504 read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2;
505 END IF;
506 END PROCESS;
507
508 -----------------------------------------------------------------------------
509 -- IRQ
510 -----------------------------------------------------------------------------
511 PROCESS
512 BEGIN -- PROCESS
461 513 state_read_buffer_on_going <= '0';
462 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
514 current_data <= 0;
515 time_mem_f0 <= (OTHERS => '0');
516 time_mem_f1 <= (OTHERS => '0');
517 time_mem_f2 <= (OTHERS => '0');
518 time_mem_f3 <= (OTHERS => '0');
519 data_mem_f0 <= (OTHERS => '0');
520 data_mem_f1 <= (OTHERS => '0');
521 data_mem_f2 <= (OTHERS => '0');
522 data_mem_f3 <= (OTHERS => '0');
523
524 while_loop2: WHILE run_test_waveform_picker = '1' LOOP
525 WAIT UNTIL clk25MHz = '1';
463 526 IF read_buffer = '1' THEN
464 527 state_read_buffer_on_going <= '1';
465 528
466 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000", time_mem_f0(31 DOWNTO 0));
467 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000", time_mem_f1(31 DOWNTO 0));
468 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000", time_mem_f2(31 DOWNTO 0));
469 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000", time_mem_f3(31 DOWNTO 0));
529 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
530 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
531 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0));
470 532
471 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000004", time_mem_f0(63 DOWNTO 32));
472 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020004", time_mem_f1(63 DOWNTO 32));
473 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040004", time_mem_f2(63 DOWNTO 32));
474 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060004", time_mem_f3(63 DOWNTO 32));
533 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32));
534 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
535 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
475 536
476 537 current_data <= 8;
477 538 ELSE
478 539 IF state_read_buffer_on_going = '1' THEN
479 540 -- READ ALL DATA in memory
480 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000" + current_data, data_mem_f0);
481 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000" + current_data, data_mem_f1);
482 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000" + current_data, data_mem_f2);
483 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000" + current_data, data_mem_f3);
484 IF current_data < LIMIT_DATA THEN
541 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
542 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
543 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
544 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
545 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
546 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
547 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
548 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
549 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
550 current_data <= current_data + 4;
551
552 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
553 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
554 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
555 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
556 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
557 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
558 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
559 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
560 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
561 current_data <= current_data + 4;
485 562
563 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
564 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
565 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
566 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
567 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
568 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
569 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
570 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
571 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
486 572 current_data <= current_data + 4;
487 ELSE
573
574 IF current_data > LIMIT_DATA THEN
488 575 state_read_buffer_on_going <= '0';
576 time_mem_f0 <= (OTHERS => '0');
577 time_mem_f1 <= (OTHERS => '0');
578 time_mem_f2 <= (OTHERS => '0');
579 time_mem_f3 <= (OTHERS => '0');
580 data_mem_f0 <= (OTHERS => '0');
581 data_mem_f1 <= (OTHERS => '0');
582 data_mem_f2 <= (OTHERS => '0');
583 data_mem_f3 <= (OTHERS => '0');
489 584 END IF;
490 585 END IF;
491 586 END IF;
492 END IF;
587 END LOOP while_loop2;
493 588 END PROCESS;
494 589 -----------------------------------------------------------------------------
495 590
496 591 END;
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@@ -1,105 +1,120
1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6 USE grlib.stdlib.ALL;
7 7 --LIBRARY gaisler;
8 8 --USE gaisler.libdcom.ALL;
9 9 --USE gaisler.sim.ALL;
10 10 --USE gaisler.jtagtst.ALL;
11 11 --LIBRARY techmap;
12 12 --USE techmap.gencomp.ALL;
13 13
14 14
15 15 PACKAGE testbench_package IS
16 16
17 17 PROCEDURE APB_WRITE (
18 18 SIGNAL clk : IN STD_LOGIC;
19 19 CONSTANT pindex : IN INTEGER;
20 20 SIGNAL apbi : OUT apb_slv_in_type;
21 21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
23 23 );
24 24
25 25 PROCEDURE APB_READ (
26 26 SIGNAL clk : IN STD_LOGIC;
27 27 CONSTANT pindex : IN INTEGER;
28 28 SIGNAL apbi : OUT apb_slv_in_type;
29 29 SIGNAL apbo : IN apb_slv_out_type;
30 30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
32 32 );
33 33
34 34 PROCEDURE AHB_READ (
35 35 SIGNAL clk : IN STD_LOGIC;
36 CONSTANT hindex : IN INTEGER
37 SIGNAL ahbmi : OUT ahb_slv_in_type;
38 SIGNAL ahbmo : IN ahb_slv_out_type;
36 CONSTANT hindex : IN INTEGER;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
39 39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
41 41 );
42 42
43 43 END testbench_package;
44 44
45 45 PACKAGE BODY testbench_package IS
46 46
47 47 PROCEDURE APB_WRITE (
48 48 SIGNAL clk : IN STD_LOGIC;
49 49 CONSTANT pindex : IN INTEGER;
50 50 SIGNAL apbi : OUT apb_slv_in_type;
51 51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 53 ) IS
54 54 BEGIN
55 55 apbi.psel(pindex) <= '1';
56 56 apbi.pwrite <= '1';
57 57 apbi.penable <= '1';
58 58 apbi.paddr <= paddr;
59 59 apbi.pwdata <= pwdata;
60 60 WAIT UNTIL clk = '1';
61 61 apbi.psel(pindex) <= '0';
62 62 apbi.pwrite <= '0';
63 63 apbi.penable <= '0';
64 64 apbi.paddr <= (OTHERS => '0');
65 65 apbi.pwdata <= (OTHERS => '0');
66 WAIT UNTIL clk = '1';
66 67
67 68 END APB_WRITE;
68 69
69 70 PROCEDURE APB_READ (
70 71 SIGNAL clk : IN STD_LOGIC;
71 72 CONSTANT pindex : IN INTEGER;
72 73 SIGNAL apbi : OUT apb_slv_in_type;
73 74 SIGNAL apbo : IN apb_slv_out_type;
74 75 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 76 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
76 77 ) IS
77 78 BEGIN
78 79 apbi.psel(pindex) <= '1';
79 80 apbi.pwrite <= '0';
80 81 apbi.penable <= '1';
81 82 apbi.paddr <= paddr;
82 83 WAIT UNTIL clk = '1';
83 84 apbi.psel(pindex) <= '0';
84 85 apbi.pwrite <= '0';
85 86 apbi.penable <= '0';
86 87 apbi.paddr <= (OTHERS => '0');
87 88 WAIT UNTIL clk = '1';
88 89 prdata <= apbo.prdata;
89 90 END APB_READ;
90 91
91 92 PROCEDURE AHB_READ (
92 93 SIGNAL clk : IN STD_LOGIC;
93 CONSTANT hindex : IN INTEGER
94 SIGNAL ahbmi : OUT ahb_slv_in_type;
95 SIGNAL ahbmo : IN ahb_slv_out_type;
94 CONSTANT hindex : IN INTEGER;
95 SIGNAL ahbmi : IN ahb_mst_in_type;
96 SIGNAL ahbmo : OUT ahb_mst_out_type;
96 97 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 98 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
98 99 ) IS
99 100 BEGIN
100
101 ahbmo.HADDR <= haddr;
102 ahbmo.HPROT <= "0011";
103 ahbmo.HIRQ <= (OTHERS => '0');
104 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
105 ahbmo.HINDEX <= hindex;
106 ahbmo.HBUSREQ <= '1';
107 ahbmo.HLOCK <= '1';
108 ahbmo.HSIZE <= HSIZE_WORD;
109 ahbmo.HBURST <= HBURST_SINGLE;
110 ahbmo.HTRANS <= HTRANS_NONSEQ;
111 ahbmo.HWRITE <= '0';
112 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
113 hrdata <= ahbmi.HRDATA;
114 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
115 ahbmo.HTRANS <= HTRANS_IDLE;
116 ahbmo.HBUSREQ <= '0';
117 ahbmo.HLOCK <= '0';
101 118 END AHB_READ;
102 119
103
104
105 120 END testbench_package;
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@@ -1,580 +1,580
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_val : STD_LOGIC;
167 167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 170
171 171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 172
173 173 -----------------------------------------------------------------------------
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175
176 176 BEGIN -- beh
177 177
178 178 -----------------------------------------------------------------------------
179 179 -- CLK
180 180 -----------------------------------------------------------------------------
181 181
182 182 PROCESS(clk_50)
183 183 BEGIN
184 184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 185 clk_50_s <= NOT clk_50_s;
186 186 END IF;
187 187 END PROCESS;
188 188
189 189 PROCESS(clk_50_s)
190 190 BEGIN
191 191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 192 clk_25 <= NOT clk_25;
193 193 END IF;
194 194 END PROCESS;
195 195
196 196 PROCESS(clk_49)
197 197 BEGIN
198 198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 199 clk_24 <= NOT clk_24;
200 200 END IF;
201 201 END PROCESS;
202 202
203 203 -----------------------------------------------------------------------------
204 204
205 205 PROCESS (clk_25, reset)
206 206 BEGIN -- PROCESS
207 207 IF reset = '0' THEN -- asynchronous reset (active low)
208 208 LED0 <= '0';
209 209 LED1 <= '0';
210 210 LED2 <= '0';
211 211 --IO1 <= '0';
212 212 --IO2 <= '1';
213 213 --IO3 <= '0';
214 214 --IO4 <= '0';
215 215 --IO5 <= '0';
216 216 --IO6 <= '0';
217 217 --IO7 <= '0';
218 218 --IO8 <= '0';
219 219 --IO9 <= '0';
220 220 --IO10 <= '0';
221 221 --IO11 <= '0';
222 222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 223 LED0 <= '0';
224 224 LED1 <= '1';
225 225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 226 --IO1 <= '1';
227 227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 228 --IO3 <= ADC_SDO(0);
229 229 --IO4 <= ADC_SDO(1);
230 230 --IO5 <= ADC_SDO(2);
231 231 --IO6 <= ADC_SDO(3);
232 232 --IO7 <= ADC_SDO(4);
233 233 --IO8 <= ADC_SDO(5);
234 234 --IO9 <= ADC_SDO(6);
235 235 --IO10 <= ADC_SDO(7);
236 236 --IO11 <= ;
237 237 END IF;
238 238 END PROCESS;
239 239
240 240 PROCESS (clk_24, reset)
241 241 BEGIN -- PROCESS
242 242 IF reset = '0' THEN -- asynchronous reset (active low)
243 243 I00_s <= '0';
244 244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 245 I00_s <= NOT I00_s;
246 246 END IF;
247 247 END PROCESS;
248 248 -- IO0 <= I00_s;
249 249
250 250 --UARTs
251 251 nCTS1 <= '1';
252 252 nCTS2 <= '1';
253 253 nDCD2 <= '1';
254 254
255 255 --EXT CONNECTOR
256 256
257 257 --SPACE WIRE
258 258
259 259 leon3_soc_1 : leon3_soc
260 260 GENERIC MAP (
261 261 fabtech => apa3e,
262 262 memtech => apa3e,
263 263 padtech => inferred,
264 264 clktech => inferred,
265 265 disas => 0,
266 266 dbguart => 0,
267 267 pclow => 2,
268 268 clk_freq => 25000,
269 269 NB_CPU => 1,
270 270 ENABLE_FPU => 1,
271 271 FPU_NETLIST => 0,
272 272 ENABLE_DSU => 1,
273 273 ENABLE_AHB_UART => 1,
274 274 ENABLE_APB_UART => 1,
275 275 ENABLE_IRQMP => 1,
276 276 ENABLE_GPT => 1,
277 277 NB_AHB_MASTER => NB_AHB_MASTER,
278 278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 279 NB_APB_SLAVE => NB_APB_SLAVE)
280 280 PORT MAP (
281 281 clk => clk_25,
282 282 reset => reset,
283 283 errorn => errorn,
284 284 ahbrxd => TXD1,
285 285 ahbtxd => RXD1,
286 286 urxd1 => TXD2,
287 287 utxd1 => RXD2,
288 288 address => SRAM_A,
289 289 data => SRAM_DQ,
290 290 nSRAM_BE0 => SRAM_nBE(0),
291 291 nSRAM_BE1 => SRAM_nBE(1),
292 292 nSRAM_BE2 => SRAM_nBE(2),
293 293 nSRAM_BE3 => SRAM_nBE(3),
294 294 nSRAM_WE => SRAM_nWE,
295 295 nSRAM_CE => SRAM_CE,
296 296 nSRAM_OE => SRAM_nOE,
297 297
298 298 apbi_ext => apbi_ext,
299 299 apbo_ext => apbo_ext,
300 300 ahbi_s_ext => ahbi_s_ext,
301 301 ahbo_s_ext => ahbo_s_ext,
302 302 ahbi_m_ext => ahbi_m_ext,
303 303 ahbo_m_ext => ahbo_m_ext);
304 304
305 305 -------------------------------------------------------------------------------
306 306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 307 -------------------------------------------------------------------------------
308 308 apb_lfr_time_management_1 : apb_lfr_time_management
309 309 GENERIC MAP (
310 310 pindex => 6,
311 311 paddr => 6,
312 312 pmask => 16#fff#,
313 313 pirq => 12,
314 314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
315 315 PORT MAP (
316 316 clk25MHz => clk_25,
317 317 clk49_152MHz => clk_24, -- 49.152MHz/2
318 318 resetn => reset,
319 319 grspw_tick => swno.tickout,
320 320 apbi => apbi_ext,
321 321 apbo => apbo_ext(6),
322 322 coarse_time => coarse_time,
323 323 fine_time => fine_time);
324 324
325 325 -----------------------------------------------------------------------
326 326 --- SpaceWire --------------------------------------------------------
327 327 -----------------------------------------------------------------------
328 328
329 329 SPW_EN <= '1';
330 330
331 331 spw_clk <= clk_50_s;
332 332 spw_rxtxclk <= spw_clk;
333 333 spw_rxclkn <= NOT spw_rxtxclk;
334 334
335 335 -- PADS for SPW1
336 336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 344 -- PADS FOR SPW2
345 345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 348 PORT MAP (SPW_RED_DIN, stmp(1));
349 349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 353
354 354 -- GRSPW PHY
355 355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 357 spw_phy0 : grspw_phy
358 358 GENERIC MAP(
359 359 tech => apa3e,
360 360 rxclkbuftype => 1,
361 361 scantest => 0)
362 362 PORT MAP(
363 363 rxrst => swno.rxrst,
364 364 di => dtmp(j),
365 365 si => stmp(j),
366 366 rxclko => spw_rxclk(j),
367 367 do => swni.d(j),
368 368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 370 END GENERATE spw_inputloop;
371 371
372 372 -- SPW core
373 373 sw0 : grspwm GENERIC MAP(
374 374 tech => apa3e,
375 375 hindex => 1,
376 376 pindex => 5,
377 377 paddr => 5,
378 378 pirq => 11,
379 379 sysfreq => 25000, -- CPU_FREQ
380 380 rmap => 1,
381 381 rmapcrc => 1,
382 382 fifosize1 => 16,
383 383 fifosize2 => 16,
384 384 rxclkbuftype => 1,
385 385 rxunaligned => 0,
386 386 rmapbufs => 4,
387 387 ft => 0,
388 388 netlist => 0,
389 389 ports => 2,
390 390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 391 memtech => apa3e,
392 392 destkey => 2,
393 393 spwcore => 1
394 394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 397 )
398 398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 401 swni, swno);
402 402
403 403 swni.tickin <= '0';
404 404 swni.rmapen <= '1';
405 405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 406 swni.tickinraw <= '0';
407 407 swni.timein <= (OTHERS => '0');
408 408 swni.dcrstval <= (OTHERS => '0');
409 409 swni.timerrstval <= (OTHERS => '0');
410 410
411 411 -------------------------------------------------------------------------------
412 412 -- LFR ------------------------------------------------------------------------
413 413 -------------------------------------------------------------------------------
414 414 lpp_lfr_1 : lpp_lfr
415 415 GENERIC MAP (
416 416 Mem_use => use_RAM,
417 417 nb_data_by_buffer_size => 32,
418 418 nb_word_by_buffer_size => 30,
419 419 nb_snapshot_param_size => 32,
420 420 delta_vector_size => 32,
421 421 delta_vector_size_f0_2 => 7, -- log2(96)
422 422 pindex => 15,
423 423 paddr => 15,
424 424 pmask => 16#fff#,
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"00000E") -- aa.bb.cc version
428 top_lfr_version => X"00000F") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
432 432 sample_B => sample(2 DOWNTO 0),
433 433 sample_E => sample(7 DOWNTO 3),
434 434 sample_val => sample_val,
435 435 apbi => apbi_ext,
436 436 apbo => apbo_ext(15),
437 437 ahbi => ahbi_m_ext,
438 438 ahbo => ahbo_m_ext(2),
439 439 coarse_time => coarse_time,
440 440 fine_time => fine_time,
441 441 data_shaping_BW => bias_fail_sw_sig,
442 442 observation_reg => observation_reg);
443 443
444 444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 445 GENERIC MAP(
446 446 ChannelCount => 8,
447 447 SampleNbBits => 14,
448 448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 450 PORT MAP (
451 451 -- CONV
452 452 cnv_clk => clk_24,
453 453 cnv_rstn => reset,
454 454 cnv => ADC_nCS_sig,
455 455 -- DATA
456 456 clk => clk_25,
457 457 rstn => reset,
458 458 sck => ADC_CLK_sig,
459 459 sdo => ADC_SDO_sig,
460 460 -- SAMPLE
461 461 sample => sample,
462 462 sample_val => sample_val);
463 463
464 464 --IO10 <= ADC_SDO_sig(5);
465 465 --IO9 <= ADC_SDO_sig(4);
466 466 --IO8 <= ADC_SDO_sig(3);
467 467
468 468 ADC_nCS <= ADC_nCS_sig;
469 469 ADC_CLK <= ADC_CLK_sig;
470 470 ADC_SDO_sig <= ADC_SDO;
471 471
472 472 ----------------------------------------------------------------------
473 473 --- GPIO -----------------------------------------------------------
474 474 ----------------------------------------------------------------------
475 475
476 476 grgpio0 : grgpio
477 477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479 479
480 480 --pio_pad_0 : iopad
481 481 -- GENERIC MAP (tech => CFG_PADTECH)
482 482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 483 --pio_pad_1 : iopad
484 484 -- GENERIC MAP (tech => CFG_PADTECH)
485 485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 486 --pio_pad_2 : iopad
487 487 -- GENERIC MAP (tech => CFG_PADTECH)
488 488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 489 --pio_pad_3 : iopad
490 490 -- GENERIC MAP (tech => CFG_PADTECH)
491 491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 492 --pio_pad_4 : iopad
493 493 -- GENERIC MAP (tech => CFG_PADTECH)
494 494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 495 --pio_pad_5 : iopad
496 496 -- GENERIC MAP (tech => CFG_PADTECH)
497 497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 498 --pio_pad_6 : iopad
499 499 -- GENERIC MAP (tech => CFG_PADTECH)
500 500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 501 --pio_pad_7 : iopad
502 502 -- GENERIC MAP (tech => CFG_PADTECH)
503 503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504 504
505 505 PROCESS (clk_25, reset)
506 506 BEGIN -- PROCESS
507 507 IF reset = '0' THEN -- asynchronous reset (active low)
508 508 IO0 <= '0';
509 509 IO1 <= '0';
510 510 IO2 <= '0';
511 511 IO3 <= '0';
512 512 IO4 <= '0';
513 513 IO5 <= '0';
514 514 IO6 <= '0';
515 515 IO7 <= '0';
516 516 IO8 <= '0';
517 517 IO9 <= '0';
518 518 IO10 <= '0';
519 519 IO11 <= '0';
520 520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 521 CASE gpioo.dout(1 DOWNTO 0) IS
522 522 WHEN "00" =>
523 523 IO0 <= observation_reg(0 );
524 524 IO1 <= observation_reg(1 );
525 525 IO2 <= observation_reg(2 );
526 526 IO3 <= observation_reg(3 );
527 527 IO4 <= observation_reg(4 );
528 528 IO5 <= observation_reg(5 );
529 529 IO6 <= observation_reg(6 );
530 530 IO7 <= observation_reg(7 );
531 531 IO8 <= observation_reg(8 );
532 532 IO9 <= observation_reg(9 );
533 533 IO10 <= observation_reg(10);
534 534 IO11 <= observation_reg(11);
535 535 WHEN "01" =>
536 536 IO0 <= observation_reg(0 + 12);
537 537 IO1 <= observation_reg(1 + 12);
538 538 IO2 <= observation_reg(2 + 12);
539 539 IO3 <= observation_reg(3 + 12);
540 540 IO4 <= observation_reg(4 + 12);
541 541 IO5 <= observation_reg(5 + 12);
542 542 IO6 <= observation_reg(6 + 12);
543 543 IO7 <= observation_reg(7 + 12);
544 544 IO8 <= observation_reg(8 + 12);
545 545 IO9 <= observation_reg(9 + 12);
546 546 IO10 <= observation_reg(10 + 12);
547 547 IO11 <= observation_reg(11 + 12);
548 548 WHEN "10" =>
549 549 IO0 <= observation_reg(0 + 12 + 12);
550 550 IO1 <= observation_reg(1 + 12 + 12);
551 551 IO2 <= observation_reg(2 + 12 + 12);
552 552 IO3 <= observation_reg(3 + 12 + 12);
553 553 IO4 <= observation_reg(4 + 12 + 12);
554 554 IO5 <= observation_reg(5 + 12 + 12);
555 555 IO6 <= observation_reg(6 + 12 + 12);
556 556 IO7 <= observation_reg(7 + 12 + 12);
557 557 IO8 <= '0';
558 558 IO9 <= '0';
559 559 IO10 <= '0';
560 560 IO11 <= '0';
561 561 WHEN "11" =>
562 562 IO0 <= '0';
563 563 IO1 <= '0';
564 564 IO2 <= '0';
565 565 IO3 <= '0';
566 566 IO4 <= '0';
567 567 IO5 <= '0';
568 568 IO6 <= '0';
569 569 IO7 <= '0';
570 570 IO8 <= '0';
571 571 IO9 <= '0';
572 572 IO10 <= '0';
573 573 IO11 <= '0';
574 574 WHEN OTHERS => NULL;
575 575 END CASE;
576 576
577 577 END IF;
578 578 END PROCESS;
579 579
580 580 END beh; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_waveform IS
40 40
41 41 GENERIC (
42 42 tech : INTEGER := inferred;
43 43 data_size : INTEGER := 96; --16*6
44 44 nb_data_by_buffer_size : INTEGER := 11;
45 45 nb_word_by_buffer_size : INTEGER := 11;
46 46 nb_snapshot_param_size : INTEGER := 11;
47 47 delta_vector_size : INTEGER := 20;
48 48 delta_vector_size_f0_2 : INTEGER := 3);
49 49
50 50 PORT (
51 51 clk : IN STD_LOGIC;
52 52 rstn : IN STD_LOGIC;
53 53
54 54 ---- AMBA AHB Master Interface
55 55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57 57
58 58 --config
59 59 reg_run : IN STD_LOGIC;
60 60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 66
67 67 enable_f0 : IN STD_LOGIC;
68 68 enable_f1 : IN STD_LOGIC;
69 69 enable_f2 : IN STD_LOGIC;
70 70 enable_f3 : IN STD_LOGIC;
71 71
72 72 burst_f0 : IN STD_LOGIC;
73 73 burst_f1 : IN STD_LOGIC;
74 74 burst_f2 : IN STD_LOGIC;
75 75
76 76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83 ---------------------------------------------------------------------------
84 84 -- INPUT
85 85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87 87
88 88 --f0
89 89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 data_f0_in_valid : IN STD_LOGIC;
91 91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 92 --f1
93 93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 data_f1_in_valid : IN STD_LOGIC;
95 95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 96 --f2
97 97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 data_f2_in_valid : IN STD_LOGIC;
99 99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 100 --f3
101 101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 data_f3_in_valid : IN STD_LOGIC;
103 103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 104
105 105 ---------------------------------------------------------------------------
106 106 -- OUTPUT
107 107 --f0
108 108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 data_f0_data_out_valid : OUT STD_LOGIC;
111 111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 112 data_f0_data_out_ren : IN STD_LOGIC;
113 113 --f1
114 114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 116 data_f1_data_out_valid : OUT STD_LOGIC;
117 117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 118 data_f1_data_out_ren : IN STD_LOGIC;
119 119 --f2
120 120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 data_f2_data_out_valid : OUT STD_LOGIC;
123 123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 124 data_f2_data_out_ren : IN STD_LOGIC;
125 125 --f3
126 126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 data_f3_data_out_valid : OUT STD_LOGIC;
129 129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 130 data_f3_data_out_ren : IN STD_LOGIC;
131 131
132 132 ---------------------------------------------------------------------------
133 133 --
134 134 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
135 135
136 136
137 137 ----debug SNAPSHOT OUT
138 138 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 139 --debug_f0_data_valid : OUT STD_LOGIC;
140 140 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 --debug_f1_data_valid : OUT STD_LOGIC;
142 142 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 143 --debug_f2_data_valid : OUT STD_LOGIC;
144 144 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 145 --debug_f3_data_valid : OUT STD_LOGIC;
146 146
147 147 ----debug FIFO IN
148 148 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 149 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
150 150 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 151 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
152 152 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
154 154 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
156 156
157 157 );
158 158
159 159 END lpp_waveform;
160 160
161 161 ARCHITECTURE beh OF lpp_waveform IS
162 162 SIGNAL start_snapshot_f0 : STD_LOGIC;
163 163 SIGNAL start_snapshot_f1 : STD_LOGIC;
164 164 SIGNAL start_snapshot_f2 : STD_LOGIC;
165 165
166 166 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
167 167 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 168 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 169 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 170
171 171 SIGNAL data_f0_out_valid : STD_LOGIC;
172 172 SIGNAL data_f1_out_valid : STD_LOGIC;
173 173 SIGNAL data_f2_out_valid : STD_LOGIC;
174 174 SIGNAL data_f3_out_valid : STD_LOGIC;
175 175 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
176 176 --
177 177 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 178 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 179 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 180 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 181 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 182 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 184 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 185 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 187 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 188 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 189 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 190 --
191 191 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 192 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 193 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 194 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 195 --
196 196 SIGNAL run : STD_LOGIC;
197 197 --
198 198 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
199 199 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
200 200 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
201 201 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
202 202 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
203 203 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 204 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 205 --
206 206
207 207 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
208 208 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 209 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 210 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 211
212 212 --
213 213
214 214 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 215 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 216
217 217 BEGIN -- beh
218 218
219 219 -----------------------------------------------------------------------------
220 220 -- DEBUG
221 221 -----------------------------------------------------------------------------
222 222 PROCESS (clk, rstn)
223 223 BEGIN -- PROCESS
224 224 IF rstn = '0' THEN -- asynchronous reset (active low)
225 225 observation_reg <= (OTHERS => '0');
226 226 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
227 227 observation_reg <= observation_reg_s;
228 228 END IF;
229 229 END PROCESS;
230 230 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
231 231 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
232 232 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
233 233 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
234 234 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
235 235 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
236 236 -----------------------------------------------------------------------------
237 237
238 238 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
239 239 GENERIC MAP (
240 240 delta_vector_size => delta_vector_size,
241 241 delta_vector_size_f0_2 => delta_vector_size_f0_2
242 242 )
243 243 PORT MAP (
244 244 clk => clk,
245 245 rstn => rstn,
246 246 reg_run => reg_run,
247 247 reg_start_date => reg_start_date,
248 248 reg_delta_snapshot => reg_delta_snapshot,
249 249 reg_delta_f0 => reg_delta_f0,
250 250 reg_delta_f0_2 => reg_delta_f0_2,
251 251 reg_delta_f1 => reg_delta_f1,
252 252 reg_delta_f2 => reg_delta_f2,
253 253 coarse_time => coarse_time(30 DOWNTO 0),
254 254 data_f0_valid => data_f0_in_valid,
255 255 data_f2_valid => data_f2_in_valid,
256 256 start_snapshot_f0 => start_snapshot_f0,
257 257 start_snapshot_f1 => start_snapshot_f1,
258 258 start_snapshot_f2 => start_snapshot_f2,
259 259 wfp_on => run);
260 260
261 261 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
262 262 GENERIC MAP (
263 263 data_size => data_size,
264 264 nb_snapshot_param_size => nb_snapshot_param_size)
265 265 PORT MAP (
266 266 clk => clk,
267 267 rstn => rstn,
268 268 run => run,
269 269 enable => enable_f0,
270 270 burst_enable => burst_f0,
271 271 nb_snapshot_param => nb_snapshot_param,
272 272 start_snapshot => start_snapshot_f0,
273 273 data_in => data_f0_in,
274 274 data_in_valid => data_f0_in_valid,
275 275 data_out => data_f0_out,
276 276 data_out_valid => data_f0_out_valid);
277 277
278 278 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
279 279
280 280 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
281 281 GENERIC MAP (
282 282 data_size => data_size,
283 283 nb_snapshot_param_size => nb_snapshot_param_size+1)
284 284 PORT MAP (
285 285 clk => clk,
286 286 rstn => rstn,
287 287 run => run,
288 288 enable => enable_f1,
289 289 burst_enable => burst_f1,
290 290 nb_snapshot_param => nb_snapshot_param_more_one,
291 291 start_snapshot => start_snapshot_f1,
292 292 data_in => data_f1_in,
293 293 data_in_valid => data_f1_in_valid,
294 294 data_out => data_f1_out,
295 295 data_out_valid => data_f1_out_valid);
296 296
297 297 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
298 298 GENERIC MAP (
299 299 data_size => data_size,
300 300 nb_snapshot_param_size => nb_snapshot_param_size+1)
301 301 PORT MAP (
302 302 clk => clk,
303 303 rstn => rstn,
304 304 run => run,
305 305 enable => enable_f2,
306 306 burst_enable => burst_f2,
307 307 nb_snapshot_param => nb_snapshot_param_more_one,
308 308 start_snapshot => start_snapshot_f2,
309 309 data_in => data_f2_in,
310 310 data_in_valid => data_f2_in_valid,
311 311 data_out => data_f2_out,
312 312 data_out_valid => data_f2_out_valid);
313 313
314 314 lpp_waveform_burst_f3 : lpp_waveform_burst
315 315 GENERIC MAP (
316 316 data_size => data_size)
317 317 PORT MAP (
318 318 clk => clk,
319 319 rstn => rstn,
320 320 run => run,
321 321 enable => enable_f3,
322 322 data_in => data_f3_in,
323 323 data_in_valid => data_f3_in_valid,
324 324 data_out => data_f3_out,
325 325 data_out_valid => data_f3_out_valid);
326 326
327 327 -----------------------------------------------------------------------------
328 328 -- DEBUG -- SNAPSHOT OUT
329 329 --debug_f0_data_valid <= data_f0_out_valid;
330 330 --debug_f0_data <= data_f0_out;
331 331 --debug_f1_data_valid <= data_f1_out_valid;
332 332 --debug_f1_data <= data_f1_out;
333 333 --debug_f2_data_valid <= data_f2_out_valid;
334 334 --debug_f2_data <= data_f2_out;
335 335 --debug_f3_data_valid <= data_f3_out_valid;
336 336 --debug_f3_data <= data_f3_out;
337 337 -----------------------------------------------------------------------------
338 338
339 339 PROCESS (clk, rstn)
340 340 BEGIN -- PROCESS
341 341 IF rstn = '0' THEN -- asynchronous reset (active low)
342 342 time_reg1 <= (OTHERS => '0');
343 343 time_reg2 <= (OTHERS => '0');
344 344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
345 345 time_reg1 <= fine_time & coarse_time;
346 346 time_reg2 <= time_reg1;
347 347 END IF;
348 348 END PROCESS;
349 349
350 350 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
351 351 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
352 352 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
353 353 PORT MAP (
354 354 HCLK => clk,
355 355 HRESETn => rstn,
356 356 run => run,
357 357 valid_in => valid_in(I),
358 358 ack_in => valid_ack(I),
359 359 time_in => time_reg2, -- Todo
360 360 valid_out => valid_out(I),
361 361 time_out => time_out(I), -- Todo
362 362 error => status_new_err(I));
363 363 END GENERATE all_input_valid;
364 364
365 365 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
366 366 data_out(0, I) <= data_f0_out(I);
367 367 data_out(1, I) <= data_f1_out(I);
368 368 data_out(2, I) <= data_f2_out(I);
369 369 data_out(3, I) <= data_f3_out(I);
370 370 END GENERATE all_bit_of_data_out;
371 371
372 372 -----------------------------------------------------------------------------
373 373 -- TODO : debug
374 374 -----------------------------------------------------------------------------
375 375 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
376 376 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
377 377 time_out_2(J, I) <= time_out(J)(I);
378 378 END GENERATE all_sample_of_time_out;
379 379 END GENERATE all_bit_of_time_out;
380 380
381 381 -- DEBUG --
382 382 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
383 383 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
384 384 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
385 385 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
386 386
387 387 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
388 388 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
389 389 -- time_out_2(J, I) <= time_out_debug(J)(I);
390 390 -- END GENERATE all_sample_of_time_out;
391 391 --END GENERATE all_bit_of_time_out;
392 392 -- DEBUG --
393 393
394 394 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
395 395 GENERIC MAP (tech => tech,
396 396 nb_data_by_buffer_size => nb_data_by_buffer_size)
397 397 PORT MAP (
398 398 clk => clk,
399 399 rstn => rstn,
400 400 run => run,
401 401 nb_data_by_buffer => nb_data_by_buffer,
402 402 data_in_valid => valid_out,
403 403 data_in_ack => valid_ack,
404 404 data_in => data_out,
405 405 time_in => time_out_2,
406 406
407 407 data_out => wdata,
408 408 data_out_wen => data_wen,
409 409 full_almost => full_almost,
410 410 full => full);
411 411
412 412 -----------------------------------------------------------------------------
413 413 -- DEBUG -- SNAPSHOT IN
414 414 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
415 415 --debug_f0_data_fifo_in <= wdata;
416 416 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
417 417 --debug_f1_data_fifo_in <= wdata;
418 418 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
419 419 --debug_f2_data_fifo_in <= wdata;
420 420 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
421 421 --debug_f3_data_fifo_in <= wdata;s
422 422 -----------------------------------------------------------------------------
423 423
424 424 lpp_waveform_fifo_1 : lpp_waveform_fifo
425 425 GENERIC MAP (tech => tech)
426 426 PORT MAP (
427 427 clk => clk,
428 428 rstn => rstn,
429 429 run => run,
430 430
431 431 empty => s_empty,
432 432 empty_almost => s_empty_almost,
433 433 data_ren => s_data_ren,
434 434 rdata => s_rdata,
435 435
436 436
437 437 full_almost => full_almost,
438 438 full => full,
439 439 data_wen => data_wen,
440 440 wdata => wdata);
441 441
442 442 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
443 443 GENERIC MAP (tech => tech)
444 444 PORT MAP (
445 445 clk => clk,
446 446 rstn => rstn,
447 447 run => run,
448 448 o_empty_almost => empty_almost,
449 449 o_empty => empty,
450 450
451 451 o_data_ren => data_ren,
452 452 o_rdata_0 => data_f0_data_out,
453 453 o_rdata_1 => data_f1_data_out,
454 454 o_rdata_2 => data_f2_data_out,
455 455 o_rdata_3 => data_f3_data_out,
456 456
457 457 i_empty_almost => s_empty_almost,
458 458 i_empty => s_empty,
459 459 i_data_ren => s_data_ren,
460 460 i_rdata => s_rdata);
461 461
462 462
463 463 --data_f0_data_out <= rdata;
464 464 --data_f1_data_out <= rdata;
465 465 --data_f2_data_out <= rdata;
466 466 --data_f3_data_out <= rdata;
467 467
468 468 data_ren <= data_f3_data_out_ren &
469 469 data_f2_data_out_ren &
470 470 data_f1_data_out_ren &
471 471 data_f0_data_out_ren;
472 472
473 473 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
474 474 GENERIC MAP (
475 475 nb_data_by_buffer_size => nb_word_by_buffer_size)
476 476 PORT MAP (
477 477 clk => clk,
478 478 rstn => rstn,
479 479 run => run,
480 480
481 481 -------------------------------------------------------------------------
482 482 -- CONFIG
483 483 -------------------------------------------------------------------------
484 484 nb_data_by_buffer => nb_word_by_buffer,
485 485
486 486 addr_data_f0 => addr_data_f0,
487 487 addr_data_f1 => addr_data_f1,
488 488 addr_data_f2 => addr_data_f2,
489 489 addr_data_f3 => addr_data_f3,
490 490 -------------------------------------------------------------------------
491 491 -- CTRL
492 492 -------------------------------------------------------------------------
493 493 -- IN
494 494 empty => empty,
495 495 empty_almost => empty_almost,
496 496 data_ren => data_ren,
497 497
498 498 -------------------------------------------------------------------------
499 499 -- STATUS
500 500 -------------------------------------------------------------------------
501 501 status_full => status_full_s,
502 502 status_full_ack => status_full_ack,
503 503 status_full_err => status_full_err,
504 504
505 505 -------------------------------------------------------------------------
506 506 -- ADDR DATA OUT
507 507 -------------------------------------------------------------------------
508 508 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
509 509 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
510 510 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
511 511 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
512 512
513 513 data_f0_data_out_valid => data_f0_data_out_valid,
514 514 data_f1_data_out_valid => data_f1_data_out_valid,
515 515 data_f2_data_out_valid => data_f2_data_out_valid,
516 516 data_f3_data_out_valid => data_f3_data_out_valid,
517 517
518 518 data_f0_addr_out => data_f0_addr_out,
519 519 data_f1_addr_out => data_f1_addr_out,
520 520 data_f2_addr_out => data_f2_addr_out,
521 521 data_f3_addr_out => data_f3_addr_out
522 522 );
523 523 status_full <= status_full_s;
524 524
525 END beh; No newline at end of file
525 END beh;
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