diff --git a/designs/LFR_simu/run_tb_waveform.do b/designs/LFR_simu/run_tb_waveform.do --- a/designs/LFR_simu/run_tb_waveform.do +++ b/designs/LFR_simu/run_tb_waveform.do @@ -18,6 +18,6 @@ vsim work.testbench log -r * -do tb_waveform.do +do wave_waveform_longsim.do -run -all +run 500 ms diff --git a/designs/LFR_simu/tb_waveform.vhd b/designs/LFR_simu/tb_waveform.vhd --- a/designs/LFR_simu/tb_waveform.vhd +++ b/designs/LFR_simu/tb_waveform.vhd @@ -187,6 +187,48 @@ ARCHITECTURE behav OF testbench IS ----------------------------------------------------------------------------- SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; SIGNAL state_read_buffer_on_going : STD_LOGIC; + CONSTANT hindex : INTEGER := 1; + SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); + + SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + ----------------------------------------------------------------------------- + + SIGNAL current_data : INTEGER; + SIGNAL LIMIT_DATA : INTEGER := 194; + + SIGNAL read_buffer_temp : STD_LOGIC; + SIGNAL read_buffer_temp_2 : STD_LOGIC; + BEGIN @@ -392,7 +434,7 @@ BEGIN APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000060");--"00000001" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040"); @@ -414,16 +456,14 @@ BEGIN WAIT UNTIL clk25MHz = '1'; - read_buffer <= '0'; while_loop: WHILE run_test_waveform_picker = '1' LOOP WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1'; APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status); + IF status(2 DOWNTO 0) = "111" THEN APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000"); - read_buffer <= '1'; END IF; - WAIT UNTIL clk25MHz = '1'; - read_buffer <= '0'; + WAIT UNTIL clk25MHz = '1'; END LOOP while_loop; @@ -447,49 +487,104 @@ BEGIN --REPORT "*** END simulation ***" SEVERITY failure; + WAIT; END PROCESS WaveGen_Proc; ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - -- IRQ - ----------------------------------------------------------------------------- + read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0'; PROCESS (clk25MHz, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - state_read_buffer_on_going <= '0'; - ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + read_buffer <= '0'; + read_buffer_temp_2 <= '0'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + read_buffer_temp_2 <= read_buffer_temp; + read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- IRQ + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + state_read_buffer_on_going <= '0'; + current_data <= 0; + time_mem_f0 <= (OTHERS => '0'); + time_mem_f1 <= (OTHERS => '0'); + time_mem_f2 <= (OTHERS => '0'); + time_mem_f3 <= (OTHERS => '0'); + data_mem_f0 <= (OTHERS => '0'); + data_mem_f1 <= (OTHERS => '0'); + data_mem_f2 <= (OTHERS => '0'); + data_mem_f3 <= (OTHERS => '0'); + + while_loop2: WHILE run_test_waveform_picker = '1' LOOP + WAIT UNTIL clk25MHz = '1'; IF read_buffer = '1' THEN state_read_buffer_on_going <= '1'; - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000", time_mem_f0(31 DOWNTO 0)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000", time_mem_f1(31 DOWNTO 0)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000", time_mem_f2(31 DOWNTO 0)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000", time_mem_f3(31 DOWNTO 0)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000004", time_mem_f0(63 DOWNTO 32)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020004", time_mem_f1(63 DOWNTO 32)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040004", time_mem_f2(63 DOWNTO 32)); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060004", time_mem_f3(63 DOWNTO 32)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32)); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32)); current_data <= 8; ELSE IF state_read_buffer_on_going = '1' THEN -- READ ALL DATA in memory - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000" + current_data, data_mem_f0); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000" + current_data, data_mem_f1); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000" + current_data, data_mem_f2); - AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000" + current_data, data_mem_f3); - IF current_data < LIMIT_DATA THEN - - current_data <= current_data + 4; - ELSE + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + data_0_f0 <= data_mem_f0(15 DOWNTO 0); + data_1_f0 <= data_mem_f0(31 DOWNTO 16); + data_0_f1 <= data_mem_f1(15 DOWNTO 0); + data_1_f1 <= data_mem_f1(31 DOWNTO 16); + data_0_f2 <= data_mem_f2(15 DOWNTO 0); + data_1_f2 <= data_mem_f2(31 DOWNTO 16); + current_data <= current_data + 4; + + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + data_2_f0 <= data_mem_f0(15 DOWNTO 0); + data_3_f0 <= data_mem_f0(31 DOWNTO 16); + data_2_f1 <= data_mem_f1(15 DOWNTO 0); + data_3_f1 <= data_mem_f1(31 DOWNTO 16); + data_2_f2 <= data_mem_f2(15 DOWNTO 0); + data_3_f2 <= data_mem_f2(31 DOWNTO 16); + current_data <= current_data + 4; + + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + data_4_f0 <= data_mem_f0(15 DOWNTO 0); + data_5_f0 <= data_mem_f0(31 DOWNTO 16); + data_4_f1 <= data_mem_f1(15 DOWNTO 0); + data_5_f1 <= data_mem_f1(31 DOWNTO 16); + data_4_f2 <= data_mem_f2(15 DOWNTO 0); + data_5_f2 <= data_mem_f2(31 DOWNTO 16); + current_data <= current_data + 4; + + IF current_data > LIMIT_DATA THEN state_read_buffer_on_going <= '0'; + time_mem_f0 <= (OTHERS => '0'); + time_mem_f1 <= (OTHERS => '0'); + time_mem_f2 <= (OTHERS => '0'); + time_mem_f3 <= (OTHERS => '0'); + data_mem_f0 <= (OTHERS => '0'); + data_mem_f1 <= (OTHERS => '0'); + data_mem_f2 <= (OTHERS => '0'); + data_mem_f3 <= (OTHERS => '0'); END IF; END IF; END IF; - END IF; + END LOOP while_loop2; END PROCESS; ----------------------------------------------------------------------------- diff --git a/designs/LFR_simu/testbench_package.vhd b/designs/LFR_simu/testbench_package.vhd --- a/designs/LFR_simu/testbench_package.vhd +++ b/designs/LFR_simu/testbench_package.vhd @@ -1,105 +1,120 @@ - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; ---LIBRARY gaisler; ---USE gaisler.libdcom.ALL; ---USE gaisler.sim.ALL; ---USE gaisler.jtagtst.ALL; ---LIBRARY techmap; ---USE techmap.gencomp.ALL; - - -PACKAGE testbench_package IS - - PROCEDURE APB_WRITE ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - - PROCEDURE APB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - SIGNAL apbo : IN apb_slv_out_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - - PROCEDURE AHB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT hindex : IN INTEGER - SIGNAL ahbmi : OUT ahb_slv_in_type; - SIGNAL ahbmo : IN ahb_slv_out_type; - CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END testbench_package; - -PACKAGE BODY testbench_package IS - - PROCEDURE APB_WRITE ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - apbi.psel(pindex) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= paddr; - apbi.pwdata <= pwdata; - WAIT UNTIL clk = '1'; - apbi.psel(pindex) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - - END APB_WRITE; - - PROCEDURE APB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - SIGNAL apbo : IN apb_slv_out_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - apbi.psel(pindex) <= '1'; - apbi.pwrite <= '0'; - apbi.penable <= '1'; - apbi.paddr <= paddr; - WAIT UNTIL clk = '1'; - apbi.psel(pindex) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - WAIT UNTIL clk = '1'; - prdata <= apbo.prdata; - END APB_READ; - - PROCEDURE AHB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT hindex : IN INTEGER - SIGNAL ahbmi : OUT ahb_slv_in_type; - SIGNAL ahbmo : IN ahb_slv_out_type; - CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - - END AHB_READ; - - - -END testbench_package; + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + hrdata <= ahbmi.HRDATA; + WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HTRANS <= HTRANS_IDLE; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + END AHB_READ; + +END testbench_package; diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00000E") -- aa.bb.cc version + top_lfr_version => X"00000F") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, @@ -446,7 +446,7 @@ BEGIN -- beh ChannelCount => 8, SampleNbBits => 14, ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 250) -- 49 152 000 / 98304 /2 + ncycle_cnv => 249) -- 49 152 000 / 98304 /2 PORT MAP ( -- CONV cnv_clk => clk_24, diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -1,525 +1,525 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY lpp; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_waveform IS - - GENERIC ( - tech : INTEGER := inferred; - data_size : INTEGER := 96; --16*6 - nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3); - - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - ---- AMBA AHB Master Interface - --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO - --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO - - --config - reg_run : IN STD_LOGIC; - reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - --------------------------------------------------------------------------- - -- INPUT - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - - --f0 - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_in_valid : IN STD_LOGIC; - data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --f1 - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_in_valid : IN STD_LOGIC; - data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --f2 - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_in_valid : IN STD_LOGIC; - data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --f3 - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_in_valid : IN STD_LOGIC; - data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - - --------------------------------------------------------------------------- - -- OUTPUT - --f0 - data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out_valid : OUT STD_LOGIC; - data_f0_data_out_valid_burst : OUT STD_LOGIC; - data_f0_data_out_ren : IN STD_LOGIC; - --f1 - data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out_valid : OUT STD_LOGIC; - data_f1_data_out_valid_burst : OUT STD_LOGIC; - data_f1_data_out_ren : IN STD_LOGIC; - --f2 - data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out_valid : OUT STD_LOGIC; - data_f2_data_out_valid_burst : OUT STD_LOGIC; - data_f2_data_out_ren : IN STD_LOGIC; - --f3 - data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out_valid : OUT STD_LOGIC; - data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - - - ----debug SNAPSHOT OUT - --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f0_data_valid : OUT STD_LOGIC; - --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f1_data_valid : OUT STD_LOGIC; - --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f2_data_valid : OUT STD_LOGIC; - --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f3_data_valid : OUT STD_LOGIC; - - ----debug FIFO IN - --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_fifo_in_valid : OUT STD_LOGIC - - ); - -END lpp_waveform; - -ARCHITECTURE beh OF lpp_waveform IS - SIGNAL start_snapshot_f0 : STD_LOGIC; - SIGNAL start_snapshot_f1 : STD_LOGIC; - SIGNAL start_snapshot_f2 : STD_LOGIC; - - SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - - SIGNAL data_f0_out_valid : STD_LOGIC; - SIGNAL data_f1_out_valid : STD_LOGIC; - SIGNAL data_f2_out_valid : STD_LOGIC; - SIGNAL data_f3_out_valid : STD_LOGIC; - SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); - -- - SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - -- - SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); - -- - SIGNAL run : STD_LOGIC; - -- - TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); - SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); - SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); - SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug - SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - -- - - SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b - SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- - - SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- DEBUG - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - observation_reg <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - observation_reg <= observation_reg_s; - END IF; - END PROCESS; - observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; - observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; - observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; - observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); - observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); - observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); - ----------------------------------------------------------------------------- - - lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler - GENERIC MAP ( - delta_vector_size => delta_vector_size, - delta_vector_size_f0_2 => delta_vector_size_f0_2 - ) - PORT MAP ( - clk => clk, - rstn => rstn, - reg_run => reg_run, - reg_start_date => reg_start_date, - reg_delta_snapshot => reg_delta_snapshot, - reg_delta_f0 => reg_delta_f0, - reg_delta_f0_2 => reg_delta_f0_2, - reg_delta_f1 => reg_delta_f1, - reg_delta_f2 => reg_delta_f2, - coarse_time => coarse_time(30 DOWNTO 0), - data_f0_valid => data_f0_in_valid, - data_f2_valid => data_f2_in_valid, - start_snapshot_f0 => start_snapshot_f0, - start_snapshot_f1 => start_snapshot_f1, - start_snapshot_f2 => start_snapshot_f2, - wfp_on => run); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f0, - burst_enable => burst_f0, - nb_snapshot_param => nb_snapshot_param, - start_snapshot => start_snapshot_f0, - data_in => data_f0_in, - data_in_valid => data_f0_in_valid, - data_out => data_f0_out, - data_out_valid => data_f0_out_valid); - - nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; - - lpp_waveform_snapshot_f1 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size+1) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f1, - burst_enable => burst_f1, - nb_snapshot_param => nb_snapshot_param_more_one, - start_snapshot => start_snapshot_f1, - data_in => data_f1_in, - data_in_valid => data_f1_in_valid, - data_out => data_f1_out, - data_out_valid => data_f1_out_valid); - - lpp_waveform_snapshot_f2 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size+1) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f2, - burst_enable => burst_f2, - nb_snapshot_param => nb_snapshot_param_more_one, - start_snapshot => start_snapshot_f2, - data_in => data_f2_in, - data_in_valid => data_f2_in_valid, - data_out => data_f2_out, - data_out_valid => data_f2_out_valid); - - lpp_waveform_burst_f3 : lpp_waveform_burst - GENERIC MAP ( - data_size => data_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f3, - data_in => data_f3_in, - data_in_valid => data_f3_in_valid, - data_out => data_f3_out, - data_out_valid => data_f3_out_valid); - - ----------------------------------------------------------------------------- - -- DEBUG -- SNAPSHOT OUT - --debug_f0_data_valid <= data_f0_out_valid; - --debug_f0_data <= data_f0_out; - --debug_f1_data_valid <= data_f1_out_valid; - --debug_f1_data <= data_f1_out; - --debug_f2_data_valid <= data_f2_out_valid; - --debug_f2_data <= data_f2_out; - --debug_f3_data_valid <= data_f3_out_valid; - --debug_f3_data <= data_f3_out; - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - time_reg1 <= (OTHERS => '0'); - time_reg2 <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - time_reg1 <= fine_time & coarse_time; - time_reg2 <= time_reg1; - END IF; - END PROCESS; - - valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; - all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE - lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - run => run, - valid_in => valid_in(I), - ack_in => valid_ack(I), - time_in => time_reg2, -- Todo - valid_out => valid_out(I), - time_out => time_out(I), -- Todo - error => status_new_err(I)); - END GENERATE all_input_valid; - - all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE - data_out(0, I) <= data_f0_out(I); - data_out(1, I) <= data_f1_out(I); - data_out(2, I) <= data_f2_out(I); - data_out(3, I) <= data_f3_out(I); - END GENERATE all_bit_of_data_out; - - ----------------------------------------------------------------------------- - -- TODO : debug - ----------------------------------------------------------------------------- - all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE - all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE - time_out_2(J, I) <= time_out(J)(I); - END GENERATE all_sample_of_time_out; - END GENERATE all_bit_of_time_out; - - -- DEBUG -- - --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; - --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; - --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; - --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; - - --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE - -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE - -- time_out_2(J, I) <= time_out_debug(J)(I); - -- END GENERATE all_sample_of_time_out; - --END GENERATE all_bit_of_time_out; - -- DEBUG -- - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - GENERIC MAP (tech => tech, - nb_data_by_buffer_size => nb_data_by_buffer_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - nb_data_by_buffer => nb_data_by_buffer, - data_in_valid => valid_out, - data_in_ack => valid_ack, - data_in => data_out, - time_in => time_out_2, - - data_out => wdata, - data_out_wen => data_wen, - full_almost => full_almost, - full => full); - - ----------------------------------------------------------------------------- - -- DEBUG -- SNAPSHOT IN - --debug_f0_data_fifo_in_valid <= NOT data_wen(0); - --debug_f0_data_fifo_in <= wdata; - --debug_f1_data_fifo_in_valid <= NOT data_wen(1); - --debug_f1_data_fifo_in <= wdata; - --debug_f2_data_fifo_in_valid <= NOT data_wen(2); - --debug_f2_data_fifo_in <= wdata; - --debug_f3_data_fifo_in_valid <= NOT data_wen(3); - --debug_f3_data_fifo_in <= wdata;s - ----------------------------------------------------------------------------- - - lpp_waveform_fifo_1 : lpp_waveform_fifo - GENERIC MAP (tech => tech) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - - empty => s_empty, - empty_almost => s_empty_almost, - data_ren => s_data_ren, - rdata => s_rdata, - - - full_almost => full_almost, - full => full, - data_wen => data_wen, - wdata => wdata); - - lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg - GENERIC MAP (tech => tech) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - o_empty_almost => empty_almost, - o_empty => empty, - - o_data_ren => data_ren, - o_rdata_0 => data_f0_data_out, - o_rdata_1 => data_f1_data_out, - o_rdata_2 => data_f2_data_out, - o_rdata_3 => data_f3_data_out, - - i_empty_almost => s_empty_almost, - i_empty => s_empty, - i_data_ren => s_data_ren, - i_rdata => s_rdata); - - - --data_f0_data_out <= rdata; - --data_f1_data_out <= rdata; - --data_f2_data_out <= rdata; - --data_f3_data_out <= rdata; - - data_ren <= data_f3_data_out_ren & - data_f2_data_out_ren & - data_f1_data_out_ren & - data_f0_data_out_ren; - - lpp_waveform_gen_address_1 : lpp_waveform_genaddress - GENERIC MAP ( - nb_data_by_buffer_size => nb_word_by_buffer_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - - ------------------------------------------------------------------------- - -- CONFIG - ------------------------------------------------------------------------- - nb_data_by_buffer => nb_word_by_buffer, - - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3, - ------------------------------------------------------------------------- - -- CTRL - ------------------------------------------------------------------------- - -- IN - empty => empty, - empty_almost => empty_almost, - data_ren => data_ren, - - ------------------------------------------------------------------------- - -- STATUS - ------------------------------------------------------------------------- - status_full => status_full_s, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - - ------------------------------------------------------------------------- - -- ADDR DATA OUT - ------------------------------------------------------------------------- - data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, - data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, - data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, - data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, - - data_f0_data_out_valid => data_f0_data_out_valid, - data_f1_data_out_valid => data_f1_data_out_valid, - data_f2_data_out_valid => data_f2_data_out_valid, - data_f3_data_out_valid => data_f3_data_out_valid, - - data_f0_addr_out => data_f0_addr_out, - data_f1_addr_out => data_f1_addr_out, - data_f2_addr_out => data_f2_addr_out, - data_f3_addr_out => data_f3_addr_out - ); - status_full <= status_full_s; - -END beh; \ No newline at end of file +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform IS + + GENERIC ( + tech : INTEGER := inferred; + data_size : INTEGER := 96; --16*6 + nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ---- AMBA AHB Master Interface + --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO + --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO + + --config + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + --------------------------------------------------------------------------- + -- INPUT + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + --f0 + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f1 + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_in_valid : IN STD_LOGIC; + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f2 + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_in_valid : IN STD_LOGIC; + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f3 + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_in_valid : IN STD_LOGIC; + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- OUTPUT + --f0 + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out_valid : OUT STD_LOGIC; + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f0_data_out_ren : IN STD_LOGIC; + --f1 + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_ren : IN STD_LOGIC; + --f2 + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_ren : IN STD_LOGIC; + --f3 + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_ren : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- + observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + + ----debug SNAPSHOT OUT + --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --debug_f0_data_valid : OUT STD_LOGIC; + --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --debug_f1_data_valid : OUT STD_LOGIC; + --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --debug_f2_data_valid : OUT STD_LOGIC; + --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --debug_f3_data_valid : OUT STD_LOGIC; + + ----debug FIFO IN + --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f3_data_fifo_in_valid : OUT STD_LOGIC + + ); + +END lpp_waveform; + +ARCHITECTURE beh OF lpp_waveform IS + SIGNAL start_snapshot_f0 : STD_LOGIC; + SIGNAL start_snapshot_f1 : STD_LOGIC; + SIGNAL start_snapshot_f2 : STD_LOGIC; + + SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_valid : STD_LOGIC; + SIGNAL data_f1_out_valid : STD_LOGIC; + SIGNAL data_f2_out_valid : STD_LOGIC; + SIGNAL data_f3_out_valid : STD_LOGIC; + SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); + -- + SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL run : STD_LOGIC; + -- + TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); + SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug + SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + -- + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- + + SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- DEBUG + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + observation_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + observation_reg <= observation_reg_s; + END IF; + END PROCESS; + observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; + observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; + observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); + observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); + observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); + ----------------------------------------------------------------------------- + + lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler + GENERIC MAP ( + delta_vector_size => delta_vector_size, + delta_vector_size_f0_2 => delta_vector_size_f0_2 + ) + PORT MAP ( + clk => clk, + rstn => rstn, + reg_run => reg_run, + reg_start_date => reg_start_date, + reg_delta_snapshot => reg_delta_snapshot, + reg_delta_f0 => reg_delta_f0, + reg_delta_f0_2 => reg_delta_f0_2, + reg_delta_f1 => reg_delta_f1, + reg_delta_f2 => reg_delta_f2, + coarse_time => coarse_time(30 DOWNTO 0), + data_f0_valid => data_f0_in_valid, + data_f2_valid => data_f2_in_valid, + start_snapshot_f0 => start_snapshot_f0, + start_snapshot_f1 => start_snapshot_f1, + start_snapshot_f2 => start_snapshot_f2, + wfp_on => run); + + lpp_waveform_snapshot_f0 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f0, + burst_enable => burst_f0, + nb_snapshot_param => nb_snapshot_param, + start_snapshot => start_snapshot_f0, + data_in => data_f0_in, + data_in_valid => data_f0_in_valid, + data_out => data_f0_out, + data_out_valid => data_f0_out_valid); + + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; + + lpp_waveform_snapshot_f1 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f1, + burst_enable => burst_f1, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f1, + data_in => data_f1_in, + data_in_valid => data_f1_in_valid, + data_out => data_f1_out, + data_out_valid => data_f1_out_valid); + + lpp_waveform_snapshot_f2 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f2, + burst_enable => burst_f2, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f2, + data_in => data_f2_in, + data_in_valid => data_f2_in_valid, + data_out => data_f2_out, + data_out_valid => data_f2_out_valid); + + lpp_waveform_burst_f3 : lpp_waveform_burst + GENERIC MAP ( + data_size => data_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f3, + data_in => data_f3_in, + data_in_valid => data_f3_in_valid, + data_out => data_f3_out, + data_out_valid => data_f3_out_valid); + + ----------------------------------------------------------------------------- + -- DEBUG -- SNAPSHOT OUT + --debug_f0_data_valid <= data_f0_out_valid; + --debug_f0_data <= data_f0_out; + --debug_f1_data_valid <= data_f1_out_valid; + --debug_f1_data <= data_f1_out; + --debug_f2_data_valid <= data_f2_out_valid; + --debug_f2_data <= data_f2_out; + --debug_f3_data_valid <= data_f3_out_valid; + --debug_f3_data <= data_f3_out; + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + time_reg1 <= (OTHERS => '0'); + time_reg2 <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + time_reg1 <= fine_time & coarse_time; + time_reg2 <= time_reg1; + END IF; + END PROCESS; + + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE + lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + valid_in => valid_in(I), + ack_in => valid_ack(I), + time_in => time_reg2, -- Todo + valid_out => valid_out(I), + time_out => time_out(I), -- Todo + error => status_new_err(I)); + END GENERATE all_input_valid; + + all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE + data_out(0, I) <= data_f0_out(I); + data_out(1, I) <= data_f1_out(I); + data_out(2, I) <= data_f2_out(I); + data_out(3, I) <= data_f3_out(I); + END GENERATE all_bit_of_data_out; + + ----------------------------------------------------------------------------- + -- TODO : debug + ----------------------------------------------------------------------------- + all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + time_out_2(J, I) <= time_out(J)(I); + END GENERATE all_sample_of_time_out; + END GENERATE all_bit_of_time_out; + + -- DEBUG -- + --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; + --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; + --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; + --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; + + --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + -- time_out_2(J, I) <= time_out_debug(J)(I); + -- END GENERATE all_sample_of_time_out; + --END GENERATE all_bit_of_time_out; + -- DEBUG -- + + lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter + GENERIC MAP (tech => tech, + nb_data_by_buffer_size => nb_data_by_buffer_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + nb_data_by_buffer => nb_data_by_buffer, + data_in_valid => valid_out, + data_in_ack => valid_ack, + data_in => data_out, + time_in => time_out_2, + + data_out => wdata, + data_out_wen => data_wen, + full_almost => full_almost, + full => full); + + ----------------------------------------------------------------------------- + -- DEBUG -- SNAPSHOT IN + --debug_f0_data_fifo_in_valid <= NOT data_wen(0); + --debug_f0_data_fifo_in <= wdata; + --debug_f1_data_fifo_in_valid <= NOT data_wen(1); + --debug_f1_data_fifo_in <= wdata; + --debug_f2_data_fifo_in_valid <= NOT data_wen(2); + --debug_f2_data_fifo_in <= wdata; + --debug_f3_data_fifo_in_valid <= NOT data_wen(3); + --debug_f3_data_fifo_in <= wdata;s + ----------------------------------------------------------------------------- + + lpp_waveform_fifo_1 : lpp_waveform_fifo + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty => s_empty, + empty_almost => s_empty_almost, + data_ren => s_data_ren, + rdata => s_rdata, + + + full_almost => full_almost, + full => full, + data_wen => data_wen, + wdata => wdata); + + lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_f0_data_out, + o_rdata_1 => data_f1_data_out, + o_rdata_2 => data_f2_data_out, + o_rdata_3 => data_f3_data_out, + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + + + --data_f0_data_out <= rdata; + --data_f1_data_out <= rdata; + --data_f2_data_out <= rdata; + --data_f3_data_out <= rdata; + + data_ren <= data_f3_data_out_ren & + data_f2_data_out_ren & + data_f1_data_out_ren & + data_f0_data_out_ren; + + lpp_waveform_gen_address_1 : lpp_waveform_genaddress + GENERIC MAP ( + nb_data_by_buffer_size => nb_word_by_buffer_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + ------------------------------------------------------------------------- + -- CONFIG + ------------------------------------------------------------------------- + nb_data_by_buffer => nb_word_by_buffer, + + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3, + ------------------------------------------------------------------------- + -- CTRL + ------------------------------------------------------------------------- + -- IN + empty => empty, + empty_almost => empty_almost, + data_ren => data_ren, + + ------------------------------------------------------------------------- + -- STATUS + ------------------------------------------------------------------------- + status_full => status_full_s, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + + ------------------------------------------------------------------------- + -- ADDR DATA OUT + ------------------------------------------------------------------------- + data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, + data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, + data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, + data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, + + data_f0_data_out_valid => data_f0_data_out_valid, + data_f1_data_out_valid => data_f1_data_out_valid, + data_f2_data_out_valid => data_f2_data_out_valid, + data_f3_data_out_valid => data_f3_data_out_valid, + + data_f0_addr_out => data_f0_addr_out, + data_f1_addr_out => data_f1_addr_out, + data_f2_addr_out => data_f2_addr_out, + data_f3_addr_out => data_f3_addr_out + ); + status_full <= status_full_s; + +END beh;