@@ -18,6 +18,6 vsim work.testbench | |||||
18 |
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18 | |||
19 | log -r * |
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19 | log -r * | |
20 |
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20 | |||
21 |
do |
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21 | do wave_waveform_longsim.do | |
22 |
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22 | |||
23 | run -all |
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23 | run 500 ms |
@@ -187,6 +187,48 ARCHITECTURE behav OF testbench IS | |||||
187 | ----------------------------------------------------------------------------- |
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187 | ----------------------------------------------------------------------------- | |
188 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; |
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188 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; | |
189 | SIGNAL state_read_buffer_on_going : STD_LOGIC; |
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189 | SIGNAL state_read_buffer_on_going : STD_LOGIC; | |
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190 | CONSTANT hindex : INTEGER := 1; | |||
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191 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
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192 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
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193 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
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194 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
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195 | ||||
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196 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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197 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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198 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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199 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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200 | ||||
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201 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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202 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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203 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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204 | ||||
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205 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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206 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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207 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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208 | ||||
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209 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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210 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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211 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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212 | ||||
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213 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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214 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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215 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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216 | ||||
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217 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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218 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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219 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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220 | ||||
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221 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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222 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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223 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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224 | ----------------------------------------------------------------------------- | |||
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225 | ||||
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226 | SIGNAL current_data : INTEGER; | |||
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227 | SIGNAL LIMIT_DATA : INTEGER := 194; | |||
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228 | ||||
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229 | SIGNAL read_buffer_temp : STD_LOGIC; | |||
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230 | SIGNAL read_buffer_temp_2 : STD_LOGIC; | |||
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231 | ||||
190 |
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232 | ||
191 | BEGIN |
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233 | BEGIN | |
192 |
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234 | |||
@@ -392,7 +434,7 BEGIN | |||||
392 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" |
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434 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" | |
393 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" |
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435 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
394 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" |
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436 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" | |
395 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"000000 |
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437 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
396 |
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438 | |||
397 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010" |
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439 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010" | |
398 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040"); |
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440 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040"); | |
@@ -414,16 +456,14 BEGIN | |||||
414 |
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456 | |||
415 | WAIT UNTIL clk25MHz = '1'; |
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457 | WAIT UNTIL clk25MHz = '1'; | |
416 |
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458 | |||
417 | read_buffer <= '0'; |
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418 |
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459 | while_loop: WHILE run_test_waveform_picker = '1' LOOP | |
419 | WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1'; |
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460 | WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1'; | |
420 | APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status); |
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461 | APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status); | |
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462 | ||||
421 |
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463 | IF status(2 DOWNTO 0) = "111" THEN | |
422 | APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000"); |
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464 | APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000"); | |
423 | read_buffer <= '1'; |
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424 | END IF; |
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465 | END IF; | |
425 |
WAIT UNTIL clk25MHz = '1'; |
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466 | WAIT UNTIL clk25MHz = '1'; | |
426 | read_buffer <= '0'; |
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427 |
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467 | END LOOP while_loop; | |
428 |
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468 | |||
429 |
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469 | |||
@@ -447,49 +487,104 BEGIN | |||||
447 | --REPORT "*** END simulation ***" SEVERITY failure; |
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487 | --REPORT "*** END simulation ***" SEVERITY failure; | |
448 |
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488 | |||
449 |
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489 | |||
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490 | ||||
450 | WAIT; |
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491 | WAIT; | |
451 |
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492 | |||
452 | END PROCESS WaveGen_Proc; |
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493 | END PROCESS WaveGen_Proc; | |
453 | ----------------------------------------------------------------------------- |
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494 | ----------------------------------------------------------------------------- | |
454 |
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495 | |||
455 | ----------------------------------------------------------------------------- |
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496 | read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0'; | |
456 | -- IRQ |
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|||
457 | ----------------------------------------------------------------------------- |
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458 | PROCESS (clk25MHz, rstn) |
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497 | PROCESS (clk25MHz, rstn) | |
459 | BEGIN -- PROCESS |
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498 | BEGIN -- PROCESS | |
460 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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499 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
461 |
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500 | read_buffer <= '0'; | |
462 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
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501 | read_buffer_temp_2 <= '0'; | |
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502 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
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503 | read_buffer_temp_2 <= read_buffer_temp; | |||
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504 | read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2; | |||
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505 | END IF; | |||
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506 | END PROCESS; | |||
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507 | ||||
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508 | ----------------------------------------------------------------------------- | |||
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509 | -- IRQ | |||
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510 | ----------------------------------------------------------------------------- | |||
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511 | PROCESS | |||
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512 | BEGIN -- PROCESS | |||
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513 | state_read_buffer_on_going <= '0'; | |||
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514 | current_data <= 0; | |||
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515 | time_mem_f0 <= (OTHERS => '0'); | |||
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516 | time_mem_f1 <= (OTHERS => '0'); | |||
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517 | time_mem_f2 <= (OTHERS => '0'); | |||
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518 | time_mem_f3 <= (OTHERS => '0'); | |||
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519 | data_mem_f0 <= (OTHERS => '0'); | |||
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520 | data_mem_f1 <= (OTHERS => '0'); | |||
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521 | data_mem_f2 <= (OTHERS => '0'); | |||
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522 | data_mem_f3 <= (OTHERS => '0'); | |||
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523 | ||||
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524 | while_loop2: WHILE run_test_waveform_picker = '1' LOOP | |||
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525 | WAIT UNTIL clk25MHz = '1'; | |||
463 | IF read_buffer = '1' THEN |
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526 | IF read_buffer = '1' THEN | |
464 | state_read_buffer_on_going <= '1'; |
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527 | state_read_buffer_on_going <= '1'; | |
465 |
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528 | |||
466 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000", time_mem_f0(31 DOWNTO 0)); |
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529 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0)); | |
467 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000", time_mem_f1(31 DOWNTO 0)); |
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530 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0)); | |
468 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000", time_mem_f2(31 DOWNTO 0)); |
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531 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0)); | |
469 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000", time_mem_f3(31 DOWNTO 0)); |
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470 |
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532 | |||
471 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000004", time_mem_f0(63 DOWNTO 32)); |
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533 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32)); | |
472 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020004", time_mem_f1(63 DOWNTO 32)); |
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534 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32)); | |
473 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040004", time_mem_f2(63 DOWNTO 32)); |
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535 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32)); | |
474 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060004", time_mem_f3(63 DOWNTO 32)); |
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475 |
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536 | |||
476 | current_data <= 8; |
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537 | current_data <= 8; | |
477 | ELSE |
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538 | ELSE | |
478 | IF state_read_buffer_on_going = '1' THEN |
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539 | IF state_read_buffer_on_going = '1' THEN | |
479 | -- READ ALL DATA in memory |
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540 | -- READ ALL DATA in memory | |
480 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000" + current_data, data_mem_f0); |
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541 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |
481 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000" + current_data, data_mem_f1); |
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542 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |
482 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000" + current_data, data_mem_f2); |
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543 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |
483 | AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000" + current_data, data_mem_f3); |
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544 | data_0_f0 <= data_mem_f0(15 DOWNTO 0); | |
484 | IF current_data < LIMIT_DATA THEN |
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545 | data_1_f0 <= data_mem_f0(31 DOWNTO 16); | |
485 |
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546 | data_0_f1 <= data_mem_f1(15 DOWNTO 0); | ||
486 | current_data <= current_data + 4; |
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547 | data_1_f1 <= data_mem_f1(31 DOWNTO 16); | |
487 | ELSE |
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548 | data_0_f2 <= data_mem_f2(15 DOWNTO 0); | |
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549 | data_1_f2 <= data_mem_f2(31 DOWNTO 16); | |||
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550 | current_data <= current_data + 4; | |||
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551 | ||||
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552 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |||
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553 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |||
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554 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |||
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555 | data_2_f0 <= data_mem_f0(15 DOWNTO 0); | |||
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556 | data_3_f0 <= data_mem_f0(31 DOWNTO 16); | |||
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557 | data_2_f1 <= data_mem_f1(15 DOWNTO 0); | |||
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558 | data_3_f1 <= data_mem_f1(31 DOWNTO 16); | |||
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559 | data_2_f2 <= data_mem_f2(15 DOWNTO 0); | |||
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560 | data_3_f2 <= data_mem_f2(31 DOWNTO 16); | |||
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561 | current_data <= current_data + 4; | |||
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562 | ||||
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563 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |||
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564 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |||
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565 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |||
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566 | data_4_f0 <= data_mem_f0(15 DOWNTO 0); | |||
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567 | data_5_f0 <= data_mem_f0(31 DOWNTO 16); | |||
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568 | data_4_f1 <= data_mem_f1(15 DOWNTO 0); | |||
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569 | data_5_f1 <= data_mem_f1(31 DOWNTO 16); | |||
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570 | data_4_f2 <= data_mem_f2(15 DOWNTO 0); | |||
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571 | data_5_f2 <= data_mem_f2(31 DOWNTO 16); | |||
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572 | current_data <= current_data + 4; | |||
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573 | ||||
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574 | IF current_data > LIMIT_DATA THEN | |||
488 | state_read_buffer_on_going <= '0'; |
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575 | state_read_buffer_on_going <= '0'; | |
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576 | time_mem_f0 <= (OTHERS => '0'); | |||
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577 | time_mem_f1 <= (OTHERS => '0'); | |||
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578 | time_mem_f2 <= (OTHERS => '0'); | |||
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579 | time_mem_f3 <= (OTHERS => '0'); | |||
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580 | data_mem_f0 <= (OTHERS => '0'); | |||
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581 | data_mem_f1 <= (OTHERS => '0'); | |||
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582 | data_mem_f2 <= (OTHERS => '0'); | |||
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583 | data_mem_f3 <= (OTHERS => '0'); | |||
489 | END IF; |
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584 | END IF; | |
490 | END IF; |
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585 | END IF; | |
491 | END IF; |
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586 | END IF; | |
492 | END IF; |
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587 | END LOOP while_loop2; | |
493 | END PROCESS; |
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588 | END PROCESS; | |
494 | ----------------------------------------------------------------------------- |
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589 | ----------------------------------------------------------------------------- | |
495 |
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590 |
@@ -1,105 +1,120 | |||||
1 |
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1 | |||
2 | LIBRARY ieee; |
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2 | LIBRARY ieee; | |
3 | USE ieee.std_logic_1164.ALL; |
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3 | USE ieee.std_logic_1164.ALL; | |
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
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5 | USE grlib.amba.ALL; | |
6 | USE grlib.stdlib.ALL; |
|
6 | USE grlib.stdlib.ALL; | |
7 | --LIBRARY gaisler; |
|
7 | --LIBRARY gaisler; | |
8 | --USE gaisler.libdcom.ALL; |
|
8 | --USE gaisler.libdcom.ALL; | |
9 | --USE gaisler.sim.ALL; |
|
9 | --USE gaisler.sim.ALL; | |
10 | --USE gaisler.jtagtst.ALL; |
|
10 | --USE gaisler.jtagtst.ALL; | |
11 | --LIBRARY techmap; |
|
11 | --LIBRARY techmap; | |
12 | --USE techmap.gencomp.ALL; |
|
12 | --USE techmap.gencomp.ALL; | |
13 |
|
13 | |||
14 |
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14 | |||
15 | PACKAGE testbench_package IS |
|
15 | PACKAGE testbench_package IS | |
16 |
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16 | |||
17 | PROCEDURE APB_WRITE ( |
|
17 | PROCEDURE APB_WRITE ( | |
18 | SIGNAL clk : IN STD_LOGIC; |
|
18 | SIGNAL clk : IN STD_LOGIC; | |
19 | CONSTANT pindex : IN INTEGER; |
|
19 | CONSTANT pindex : IN INTEGER; | |
20 | SIGNAL apbi : OUT apb_slv_in_type; |
|
20 | SIGNAL apbi : OUT apb_slv_in_type; | |
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
23 | ); |
|
23 | ); | |
24 |
|
24 | |||
25 | PROCEDURE APB_READ ( |
|
25 | PROCEDURE APB_READ ( | |
26 | SIGNAL clk : IN STD_LOGIC; |
|
26 | SIGNAL clk : IN STD_LOGIC; | |
27 | CONSTANT pindex : IN INTEGER; |
|
27 | CONSTANT pindex : IN INTEGER; | |
28 | SIGNAL apbi : OUT apb_slv_in_type; |
|
28 | SIGNAL apbi : OUT apb_slv_in_type; | |
29 | SIGNAL apbo : IN apb_slv_out_type; |
|
29 | SIGNAL apbo : IN apb_slv_out_type; | |
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
32 | ); |
|
32 | ); | |
33 |
|
33 | |||
34 | PROCEDURE AHB_READ ( |
|
34 | PROCEDURE AHB_READ ( | |
35 | SIGNAL clk : IN STD_LOGIC; |
|
35 | SIGNAL clk : IN STD_LOGIC; | |
36 | CONSTANT hindex : IN INTEGER |
|
36 | CONSTANT hindex : IN INTEGER; | |
37 |
SIGNAL ahbmi : |
|
37 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
38 |
SIGNAL ahbmo : |
|
38 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
41 | ); |
|
41 | ); | |
42 |
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42 | |||
43 | END testbench_package; |
|
43 | END testbench_package; | |
44 |
|
44 | |||
45 | PACKAGE BODY testbench_package IS |
|
45 | PACKAGE BODY testbench_package IS | |
46 |
|
46 | |||
47 | PROCEDURE APB_WRITE ( |
|
47 | PROCEDURE APB_WRITE ( | |
48 | SIGNAL clk : IN STD_LOGIC; |
|
48 | SIGNAL clk : IN STD_LOGIC; | |
49 | CONSTANT pindex : IN INTEGER; |
|
49 | CONSTANT pindex : IN INTEGER; | |
50 | SIGNAL apbi : OUT apb_slv_in_type; |
|
50 | SIGNAL apbi : OUT apb_slv_in_type; | |
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
53 | ) IS |
|
53 | ) IS | |
54 | BEGIN |
|
54 | BEGIN | |
55 | apbi.psel(pindex) <= '1'; |
|
55 | apbi.psel(pindex) <= '1'; | |
56 | apbi.pwrite <= '1'; |
|
56 | apbi.pwrite <= '1'; | |
57 | apbi.penable <= '1'; |
|
57 | apbi.penable <= '1'; | |
58 | apbi.paddr <= paddr; |
|
58 | apbi.paddr <= paddr; | |
59 | apbi.pwdata <= pwdata; |
|
59 | apbi.pwdata <= pwdata; | |
60 | WAIT UNTIL clk = '1'; |
|
60 | WAIT UNTIL clk = '1'; | |
61 | apbi.psel(pindex) <= '0'; |
|
61 | apbi.psel(pindex) <= '0'; | |
62 | apbi.pwrite <= '0'; |
|
62 | apbi.pwrite <= '0'; | |
63 | apbi.penable <= '0'; |
|
63 | apbi.penable <= '0'; | |
64 | apbi.paddr <= (OTHERS => '0'); |
|
64 | apbi.paddr <= (OTHERS => '0'); | |
65 | apbi.pwdata <= (OTHERS => '0'); |
|
65 | apbi.pwdata <= (OTHERS => '0'); | |
66 |
|
66 | WAIT UNTIL clk = '1'; | ||
67 | END APB_WRITE; |
|
67 | ||
68 |
|
68 | END APB_WRITE; | ||
69 | PROCEDURE APB_READ ( |
|
69 | ||
70 | SIGNAL clk : IN STD_LOGIC; |
|
70 | PROCEDURE APB_READ ( | |
71 | CONSTANT pindex : IN INTEGER; |
|
71 | SIGNAL clk : IN STD_LOGIC; | |
72 | SIGNAL apbi : OUT apb_slv_in_type; |
|
72 | CONSTANT pindex : IN INTEGER; | |
73 |
SIGNAL apb |
|
73 | SIGNAL apbi : OUT apb_slv_in_type; | |
74 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | SIGNAL apbo : IN apb_slv_out_type; | |
75 |
|
|
75 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | ) IS |
|
76 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
77 | BEGIN |
|
77 | ) IS | |
78 | apbi.psel(pindex) <= '1'; |
|
78 | BEGIN | |
79 |
apbi.p |
|
79 | apbi.psel(pindex) <= '1'; | |
80 |
apbi.p |
|
80 | apbi.pwrite <= '0'; | |
81 |
apbi.p |
|
81 | apbi.penable <= '1'; | |
82 | WAIT UNTIL clk = '1'; |
|
82 | apbi.paddr <= paddr; | |
83 | apbi.psel(pindex) <= '0'; |
|
83 | WAIT UNTIL clk = '1'; | |
84 |
apbi.p |
|
84 | apbi.psel(pindex) <= '0'; | |
85 |
apbi.p |
|
85 | apbi.pwrite <= '0'; | |
86 |
apbi.p |
|
86 | apbi.penable <= '0'; | |
87 | WAIT UNTIL clk = '1'; |
|
87 | apbi.paddr <= (OTHERS => '0'); | |
88 | prdata <= apbo.prdata; |
|
88 | WAIT UNTIL clk = '1'; | |
89 | END APB_READ; |
|
89 | prdata <= apbo.prdata; | |
90 |
|
90 | END APB_READ; | ||
91 | PROCEDURE AHB_READ ( |
|
91 | ||
92 | SIGNAL clk : IN STD_LOGIC; |
|
92 | PROCEDURE AHB_READ ( | |
93 | CONSTANT hindex : IN INTEGER |
|
93 | SIGNAL clk : IN STD_LOGIC; | |
94 | SIGNAL ahbmi : OUT ahb_slv_in_type; |
|
94 | CONSTANT hindex : IN INTEGER; | |
95 |
SIGNAL ahbm |
|
95 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
96 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
96 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
97 |
|
|
97 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | ) IS |
|
98 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
99 | BEGIN |
|
99 | ) IS | |
100 |
|
100 | BEGIN | ||
101 | END AHB_READ; |
|
101 | ahbmo.HADDR <= haddr; | |
102 |
|
102 | ahbmo.HPROT <= "0011"; | ||
103 |
|
103 | ahbmo.HIRQ <= (OTHERS => '0'); | ||
104 |
|
104 | ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); | ||
105 | END testbench_package; |
|
105 | ahbmo.HINDEX <= hindex; | |
|
106 | ahbmo.HBUSREQ <= '1'; | |||
|
107 | ahbmo.HLOCK <= '1'; | |||
|
108 | ahbmo.HSIZE <= HSIZE_WORD; | |||
|
109 | ahbmo.HBURST <= HBURST_SINGLE; | |||
|
110 | ahbmo.HTRANS <= HTRANS_NONSEQ; | |||
|
111 | ahbmo.HWRITE <= '0'; | |||
|
112 | WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
113 | hrdata <= ahbmi.HRDATA; | |||
|
114 | WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
115 | ahbmo.HTRANS <= HTRANS_IDLE; | |||
|
116 | ahbmo.HBUSREQ <= '0'; | |||
|
117 | ahbmo.HLOCK <= '0'; | |||
|
118 | END AHB_READ; | |||
|
119 | ||||
|
120 | END testbench_package; |
@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
|
425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
|
426 | pirq_wfp => 14, | |
427 | hindex => 2, |
|
427 | hindex => 2, | |
428 |
top_lfr_version => X"00000 |
|
428 | top_lfr_version => X"00000F") -- aa.bb.cc version | |
429 | PORT MAP ( |
|
429 | PORT MAP ( | |
430 | clk => clk_25, |
|
430 | clk => clk_25, | |
431 | rstn => reset, |
|
431 | rstn => reset, | |
@@ -446,7 +446,7 BEGIN -- beh | |||||
446 | ChannelCount => 8, |
|
446 | ChannelCount => 8, | |
447 | SampleNbBits => 14, |
|
447 | SampleNbBits => 14, | |
448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
449 |
ncycle_cnv => 2 |
|
449 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
450 | PORT MAP ( |
|
450 | PORT MAP ( | |
451 | -- CONV |
|
451 | -- CONV | |
452 | cnv_clk => clk_24, |
|
452 | cnv_clk => clk_24, |
This diff has been collapsed as it changes many lines, (1050 lines changed) Show them Hide them | |||||
@@ -1,525 +1,525 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
23 | LIBRARY IEEE; |
|
23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 |
|
26 | |||
27 | LIBRARY grlib; |
|
27 | LIBRARY grlib; | |
28 | USE grlib.amba.ALL; |
|
28 | USE grlib.amba.ALL; | |
29 | USE grlib.stdlib.ALL; |
|
29 | USE grlib.stdlib.ALL; | |
30 | USE grlib.devices.ALL; |
|
30 | USE grlib.devices.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 |
|
32 | |||
33 | LIBRARY lpp; |
|
33 | LIBRARY lpp; | |
34 | USE lpp.lpp_waveform_pkg.ALL; |
|
34 | USE lpp.lpp_waveform_pkg.ALL; | |
35 |
|
35 | |||
36 | LIBRARY techmap; |
|
36 | LIBRARY techmap; | |
37 | USE techmap.gencomp.ALL; |
|
37 | USE techmap.gencomp.ALL; | |
38 |
|
38 | |||
39 | ENTITY lpp_waveform IS |
|
39 | ENTITY lpp_waveform IS | |
40 |
|
40 | |||
41 | GENERIC ( |
|
41 | GENERIC ( | |
42 | tech : INTEGER := inferred; |
|
42 | tech : INTEGER := inferred; | |
43 | data_size : INTEGER := 96; --16*6 |
|
43 | data_size : INTEGER := 96; --16*6 | |
44 | nb_data_by_buffer_size : INTEGER := 11; |
|
44 | nb_data_by_buffer_size : INTEGER := 11; | |
45 | nb_word_by_buffer_size : INTEGER := 11; |
|
45 | nb_word_by_buffer_size : INTEGER := 11; | |
46 | nb_snapshot_param_size : INTEGER := 11; |
|
46 | nb_snapshot_param_size : INTEGER := 11; | |
47 | delta_vector_size : INTEGER := 20; |
|
47 | delta_vector_size : INTEGER := 20; | |
48 | delta_vector_size_f0_2 : INTEGER := 3); |
|
48 | delta_vector_size_f0_2 : INTEGER := 3); | |
49 |
|
49 | |||
50 | PORT ( |
|
50 | PORT ( | |
51 | clk : IN STD_LOGIC; |
|
51 | clk : IN STD_LOGIC; | |
52 | rstn : IN STD_LOGIC; |
|
52 | rstn : IN STD_LOGIC; | |
53 |
|
53 | |||
54 | ---- AMBA AHB Master Interface |
|
54 | ---- AMBA AHB Master Interface | |
55 | --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO |
|
55 | --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO | |
56 | --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO |
|
56 | --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO | |
57 |
|
57 | |||
58 | --config |
|
58 | --config | |
59 | reg_run : IN STD_LOGIC; |
|
59 | reg_run : IN STD_LOGIC; | |
60 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
60 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
61 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
61 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
62 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
62 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
63 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
63 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
64 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
64 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
65 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
65 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
66 |
|
66 | |||
67 | enable_f0 : IN STD_LOGIC; |
|
67 | enable_f0 : IN STD_LOGIC; | |
68 | enable_f1 : IN STD_LOGIC; |
|
68 | enable_f1 : IN STD_LOGIC; | |
69 | enable_f2 : IN STD_LOGIC; |
|
69 | enable_f2 : IN STD_LOGIC; | |
70 | enable_f3 : IN STD_LOGIC; |
|
70 | enable_f3 : IN STD_LOGIC; | |
71 |
|
71 | |||
72 | burst_f0 : IN STD_LOGIC; |
|
72 | burst_f0 : IN STD_LOGIC; | |
73 | burst_f1 : IN STD_LOGIC; |
|
73 | burst_f1 : IN STD_LOGIC; | |
74 | burst_f2 : IN STD_LOGIC; |
|
74 | burst_f2 : IN STD_LOGIC; | |
75 |
|
75 | |||
76 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
76 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
77 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
77 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
78 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
78 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
79 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
79 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
80 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
80 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
81 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
81 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
|
82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
83 | --------------------------------------------------------------------------- |
|
83 | --------------------------------------------------------------------------- | |
84 | -- INPUT |
|
84 | -- INPUT | |
85 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
86 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
87 |
|
87 | |||
88 | --f0 |
|
88 | --f0 | |
89 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | data_f0_in_valid : IN STD_LOGIC; |
|
90 | data_f0_in_valid : IN STD_LOGIC; | |
91 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
91 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
92 | --f1 |
|
92 | --f1 | |
93 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | data_f1_in_valid : IN STD_LOGIC; |
|
94 | data_f1_in_valid : IN STD_LOGIC; | |
95 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
95 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
96 | --f2 |
|
96 | --f2 | |
97 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | data_f2_in_valid : IN STD_LOGIC; |
|
98 | data_f2_in_valid : IN STD_LOGIC; | |
99 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
99 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
100 | --f3 |
|
100 | --f3 | |
101 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | data_f3_in_valid : IN STD_LOGIC; |
|
102 | data_f3_in_valid : IN STD_LOGIC; | |
103 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
103 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
104 |
|
104 | |||
105 | --------------------------------------------------------------------------- |
|
105 | --------------------------------------------------------------------------- | |
106 | -- OUTPUT |
|
106 | -- OUTPUT | |
107 | --f0 |
|
107 | --f0 | |
108 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
109 | data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
109 | data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
110 | data_f0_data_out_valid : OUT STD_LOGIC; |
|
110 | data_f0_data_out_valid : OUT STD_LOGIC; | |
111 | data_f0_data_out_valid_burst : OUT STD_LOGIC; |
|
111 | data_f0_data_out_valid_burst : OUT STD_LOGIC; | |
112 | data_f0_data_out_ren : IN STD_LOGIC; |
|
112 | data_f0_data_out_ren : IN STD_LOGIC; | |
113 | --f1 |
|
113 | --f1 | |
114 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
115 | data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
116 | data_f1_data_out_valid : OUT STD_LOGIC; |
|
116 | data_f1_data_out_valid : OUT STD_LOGIC; | |
117 | data_f1_data_out_valid_burst : OUT STD_LOGIC; |
|
117 | data_f1_data_out_valid_burst : OUT STD_LOGIC; | |
118 | data_f1_data_out_ren : IN STD_LOGIC; |
|
118 | data_f1_data_out_ren : IN STD_LOGIC; | |
119 | --f2 |
|
119 | --f2 | |
120 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
122 | data_f2_data_out_valid : OUT STD_LOGIC; |
|
122 | data_f2_data_out_valid : OUT STD_LOGIC; | |
123 | data_f2_data_out_valid_burst : OUT STD_LOGIC; |
|
123 | data_f2_data_out_valid_burst : OUT STD_LOGIC; | |
124 | data_f2_data_out_ren : IN STD_LOGIC; |
|
124 | data_f2_data_out_ren : IN STD_LOGIC; | |
125 | --f3 |
|
125 | --f3 | |
126 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
126 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
128 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
128 | data_f3_data_out_valid : OUT STD_LOGIC; | |
129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
130 | data_f3_data_out_ren : IN STD_LOGIC; |
|
130 | data_f3_data_out_ren : IN STD_LOGIC; | |
131 |
|
131 | |||
132 | --------------------------------------------------------------------------- |
|
132 | --------------------------------------------------------------------------- | |
133 | -- |
|
133 | -- | |
134 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
134 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
135 |
|
135 | |||
136 |
|
136 | |||
137 | ----debug SNAPSHOT OUT |
|
137 | ----debug SNAPSHOT OUT | |
138 | --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
138 | --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
139 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
139 | --debug_f0_data_valid : OUT STD_LOGIC; | |
140 | --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
140 | --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
141 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
141 | --debug_f1_data_valid : OUT STD_LOGIC; | |
142 | --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
142 | --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
143 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
143 | --debug_f2_data_valid : OUT STD_LOGIC; | |
144 | --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
144 | --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
145 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
145 | --debug_f3_data_valid : OUT STD_LOGIC; | |
146 |
|
146 | |||
147 | ----debug FIFO IN |
|
147 | ----debug FIFO IN | |
148 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
148 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
149 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
149 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
150 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
151 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
152 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
153 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
154 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC |
|
155 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC | |
156 |
|
156 | |||
157 | ); |
|
157 | ); | |
158 |
|
158 | |||
159 | END lpp_waveform; |
|
159 | END lpp_waveform; | |
160 |
|
160 | |||
161 | ARCHITECTURE beh OF lpp_waveform IS |
|
161 | ARCHITECTURE beh OF lpp_waveform IS | |
162 | SIGNAL start_snapshot_f0 : STD_LOGIC; |
|
162 | SIGNAL start_snapshot_f0 : STD_LOGIC; | |
163 | SIGNAL start_snapshot_f1 : STD_LOGIC; |
|
163 | SIGNAL start_snapshot_f1 : STD_LOGIC; | |
164 | SIGNAL start_snapshot_f2 : STD_LOGIC; |
|
164 | SIGNAL start_snapshot_f2 : STD_LOGIC; | |
165 |
|
165 | |||
166 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
166 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
167 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
167 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
168 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
168 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
169 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
169 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
170 |
|
170 | |||
171 | SIGNAL data_f0_out_valid : STD_LOGIC; |
|
171 | SIGNAL data_f0_out_valid : STD_LOGIC; | |
172 | SIGNAL data_f1_out_valid : STD_LOGIC; |
|
172 | SIGNAL data_f1_out_valid : STD_LOGIC; | |
173 | SIGNAL data_f2_out_valid : STD_LOGIC; |
|
173 | SIGNAL data_f2_out_valid : STD_LOGIC; | |
174 | SIGNAL data_f3_out_valid : STD_LOGIC; |
|
174 | SIGNAL data_f3_out_valid : STD_LOGIC; | |
175 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); |
|
175 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); | |
176 | -- |
|
176 | -- | |
177 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
177 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
178 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
178 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
179 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
179 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
180 | SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
180 | SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
181 | SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
181 | SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
182 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
182 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
183 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
183 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
184 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
184 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
186 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
186 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
188 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
188 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
189 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
190 | -- |
|
190 | -- | |
191 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
191 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
192 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
192 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
193 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 | SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
194 | SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
195 | -- |
|
195 | -- | |
196 | SIGNAL run : STD_LOGIC; |
|
196 | SIGNAL run : STD_LOGIC; | |
197 | -- |
|
197 | -- | |
198 | TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
198 | TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); | |
199 | SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
199 | SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
200 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
200 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
201 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); |
|
201 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); | |
202 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug |
|
202 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug | |
203 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
203 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
204 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
204 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
205 | -- |
|
205 | -- | |
206 |
|
206 | |||
207 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b |
|
207 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |
208 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
208 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
209 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
209 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
210 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 |
|
211 | |||
212 | -- |
|
212 | -- | |
213 |
|
213 | |||
214 | SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
215 | SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
215 | SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
216 |
|
216 | |||
217 | BEGIN -- beh |
|
217 | BEGIN -- beh | |
218 |
|
218 | |||
219 | ----------------------------------------------------------------------------- |
|
219 | ----------------------------------------------------------------------------- | |
220 | -- DEBUG |
|
220 | -- DEBUG | |
221 | ----------------------------------------------------------------------------- |
|
221 | ----------------------------------------------------------------------------- | |
222 | PROCESS (clk, rstn) |
|
222 | PROCESS (clk, rstn) | |
223 | BEGIN -- PROCESS |
|
223 | BEGIN -- PROCESS | |
224 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
224 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
225 | observation_reg <= (OTHERS => '0'); |
|
225 | observation_reg <= (OTHERS => '0'); | |
226 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
226 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
227 | observation_reg <= observation_reg_s; |
|
227 | observation_reg <= observation_reg_s; | |
228 | END IF; |
|
228 | END IF; | |
229 | END PROCESS; |
|
229 | END PROCESS; | |
230 | observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; |
|
230 | observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; | |
231 | observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; |
|
231 | observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; | |
232 | observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; |
|
232 | observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; | |
233 | observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); |
|
233 | observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); | |
234 | observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); |
|
234 | observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); | |
235 | observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); |
|
235 | observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); | |
236 | ----------------------------------------------------------------------------- |
|
236 | ----------------------------------------------------------------------------- | |
237 |
|
237 | |||
238 | lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler |
|
238 | lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler | |
239 | GENERIC MAP ( |
|
239 | GENERIC MAP ( | |
240 | delta_vector_size => delta_vector_size, |
|
240 | delta_vector_size => delta_vector_size, | |
241 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
241 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
242 | ) |
|
242 | ) | |
243 | PORT MAP ( |
|
243 | PORT MAP ( | |
244 | clk => clk, |
|
244 | clk => clk, | |
245 | rstn => rstn, |
|
245 | rstn => rstn, | |
246 | reg_run => reg_run, |
|
246 | reg_run => reg_run, | |
247 | reg_start_date => reg_start_date, |
|
247 | reg_start_date => reg_start_date, | |
248 | reg_delta_snapshot => reg_delta_snapshot, |
|
248 | reg_delta_snapshot => reg_delta_snapshot, | |
249 | reg_delta_f0 => reg_delta_f0, |
|
249 | reg_delta_f0 => reg_delta_f0, | |
250 | reg_delta_f0_2 => reg_delta_f0_2, |
|
250 | reg_delta_f0_2 => reg_delta_f0_2, | |
251 | reg_delta_f1 => reg_delta_f1, |
|
251 | reg_delta_f1 => reg_delta_f1, | |
252 | reg_delta_f2 => reg_delta_f2, |
|
252 | reg_delta_f2 => reg_delta_f2, | |
253 | coarse_time => coarse_time(30 DOWNTO 0), |
|
253 | coarse_time => coarse_time(30 DOWNTO 0), | |
254 | data_f0_valid => data_f0_in_valid, |
|
254 | data_f0_valid => data_f0_in_valid, | |
255 | data_f2_valid => data_f2_in_valid, |
|
255 | data_f2_valid => data_f2_in_valid, | |
256 | start_snapshot_f0 => start_snapshot_f0, |
|
256 | start_snapshot_f0 => start_snapshot_f0, | |
257 | start_snapshot_f1 => start_snapshot_f1, |
|
257 | start_snapshot_f1 => start_snapshot_f1, | |
258 | start_snapshot_f2 => start_snapshot_f2, |
|
258 | start_snapshot_f2 => start_snapshot_f2, | |
259 | wfp_on => run); |
|
259 | wfp_on => run); | |
260 |
|
260 | |||
261 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot |
|
261 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot | |
262 | GENERIC MAP ( |
|
262 | GENERIC MAP ( | |
263 | data_size => data_size, |
|
263 | data_size => data_size, | |
264 | nb_snapshot_param_size => nb_snapshot_param_size) |
|
264 | nb_snapshot_param_size => nb_snapshot_param_size) | |
265 | PORT MAP ( |
|
265 | PORT MAP ( | |
266 | clk => clk, |
|
266 | clk => clk, | |
267 | rstn => rstn, |
|
267 | rstn => rstn, | |
268 | run => run, |
|
268 | run => run, | |
269 | enable => enable_f0, |
|
269 | enable => enable_f0, | |
270 | burst_enable => burst_f0, |
|
270 | burst_enable => burst_f0, | |
271 | nb_snapshot_param => nb_snapshot_param, |
|
271 | nb_snapshot_param => nb_snapshot_param, | |
272 | start_snapshot => start_snapshot_f0, |
|
272 | start_snapshot => start_snapshot_f0, | |
273 | data_in => data_f0_in, |
|
273 | data_in => data_f0_in, | |
274 | data_in_valid => data_f0_in_valid, |
|
274 | data_in_valid => data_f0_in_valid, | |
275 | data_out => data_f0_out, |
|
275 | data_out => data_f0_out, | |
276 | data_out_valid => data_f0_out_valid); |
|
276 | data_out_valid => data_f0_out_valid); | |
277 |
|
277 | |||
278 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; |
|
278 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; | |
279 |
|
279 | |||
280 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot |
|
280 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot | |
281 | GENERIC MAP ( |
|
281 | GENERIC MAP ( | |
282 | data_size => data_size, |
|
282 | data_size => data_size, | |
283 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
|
283 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |
284 | PORT MAP ( |
|
284 | PORT MAP ( | |
285 | clk => clk, |
|
285 | clk => clk, | |
286 | rstn => rstn, |
|
286 | rstn => rstn, | |
287 | run => run, |
|
287 | run => run, | |
288 | enable => enable_f1, |
|
288 | enable => enable_f1, | |
289 | burst_enable => burst_f1, |
|
289 | burst_enable => burst_f1, | |
290 | nb_snapshot_param => nb_snapshot_param_more_one, |
|
290 | nb_snapshot_param => nb_snapshot_param_more_one, | |
291 | start_snapshot => start_snapshot_f1, |
|
291 | start_snapshot => start_snapshot_f1, | |
292 | data_in => data_f1_in, |
|
292 | data_in => data_f1_in, | |
293 | data_in_valid => data_f1_in_valid, |
|
293 | data_in_valid => data_f1_in_valid, | |
294 | data_out => data_f1_out, |
|
294 | data_out => data_f1_out, | |
295 | data_out_valid => data_f1_out_valid); |
|
295 | data_out_valid => data_f1_out_valid); | |
296 |
|
296 | |||
297 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot |
|
297 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot | |
298 | GENERIC MAP ( |
|
298 | GENERIC MAP ( | |
299 | data_size => data_size, |
|
299 | data_size => data_size, | |
300 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
|
300 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |
301 | PORT MAP ( |
|
301 | PORT MAP ( | |
302 | clk => clk, |
|
302 | clk => clk, | |
303 | rstn => rstn, |
|
303 | rstn => rstn, | |
304 | run => run, |
|
304 | run => run, | |
305 | enable => enable_f2, |
|
305 | enable => enable_f2, | |
306 | burst_enable => burst_f2, |
|
306 | burst_enable => burst_f2, | |
307 | nb_snapshot_param => nb_snapshot_param_more_one, |
|
307 | nb_snapshot_param => nb_snapshot_param_more_one, | |
308 | start_snapshot => start_snapshot_f2, |
|
308 | start_snapshot => start_snapshot_f2, | |
309 | data_in => data_f2_in, |
|
309 | data_in => data_f2_in, | |
310 | data_in_valid => data_f2_in_valid, |
|
310 | data_in_valid => data_f2_in_valid, | |
311 | data_out => data_f2_out, |
|
311 | data_out => data_f2_out, | |
312 | data_out_valid => data_f2_out_valid); |
|
312 | data_out_valid => data_f2_out_valid); | |
313 |
|
313 | |||
314 | lpp_waveform_burst_f3 : lpp_waveform_burst |
|
314 | lpp_waveform_burst_f3 : lpp_waveform_burst | |
315 | GENERIC MAP ( |
|
315 | GENERIC MAP ( | |
316 | data_size => data_size) |
|
316 | data_size => data_size) | |
317 | PORT MAP ( |
|
317 | PORT MAP ( | |
318 | clk => clk, |
|
318 | clk => clk, | |
319 | rstn => rstn, |
|
319 | rstn => rstn, | |
320 | run => run, |
|
320 | run => run, | |
321 | enable => enable_f3, |
|
321 | enable => enable_f3, | |
322 | data_in => data_f3_in, |
|
322 | data_in => data_f3_in, | |
323 | data_in_valid => data_f3_in_valid, |
|
323 | data_in_valid => data_f3_in_valid, | |
324 | data_out => data_f3_out, |
|
324 | data_out => data_f3_out, | |
325 | data_out_valid => data_f3_out_valid); |
|
325 | data_out_valid => data_f3_out_valid); | |
326 |
|
326 | |||
327 | ----------------------------------------------------------------------------- |
|
327 | ----------------------------------------------------------------------------- | |
328 | -- DEBUG -- SNAPSHOT OUT |
|
328 | -- DEBUG -- SNAPSHOT OUT | |
329 | --debug_f0_data_valid <= data_f0_out_valid; |
|
329 | --debug_f0_data_valid <= data_f0_out_valid; | |
330 | --debug_f0_data <= data_f0_out; |
|
330 | --debug_f0_data <= data_f0_out; | |
331 | --debug_f1_data_valid <= data_f1_out_valid; |
|
331 | --debug_f1_data_valid <= data_f1_out_valid; | |
332 | --debug_f1_data <= data_f1_out; |
|
332 | --debug_f1_data <= data_f1_out; | |
333 | --debug_f2_data_valid <= data_f2_out_valid; |
|
333 | --debug_f2_data_valid <= data_f2_out_valid; | |
334 | --debug_f2_data <= data_f2_out; |
|
334 | --debug_f2_data <= data_f2_out; | |
335 | --debug_f3_data_valid <= data_f3_out_valid; |
|
335 | --debug_f3_data_valid <= data_f3_out_valid; | |
336 | --debug_f3_data <= data_f3_out; |
|
336 | --debug_f3_data <= data_f3_out; | |
337 | ----------------------------------------------------------------------------- |
|
337 | ----------------------------------------------------------------------------- | |
338 |
|
338 | |||
339 | PROCESS (clk, rstn) |
|
339 | PROCESS (clk, rstn) | |
340 | BEGIN -- PROCESS |
|
340 | BEGIN -- PROCESS | |
341 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
341 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
342 | time_reg1 <= (OTHERS => '0'); |
|
342 | time_reg1 <= (OTHERS => '0'); | |
343 | time_reg2 <= (OTHERS => '0'); |
|
343 | time_reg2 <= (OTHERS => '0'); | |
344 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
344 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
345 | time_reg1 <= fine_time & coarse_time; |
|
345 | time_reg1 <= fine_time & coarse_time; | |
346 | time_reg2 <= time_reg1; |
|
346 | time_reg2 <= time_reg1; | |
347 | END IF; |
|
347 | END IF; | |
348 | END PROCESS; |
|
348 | END PROCESS; | |
349 |
|
349 | |||
350 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; |
|
350 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; | |
351 | all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE |
|
351 | all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE | |
352 | lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid |
|
352 | lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid | |
353 | PORT MAP ( |
|
353 | PORT MAP ( | |
354 | HCLK => clk, |
|
354 | HCLK => clk, | |
355 | HRESETn => rstn, |
|
355 | HRESETn => rstn, | |
356 | run => run, |
|
356 | run => run, | |
357 | valid_in => valid_in(I), |
|
357 | valid_in => valid_in(I), | |
358 | ack_in => valid_ack(I), |
|
358 | ack_in => valid_ack(I), | |
359 | time_in => time_reg2, -- Todo |
|
359 | time_in => time_reg2, -- Todo | |
360 | valid_out => valid_out(I), |
|
360 | valid_out => valid_out(I), | |
361 | time_out => time_out(I), -- Todo |
|
361 | time_out => time_out(I), -- Todo | |
362 | error => status_new_err(I)); |
|
362 | error => status_new_err(I)); | |
363 | END GENERATE all_input_valid; |
|
363 | END GENERATE all_input_valid; | |
364 |
|
364 | |||
365 | all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE |
|
365 | all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE | |
366 | data_out(0, I) <= data_f0_out(I); |
|
366 | data_out(0, I) <= data_f0_out(I); | |
367 | data_out(1, I) <= data_f1_out(I); |
|
367 | data_out(1, I) <= data_f1_out(I); | |
368 | data_out(2, I) <= data_f2_out(I); |
|
368 | data_out(2, I) <= data_f2_out(I); | |
369 | data_out(3, I) <= data_f3_out(I); |
|
369 | data_out(3, I) <= data_f3_out(I); | |
370 | END GENERATE all_bit_of_data_out; |
|
370 | END GENERATE all_bit_of_data_out; | |
371 |
|
371 | |||
372 | ----------------------------------------------------------------------------- |
|
372 | ----------------------------------------------------------------------------- | |
373 | -- TODO : debug |
|
373 | -- TODO : debug | |
374 | ----------------------------------------------------------------------------- |
|
374 | ----------------------------------------------------------------------------- | |
375 | all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE |
|
375 | all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE | |
376 | all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE |
|
376 | all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE | |
377 | time_out_2(J, I) <= time_out(J)(I); |
|
377 | time_out_2(J, I) <= time_out(J)(I); | |
378 | END GENERATE all_sample_of_time_out; |
|
378 | END GENERATE all_sample_of_time_out; | |
379 | END GENERATE all_bit_of_time_out; |
|
379 | END GENERATE all_bit_of_time_out; | |
380 |
|
380 | |||
381 | -- DEBUG -- |
|
381 | -- DEBUG -- | |
382 | --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; |
|
382 | --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; | |
383 | --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; |
|
383 | --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; | |
384 | --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; |
|
384 | --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; | |
385 | --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; |
|
385 | --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; | |
386 |
|
386 | |||
387 | --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE |
|
387 | --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE | |
388 | -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE |
|
388 | -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE | |
389 | -- time_out_2(J, I) <= time_out_debug(J)(I); |
|
389 | -- time_out_2(J, I) <= time_out_debug(J)(I); | |
390 | -- END GENERATE all_sample_of_time_out; |
|
390 | -- END GENERATE all_sample_of_time_out; | |
391 | --END GENERATE all_bit_of_time_out; |
|
391 | --END GENERATE all_bit_of_time_out; | |
392 | -- DEBUG -- |
|
392 | -- DEBUG -- | |
393 |
|
393 | |||
394 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter |
|
394 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter | |
395 | GENERIC MAP (tech => tech, |
|
395 | GENERIC MAP (tech => tech, | |
396 | nb_data_by_buffer_size => nb_data_by_buffer_size) |
|
396 | nb_data_by_buffer_size => nb_data_by_buffer_size) | |
397 | PORT MAP ( |
|
397 | PORT MAP ( | |
398 | clk => clk, |
|
398 | clk => clk, | |
399 | rstn => rstn, |
|
399 | rstn => rstn, | |
400 | run => run, |
|
400 | run => run, | |
401 | nb_data_by_buffer => nb_data_by_buffer, |
|
401 | nb_data_by_buffer => nb_data_by_buffer, | |
402 | data_in_valid => valid_out, |
|
402 | data_in_valid => valid_out, | |
403 | data_in_ack => valid_ack, |
|
403 | data_in_ack => valid_ack, | |
404 | data_in => data_out, |
|
404 | data_in => data_out, | |
405 | time_in => time_out_2, |
|
405 | time_in => time_out_2, | |
406 |
|
406 | |||
407 | data_out => wdata, |
|
407 | data_out => wdata, | |
408 | data_out_wen => data_wen, |
|
408 | data_out_wen => data_wen, | |
409 | full_almost => full_almost, |
|
409 | full_almost => full_almost, | |
410 | full => full); |
|
410 | full => full); | |
411 |
|
411 | |||
412 | ----------------------------------------------------------------------------- |
|
412 | ----------------------------------------------------------------------------- | |
413 | -- DEBUG -- SNAPSHOT IN |
|
413 | -- DEBUG -- SNAPSHOT IN | |
414 | --debug_f0_data_fifo_in_valid <= NOT data_wen(0); |
|
414 | --debug_f0_data_fifo_in_valid <= NOT data_wen(0); | |
415 | --debug_f0_data_fifo_in <= wdata; |
|
415 | --debug_f0_data_fifo_in <= wdata; | |
416 | --debug_f1_data_fifo_in_valid <= NOT data_wen(1); |
|
416 | --debug_f1_data_fifo_in_valid <= NOT data_wen(1); | |
417 | --debug_f1_data_fifo_in <= wdata; |
|
417 | --debug_f1_data_fifo_in <= wdata; | |
418 | --debug_f2_data_fifo_in_valid <= NOT data_wen(2); |
|
418 | --debug_f2_data_fifo_in_valid <= NOT data_wen(2); | |
419 | --debug_f2_data_fifo_in <= wdata; |
|
419 | --debug_f2_data_fifo_in <= wdata; | |
420 | --debug_f3_data_fifo_in_valid <= NOT data_wen(3); |
|
420 | --debug_f3_data_fifo_in_valid <= NOT data_wen(3); | |
421 | --debug_f3_data_fifo_in <= wdata;s |
|
421 | --debug_f3_data_fifo_in <= wdata;s | |
422 | ----------------------------------------------------------------------------- |
|
422 | ----------------------------------------------------------------------------- | |
423 |
|
423 | |||
424 | lpp_waveform_fifo_1 : lpp_waveform_fifo |
|
424 | lpp_waveform_fifo_1 : lpp_waveform_fifo | |
425 | GENERIC MAP (tech => tech) |
|
425 | GENERIC MAP (tech => tech) | |
426 | PORT MAP ( |
|
426 | PORT MAP ( | |
427 | clk => clk, |
|
427 | clk => clk, | |
428 | rstn => rstn, |
|
428 | rstn => rstn, | |
429 | run => run, |
|
429 | run => run, | |
430 |
|
430 | |||
431 | empty => s_empty, |
|
431 | empty => s_empty, | |
432 | empty_almost => s_empty_almost, |
|
432 | empty_almost => s_empty_almost, | |
433 | data_ren => s_data_ren, |
|
433 | data_ren => s_data_ren, | |
434 | rdata => s_rdata, |
|
434 | rdata => s_rdata, | |
435 |
|
435 | |||
436 |
|
436 | |||
437 | full_almost => full_almost, |
|
437 | full_almost => full_almost, | |
438 | full => full, |
|
438 | full => full, | |
439 | data_wen => data_wen, |
|
439 | data_wen => data_wen, | |
440 | wdata => wdata); |
|
440 | wdata => wdata); | |
441 |
|
441 | |||
442 | lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg |
|
442 | lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg | |
443 | GENERIC MAP (tech => tech) |
|
443 | GENERIC MAP (tech => tech) | |
444 | PORT MAP ( |
|
444 | PORT MAP ( | |
445 | clk => clk, |
|
445 | clk => clk, | |
446 | rstn => rstn, |
|
446 | rstn => rstn, | |
447 | run => run, |
|
447 | run => run, | |
448 | o_empty_almost => empty_almost, |
|
448 | o_empty_almost => empty_almost, | |
449 | o_empty => empty, |
|
449 | o_empty => empty, | |
450 |
|
450 | |||
451 | o_data_ren => data_ren, |
|
451 | o_data_ren => data_ren, | |
452 | o_rdata_0 => data_f0_data_out, |
|
452 | o_rdata_0 => data_f0_data_out, | |
453 | o_rdata_1 => data_f1_data_out, |
|
453 | o_rdata_1 => data_f1_data_out, | |
454 | o_rdata_2 => data_f2_data_out, |
|
454 | o_rdata_2 => data_f2_data_out, | |
455 | o_rdata_3 => data_f3_data_out, |
|
455 | o_rdata_3 => data_f3_data_out, | |
456 |
|
456 | |||
457 | i_empty_almost => s_empty_almost, |
|
457 | i_empty_almost => s_empty_almost, | |
458 | i_empty => s_empty, |
|
458 | i_empty => s_empty, | |
459 | i_data_ren => s_data_ren, |
|
459 | i_data_ren => s_data_ren, | |
460 | i_rdata => s_rdata); |
|
460 | i_rdata => s_rdata); | |
461 |
|
461 | |||
462 |
|
462 | |||
463 | --data_f0_data_out <= rdata; |
|
463 | --data_f0_data_out <= rdata; | |
464 | --data_f1_data_out <= rdata; |
|
464 | --data_f1_data_out <= rdata; | |
465 | --data_f2_data_out <= rdata; |
|
465 | --data_f2_data_out <= rdata; | |
466 | --data_f3_data_out <= rdata; |
|
466 | --data_f3_data_out <= rdata; | |
467 |
|
467 | |||
468 | data_ren <= data_f3_data_out_ren & |
|
468 | data_ren <= data_f3_data_out_ren & | |
469 | data_f2_data_out_ren & |
|
469 | data_f2_data_out_ren & | |
470 | data_f1_data_out_ren & |
|
470 | data_f1_data_out_ren & | |
471 | data_f0_data_out_ren; |
|
471 | data_f0_data_out_ren; | |
472 |
|
472 | |||
473 | lpp_waveform_gen_address_1 : lpp_waveform_genaddress |
|
473 | lpp_waveform_gen_address_1 : lpp_waveform_genaddress | |
474 | GENERIC MAP ( |
|
474 | GENERIC MAP ( | |
475 | nb_data_by_buffer_size => nb_word_by_buffer_size) |
|
475 | nb_data_by_buffer_size => nb_word_by_buffer_size) | |
476 | PORT MAP ( |
|
476 | PORT MAP ( | |
477 | clk => clk, |
|
477 | clk => clk, | |
478 | rstn => rstn, |
|
478 | rstn => rstn, | |
479 | run => run, |
|
479 | run => run, | |
480 |
|
480 | |||
481 | ------------------------------------------------------------------------- |
|
481 | ------------------------------------------------------------------------- | |
482 | -- CONFIG |
|
482 | -- CONFIG | |
483 | ------------------------------------------------------------------------- |
|
483 | ------------------------------------------------------------------------- | |
484 | nb_data_by_buffer => nb_word_by_buffer, |
|
484 | nb_data_by_buffer => nb_word_by_buffer, | |
485 |
|
485 | |||
486 | addr_data_f0 => addr_data_f0, |
|
486 | addr_data_f0 => addr_data_f0, | |
487 | addr_data_f1 => addr_data_f1, |
|
487 | addr_data_f1 => addr_data_f1, | |
488 | addr_data_f2 => addr_data_f2, |
|
488 | addr_data_f2 => addr_data_f2, | |
489 | addr_data_f3 => addr_data_f3, |
|
489 | addr_data_f3 => addr_data_f3, | |
490 | ------------------------------------------------------------------------- |
|
490 | ------------------------------------------------------------------------- | |
491 | -- CTRL |
|
491 | -- CTRL | |
492 | ------------------------------------------------------------------------- |
|
492 | ------------------------------------------------------------------------- | |
493 | -- IN |
|
493 | -- IN | |
494 | empty => empty, |
|
494 | empty => empty, | |
495 | empty_almost => empty_almost, |
|
495 | empty_almost => empty_almost, | |
496 | data_ren => data_ren, |
|
496 | data_ren => data_ren, | |
497 |
|
497 | |||
498 | ------------------------------------------------------------------------- |
|
498 | ------------------------------------------------------------------------- | |
499 | -- STATUS |
|
499 | -- STATUS | |
500 | ------------------------------------------------------------------------- |
|
500 | ------------------------------------------------------------------------- | |
501 | status_full => status_full_s, |
|
501 | status_full => status_full_s, | |
502 | status_full_ack => status_full_ack, |
|
502 | status_full_ack => status_full_ack, | |
503 | status_full_err => status_full_err, |
|
503 | status_full_err => status_full_err, | |
504 |
|
504 | |||
505 | ------------------------------------------------------------------------- |
|
505 | ------------------------------------------------------------------------- | |
506 | -- ADDR DATA OUT |
|
506 | -- ADDR DATA OUT | |
507 | ------------------------------------------------------------------------- |
|
507 | ------------------------------------------------------------------------- | |
508 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, |
|
508 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, | |
509 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, |
|
509 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, | |
510 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, |
|
510 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, | |
511 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, |
|
511 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, | |
512 |
|
512 | |||
513 | data_f0_data_out_valid => data_f0_data_out_valid, |
|
513 | data_f0_data_out_valid => data_f0_data_out_valid, | |
514 | data_f1_data_out_valid => data_f1_data_out_valid, |
|
514 | data_f1_data_out_valid => data_f1_data_out_valid, | |
515 | data_f2_data_out_valid => data_f2_data_out_valid, |
|
515 | data_f2_data_out_valid => data_f2_data_out_valid, | |
516 | data_f3_data_out_valid => data_f3_data_out_valid, |
|
516 | data_f3_data_out_valid => data_f3_data_out_valid, | |
517 |
|
517 | |||
518 | data_f0_addr_out => data_f0_addr_out, |
|
518 | data_f0_addr_out => data_f0_addr_out, | |
519 | data_f1_addr_out => data_f1_addr_out, |
|
519 | data_f1_addr_out => data_f1_addr_out, | |
520 | data_f2_addr_out => data_f2_addr_out, |
|
520 | data_f2_addr_out => data_f2_addr_out, | |
521 | data_f3_addr_out => data_f3_addr_out |
|
521 | data_f3_addr_out => data_f3_addr_out | |
522 | ); |
|
522 | ); | |
523 | status_full <= status_full_s; |
|
523 | status_full <= status_full_s; | |
524 |
|
524 | |||
525 | END beh; No newline at end of file |
|
525 | END beh; |
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