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LFR-EQM (edn file send to Altran)
pellion -
r618:12ec00ce062e simu_with_Leon3
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@@ -75,10 +75,10 set_io spw2_sin -pinname 304 -fixed yes
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
77
77
78 set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout
78 #set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout
79 #set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout
79 set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout
80 #set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout
81 #set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout
81 set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout
82 #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout
82 #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout
83 #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout
83 #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout
84 #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout
84 #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout
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@@ -92,10 +92,9 set_min_delay 0.000 -from [get_clocks {c
92
92
93 ######## Delay Constraints ########
93 ######## Delay Constraints ########
94
94
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
96
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
98
99
98
100
99
101 ######## Delay Constraints ########
100 ######## Delay Constraints ########
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@@ -29,3 +29,7 create_clock -name SPW_CLOCK -period 100
29 # set_wire_load_mode top
29 # set_wire_load_mode top
30
30
31 # Other Constraints
31 # Other Constraints
32
33 set_max_delay 4.000 -from [get_ports { SPW_NOM_DIN SPW_NOM_SIN SPW_RED_DIN SPW_RED_SIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
34
35 set_max_delay 4.000 -from [get_ports { SPW_NOM_DIN SPW_NOM_SIN SPW_RED_DIN SPW_RED_SIN reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
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@@ -143,8 +143,7 ARCHITECTURE beh OF TB IS
143 SIGNAL spw2_sout : STD_LOGIC;
143 SIGNAL spw2_sout : STD_LOGIC;
144 SIGNAL bias_fail_sw : STD_LOGIC;
144 SIGNAL bias_fail_sw : STD_LOGIC;
145 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
147 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
148 SIGNAL ADC_smpclk : STD_LOGIC;
147 SIGNAL ADC_smpclk : STD_LOGIC;
149 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
148 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
150 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
@@ -286,7 +285,7 BEGIN -- beh
286 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
285 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
287 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
288
287
289 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
288 MODULE_RHF1401 : FOR I IN 0 TO 8 GENERATE
290 TestModule_RHF1401_1 : TestModule_RHF1401
289 TestModule_RHF1401_1 : TestModule_RHF1401
291 GENERIC MAP (
290 GENERIC MAP (
292 freq => 2400,--24*(I*5+1),
291 freq => 2400,--24*(I*5+1),
@@ -299,8 +298,8 BEGIN -- beh
299 --ADC_data_s <= "00" & X"190";
298 --ADC_data_s <= "00" & X"190";
300 END GENERATE MODULE_RHF1401;
299 END GENERATE MODULE_RHF1401;
301
300
302 ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns;
301 ADC_OEB_bar_CH_s <= TRANSPORT (ADC_OEB_bar_HK & ADC_OEB_bar_CH) AFTER 10 ns;
303 ADC_data <= TRANSPORT ADC_data_s AFTER 35 ns;
302 ADC_data <= TRANSPORT ADC_data_s AFTER 55 ns;
304 -----------------------------------------------------------------------------
303 -----------------------------------------------------------------------------
305 PROCESS (clk50MHz, reset)
304 PROCESS (clk50MHz, reset)
306 BEGIN -- PROCESS
305 BEGIN -- PROCESS
@@ -665,6 +664,9 BEGIN -- beh
665 -----------------------------------------------------------------------------
664 -----------------------------------------------------------------------------
666 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
665 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
667
666
667 data_ram <= TRANSPORT data AFTER 45 ns WHEN nSRAM_W = '0' ELSE (OTHERS => 'Z');
668 data <= TRANSPORT data_ram AFTER 45 ns WHEN nSRAM_W = '1' ELSE (OTHERS => 'Z');
669
668 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
670 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
669 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
671 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
670 sr0 : sram
672 sr0 : sram
@@ -674,7 +676,7 BEGIN -- beh
674 fname => sramfile)
676 fname => sramfile)
675 PORT MAP (
677 PORT MAP (
676 address,
678 address,
677 data(31-i*8 DOWNTO 24-i*8),
679 data_ram(31-i*8 DOWNTO 24-i*8),
678 ramsn(k),
680 ramsn(k),
679 nSRAM_W,
681 nSRAM_W,
680 nSRAM_G
682 nSRAM_G
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@@ -5,32 +5,26 quietly virtual signal -install /tb/LFR_
5 quietly WaveActivateNextPane {} 0
5 quietly WaveActivateNextPane {} 0
6 add wave -noupdate -expand -group ALL /tb/data_message
6 add wave -noupdate -expand -group ALL /tb/data_message
7 add wave -noupdate -expand -group ALL /tb/message_simu
7 add wave -noupdate -expand -group ALL /tb/message_simu
8 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
8 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
9 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
10 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
11 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
12 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 add wave -noupdate -expand -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
13 add wave -noupdate -expand -group ALL -expand -group RAM /tb/data_ram
14 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
14 add wave -noupdate -expand -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
15 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
15 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
16 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
16 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
17 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
17 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
18 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
18 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
19 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
19 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
20 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
20 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s
21 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
21 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg
22 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn
22 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync
23 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling
23 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
24 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s
24 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
25 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg
25 add wave -noupdate -expand -group ALL -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter
26 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync
26 add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK
27 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_reg
27 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH
28 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
29 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
30 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
31 add wave -noupdate -expand -group ALL -expand -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter
32 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK
33 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH
34 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
28 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
35 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
29 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
36 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
30 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
@@ -46,7 +40,6 add wave -noupdate -expand -group ALL -g
46 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
40 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
47 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
41 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
48 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
42 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
49 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
50 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
43 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
51 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
44 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
52 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
45 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
@@ -68,7 +61,6 add wave -noupdate -expand -group ALL -g
68 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
61 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
69 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
62 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
70 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
63 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
71 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
72 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
64 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
73 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
65 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
74 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
66 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
@@ -124,10 +116,6 add wave -noupdate -expand -group ALL -r
124 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
116 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
125 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
117 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
126 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
118 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
127 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
128 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid_s
129 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
130 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val_s2
131 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
119 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
132 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
120 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
133 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
121 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
@@ -143,62 +131,47 add wave -noupdate -expand -group ALL -r
143 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
131 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
144 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
132 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
145 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
133 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
146 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
147 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
148 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
134 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
149 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
150 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
151 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
135 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
152 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
136 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
153 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
137 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
154 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
138 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
155 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
139 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
156 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 15 -max 7517.0 -min -7504.0 -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) {-height 15 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
140 add wave -noupdate -expand /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
157 add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val
141 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_pre
158 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in
142 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling_edge
159 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
143 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync
160 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out
144 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg
161 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg
145 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s
162 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg
146 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter
163 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg
147 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_sel_n
164 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg
148 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_r
165 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg
149 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_r2
166 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg
150 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_d1
167 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg
151 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter
168 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg
152 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/MAX_CHANNEL_COUNTER
169 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 74 -max 14061.999999999998 -min -14378.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim
153 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/FILTER_ENABLED_STDLOGIC
170 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim
154 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
171 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim
155 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
172 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim
156 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_d1
173 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/sample(8) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(7) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(6) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(5) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(4) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(3) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(2) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(1) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(0) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal}} /tb/LFR_EQM_1/sample
174 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample_s(8) -radix decimal} {/tb/LFR_EQM_1/sample_s(7) -radix decimal} {/tb/LFR_EQM_1/sample_s(6) -radix decimal} {/tb/LFR_EQM_1/sample_s(5) -radix decimal} {/tb/LFR_EQM_1/sample_s(4) -radix decimal} {/tb/LFR_EQM_1/sample_s(3) -radix decimal} {/tb/LFR_EQM_1/sample_s(2) -radix decimal} {/tb/LFR_EQM_1/sample_s(1) -radix decimal} {/tb/LFR_EQM_1/sample_s(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/sample_s(8) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/sample_s
175 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in
176 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim
177 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out
178 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0
179 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
180 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
181 add wave -noupdate /tb/LFR_EQM_1/sample_val
182 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn
183 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
184 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
185 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
186 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out
187 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_wen
188 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/wdata
189 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_data
190 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_ren
191 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_buffer_full
192 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/data
193 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
194 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/address
195 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
196 add wave -noupdate -expand /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/fifo_ren
197 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
198 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
157 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
158 add wave -noupdate -expand /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
159 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
160 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
161 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
162 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
163 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
164 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
165 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
166 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
167 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/FILTER_ENABLED
168 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ChanelCount
169 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
170 add wave -noupdate -expand /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbo
171 add wave -noupdate -expand -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbi.hgrant -expand} /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbi
199 TreeUpdate [SetDefaultTree]
172 TreeUpdate [SetDefaultTree]
200 WaveRestoreCursors {{Cursor 1} {42970000 ps} 0} {{Cursor 2} {33108681 ps} 0} {{Cursor 3} {515290000 ps} 0} {{Cursor 4} {8300650000 ps} 0}
173 WaveRestoreCursors {{Cursor 1} {42970000 ps} 0} {{Cursor 2} {35941209 ps} 0} {{Cursor 3} {2025053000 ps} 0} {{Cursor 4} {8300650000 ps} 0}
201 quietly wave cursor active 1
174 quietly wave cursor active 3
202 configure wave -namecolwidth 619
175 configure wave -namecolwidth 619
203 configure wave -valuecolwidth 311
176 configure wave -valuecolwidth 311
204 configure wave -justifyvalue left
177 configure wave -justifyvalue left
@@ -213,4 +186,4 configure wave -griddelta 40
213 configure wave -timeline 0
186 configure wave -timeline 0
214 configure wave -timelineunits ns
187 configure wave -timelineunits ns
215 update
188 update
216 WaveRestoreZoom {31103383 ps} {50275736 ps}
189 WaveRestoreZoom {1879745491179 ps} {1880033658360 ps}
Show file before | Show file after | Hide comments
@@ -317,7 +317,7 BEGIN -- beh
317 FPU_NETLIST => 0,
317 FPU_NETLIST => 0,
318 ENABLE_DSU => 1,
318 ENABLE_DSU => 1,
319 ENABLE_AHB_UART => 0,
319 ENABLE_AHB_UART => 0,
320 ENABLE_APB_UART => 0,
320 ENABLE_APB_UART => 1,
321 ENABLE_IRQMP => 1,
321 ENABLE_IRQMP => 1,
322 ENABLE_GPT => 1,
322 ENABLE_GPT => 1,
323 NB_AHB_MASTER => NB_AHB_MASTER,
323 NB_AHB_MASTER => NB_AHB_MASTER,
@@ -331,8 +331,8 BEGIN -- beh
331 clk => clk_25,
331 clk => clk_25,
332 reset => rstn_25,
332 reset => rstn_25,
333 errorn => errorn,
333 errorn => errorn,
334 ahbrxd => TXD1,
334 ahbrxd => OPEN,--TXD1,
335 ahbtxd => RXD1,
335 ahbtxd => OPEN,--RXD1,
336 urxd1 => TXD2,
336 urxd1 => TXD2,
337 utxd1 => RXD2,
337 utxd1 => RXD2,
338 address => SRAM_A,
338 address => SRAM_A,
@@ -653,4 +653,4 BEGIN -- beh
653 END GENERATE ahbo_m_ext_not_used;
653 END GENERATE ahbo_m_ext_not_used;
654 END GENERATE all_ahbo_m_ext;
654 END GENERATE all_ahbo_m_ext;
655
655
656 END beh;
656 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -13,8 +13,9 SYNPOPT="set_option -pipe 0; set_option
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 VHDLSIMFILES= testbench.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 SIMTOP=testbench
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 ##PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 PDC=$(VHDLIB)/boards/$(BOARD)/no_uart.pdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
Show file before | Show file after | Hide comments
@@ -180,9 +180,14 BEGIN
180 STATE_CIC_LFR <= RUN_PROG_I;
180 STATE_CIC_LFR <= RUN_PROG_I;
181 current_cmd <= PROG_START_I;
181 current_cmd <= PROG_START_I;
182 current_channel <= 0;
182 current_channel <= 0;
183 IF nb_data_receipt = 255 THEN
184 nb_data_receipt <= 0;
185 ELSE
183 nb_data_receipt <= nb_data_receipt + 1;
186 nb_data_receipt <= nb_data_receipt + 1;
184 END IF;
187 END IF;
185
188
189 END IF;
190
186 WHEN RUN_PROG_I =>
191 WHEN RUN_PROG_I =>
187 IF current_cmd = PROG_END_I THEN
192 IF current_cmd = PROG_END_I THEN
188 IF nb_data_receipt MOD 16 = 15 THEN
193 IF nb_data_receipt MOD 16 = 15 THEN
@@ -246,4 +251,4 BEGIN
246 END IF;
251 END IF;
247 END PROCESS;
252 END PROCESS;
248
253
249 END beh; No newline at end of file
254 END beh;
Show file before | Show file after | Hide comments
@@ -30,27 +30,36 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 -----------------------------------------------------------------------------
34 -- CNV GEN
35 -----------------------------------------------------------------------------
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
36 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 SIGNAL cnv_s : STD_LOGIC;
37 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
38 SIGNAL cnv_s_reg : STD_LOGIC;
39
40 -----------------------------------------------------------------------------
41 -- SYNC CNV
42 -----------------------------------------------------------------------------
36 SIGNAL cnv_sync : STD_LOGIC;
43 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
44 SIGNAL cnv_sync_pre : STD_LOGIC;
38 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
45 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
39
46
40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
47 -----------------------------------------------------------------------------
41 SIGNAL enable_ADC : STD_LOGIC;
48 -- DATA Read and Data Output Enable
49 -----------------------------------------------------------------------------
50 CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5;
51 SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
52 SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
53 SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
54 SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
42
55
56 SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
43
57
44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
58 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45
59 SIGNAL ADC_data_d1 : Samples14;
46 SIGNAL channel_counter : INTEGER;
47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48
49 SIGNAL ADC_data_selected : Samples14;
60 SIGNAL ADC_data_selected : Samples14;
50 SIGNAL ADC_data_result : Samples15;
61 SIGNAL ADC_data_result : Samples15;
51
62
52 SIGNAL sample_counter : INTEGER;
53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54
63
55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
64 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
56
65
@@ -105,95 +114,82 BEGIN
105 A => cnv_s_reg,
114 A => cnv_s_reg,
106 A_sync => cnv_sync);
115 A_sync => cnv_sync);
107
116
108 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
109
110 -----------------------------------------------------------------------------
111 -- DATA GEN Output Enable
112 -----------------------------------------------------------------------------
113 PROCESS (clk, rstn)
114 BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
117 cnv_sync_pre <= '0';
118 enable_ADC <= '0';
119 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
120 cnv_sync_pre <= cnv_sync;
121 IF cnv_sync_falling_edge = '1' THEN
122 enable_ADC <= '1';
123 ADC_nOE_reg(0) <= '0';
124 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
125 ELSE
126 enable_ADC <= NOT enable_ADC;
127 IF enable_ADC = '0' THEN
128 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
129 END IF;
130 END IF;
131
132 END IF;
133 END PROCESS;
134
135 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
136
137 -----------------------------------------------------------------------------
138 -- ADC READ DATA
139 -----------------------------------------------------------------------------
140 PROCESS (clk, rstn)
117 PROCESS (clk, rstn)
141 BEGIN -- PROCESS
118 BEGIN -- PROCESS
142 IF rstn = '0' THEN -- asynchronous reset (active low)
119 IF rstn = '0' THEN -- asynchronous reset (active low)
143 channel_counter <= MAX_COUNTER;
120 cnv_sync_pre <= '0';
121 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
122 cnv_sync_pre <= cnv_sync;
123 END IF;
124 END PROCESS;
125
126 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
127
144
128
145 all_sample_reg_init : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
129 -----------------------------------------------------------------------------
146 sample_reg(I) <= (OTHERS => '0');
130 -- DATA Read and Data Output Enable
147 END LOOP all_sample_reg_init;
131 -----------------------------------------------------------------------------
148
132
133 PROCESS (clk, rstn)
134 BEGIN -- PROCESS
135 IF rstn = '0' THEN -- asynchronous reset (active low)
136 channel_counter <= MAX_CHANNEL_COUNTER;
149 sample_val <= '0';
137 sample_val <= '0';
150 sample_counter <= 0;
138 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
151 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
152 IF cnv_sync_falling_edge = '1' THEN
139 IF cnv_sync_falling_edge = '1' THEN
153 channel_counter <= 0;
140 channel_counter <= 0;
154 ELSE
141 ELSE
155 IF channel_counter < MAX_COUNTER THEN
142 IF channel_counter < MAX_CHANNEL_COUNTER THEN
156 channel_counter <= channel_counter + 1;
143 channel_counter <= channel_counter + 1;
157 END IF;
144 END IF;
158 END IF;
145 END IF;
159 sample_val <= '0';
160
146
161 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
147 IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN
162 IF channel_counter = I*2 THEN
163 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
164 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
165 ELSE
166 sample_reg(I) <= ADC_data;
167 END IF;
168 END IF;
169 END LOOP all_sample_reg;
170
171 IF channel_counter = (ChanelCount-1)*2 THEN
172
173 IF sample_counter = MAX_SAMPLE_COUNTER THEN
174 sample_counter <= 0;
175 sample_val <= '1';
148 sample_val <= '1';
176 ELSE
149 ELSE
177 sample_counter <= sample_counter +1;
150 sample_val <= '0';
178 END IF;
179
180 END IF;
151 END IF;
181 END IF;
152 END IF;
182 END PROCESS;
153 END PROCESS;
183
154
184 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
155 all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE
185 -- BEGIN -- PROCESS mux_adc
156 channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1';
186 -- CASE channel_counter IS
157
187 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
158 PROCESS (clk, rstn)
188 -- END CASE;
159 BEGIN -- PROCESS
189 -- END PROCESS mux_adc;
160 IF rstn = '0' THEN -- asynchronous reset (active low)
161 sample_reg(I) <= (OTHERS => '0');
162 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
163 IF channel_counter_d1 = 2*I THEN
164 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
165 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
166 ELSE
167 sample_reg(I) <= ADC_data_d1;
168 END IF;
169 END IF;
170 END IF;
171 END PROCESS;
190
172
173 END GENERATE all_channel;
191
174
192 -----------------------------------------------------------------------------
175 PROCESS (clk, rstn)
193 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
176 BEGIN -- PROCESS
194 -----------------------------------------------------------------------------
177 IF rstn = '0' THEN -- asynchronous reset (active low)
178 ADC_nOE <= (OTHERS => '1');
179 channel_counter_r <= MAX_CHANNEL_COUNTER;
180 channel_counter_r2 <= MAX_CHANNEL_COUNTER;
181 channel_counter_d1 <= MAX_CHANNEL_COUNTER;
182 ADC_data_d1 <= (OTHERS => '0');
183 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
184 ADC_nOE <= channel_sel_n;
185 channel_counter_r <= channel_counter;
186 channel_counter_r2 <= channel_counter_r;
187 channel_counter_d1 <= channel_counter_r2;
188 ADC_data_d1 <= ADC_data;
189 END IF;
190 END PROCESS;
195
191
196 WITH channel_counter SELECT
192 WITH channel_counter_d1 SELECT
197 ADC_data_selected <= sample_reg(0) WHEN 0*2,
193 ADC_data_selected <= sample_reg(0) WHEN 0*2,
198 sample_reg(1) WHEN 1*2,
194 sample_reg(1) WHEN 1*2,
199 sample_reg(2) WHEN 2*2,
195 sample_reg(2) WHEN 2*2,
@@ -204,14 +200,12 BEGIN
204 sample_reg(7) WHEN 7*2,
200 sample_reg(7) WHEN 7*2,
205 sample_reg(8) WHEN OTHERS;
201 sample_reg(8) WHEN OTHERS;
206
202
207 -----------------------------------------------------------------------------
203 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1)));
208 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
209 -----------------------------------------------------------------------------
210
211 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data(13) & ADC_data)));
212
204
213 sample <= sample_reg;
205 sample <= sample_reg;
214
206
207
208
215 END ar_top_ad_conv_RHF1401;
209 END ar_top_ad_conv_RHF1401;
216
210
217
211
Show file before | Show file after | Hide comments
@@ -42,41 +42,61 ENTITY SPI_DAC_DRIVER IS
42 END ENTITY SPI_DAC_DRIVER;
42 END ENTITY SPI_DAC_DRIVER;
43
43
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 SIGNAL DATA_s : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
47 SIGNAL SMP_CLK_RisingEdge : STD_LOGIC := '0';
48 SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
49 SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
50
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
51 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 SIGNAL shiftcnt : INTEGER := 0;
52 SIGNAL shiftcnt : INTEGER := 0;
49 SIGNAL shifting : STD_LOGIC := '0';
53 SIGNAL shifting : STD_LOGIC := '0';
50
54
51 SIGNAL SCLK_s : STD_LOGIC;
55 SIGNAL SCLK_s : STD_LOGIC;
52 BEGIN
56 BEGIN
53
57
58 -----------------------------------------------------------------------------
59 -- Data Re-Orderng
60 -----------------------------------------------------------------------------
54
61
55 MSB : IF MSBFIRST = 1 GENERATE
62 MSB : IF MSBFIRST = 1 GENERATE
56 INPUTREG <= DATA;
63 DATA_s <= DATA;
57 END GENERATE;
64 END GENERATE;
58
65
59 LSB : IF MSBFIRST = 0 GENERATE
66 LSB : IF MSBFIRST = 0 GENERATE
60 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
67 DATA_s(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
61 END GENERATE;
68 END GENERATE;
62
69
70 -----------------------------------------------------------------------------
71 --
72 -----------------------------------------------------------------------------
73 PROCESS(clk, rstn)
74 BEGIN
75 IF rstn = '0' THEN
76 SMP_CLK_R <= '0';
77 SMP_CLK_RisingEdge_2 <= '0';
78 ELSIF clk'EVENT AND clk = '1' THEN
79 SMP_CLK_R <= SMP_CLK;
80 SMP_CLK_RisingEdge_2 <= SMP_CLK_RisingEdge_1;
81 END IF;
82 END PROCESS;
83
84 SMP_CLK_RisingEdge_1 <= '1' WHEN SMP_CLK = '1' AND SMP_CLK_R = '0' ELSE '0';
85 SMP_CLK_RisingEdge <= '1' WHEN SMP_CLK_RisingEdge_1 = '1' OR SMP_CLK_RisingEdge_2 = '1' ELSE '0';
86
87
88 -----------------------------------------------------------------------------
89 --
90 -----------------------------------------------------------------------------
91 SCLK <= SCLK_s;
92 DOUT <= SHIFTREG(datawidth-1);
93
63 PROCESS (clk, rstn)
94 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
95 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
96 IF rstn = '0' THEN -- asynchronous reset (active low)
66 SCLK_s <= '0';
97 SCLK_s <= '0';
67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
98 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 SCLK_s <= NOT SCLK_s;
99 SCLK_s <= NOT SCLK_s;
69
70 END IF;
71 END PROCESS;
72 SCLK <= SCLK_s;
73
74 PROCESS(clk, rstn)
75 BEGIN
76 IF rstn = '0' THEN
77 SMP_CLK_R <= '0';
78 ELSIF clk'EVENT AND clk = '1' THEN
79 SMP_CLK_R <= SMP_CLK;
80 END IF;
100 END IF;
81 END PROCESS;
101 END PROCESS;
82
102
@@ -87,10 +107,11 BEGIN
87 SHIFTREG <= (OTHERS => '0');
107 SHIFTREG <= (OTHERS => '0');
88 SYNC <= '0';
108 SYNC <= '0';
89 shiftcnt <= 0;
109 shiftcnt <= 0;
90 DOUT <= '0';
91 ELSIF clk'EVENT AND clk = '1' THEN
110 ELSIF clk'EVENT AND clk = '1' THEN
92 DOUT <= SHIFTREG(datawidth-1);
111
93 IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
112 IF SCLK_s = '0' THEN
113
114 IF SMP_CLK_RisingEdge = '1' THEN
94 SYNC <= '1';
115 SYNC <= '1';
95 shifting <= '1';
116 shifting <= '1';
96 ELSE
117 ELSE
@@ -99,16 +120,17 BEGIN
99 shifting <= '0';
120 shifting <= '0';
100 END IF;
121 END IF;
101 END IF;
122 END IF;
123
102 IF shifting = '1' THEN
124 IF shifting = '1' THEN
103 shiftcnt <= shiftcnt + 1;
125 shiftcnt <= shiftcnt + 1;
104 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
126 SHIFTREG(datawidth-1 DOWNTO 1) <= SHIFTREG (datawidth-2 DOWNTO 0);
105
106 ELSE
127 ELSE
107 SHIFTREG <= INPUTREG;
128 SHIFTREG <= DATA_s;
108 shiftcnt <= 0;
129 shiftcnt <= 0;
109 END IF;
130 END IF;
131
132 END IF;
110 END IF;
133 END IF;
111 END PROCESS;
134 END PROCESS;
112
135
113 END ARCHITECTURE behav;
136 END ARCHITECTURE behav;
114
Show file before | Show file after | Hide comments
@@ -234,7 +234,7 BEGIN
234 apbi => apbi,
234 apbi => apbi,
235 apbo => apbo,
235 apbo => apbo,
236
236
237 run_ms => OPEN,--run_ms,
237 -- run_ms => OPEN,--run_ms,
238
238
239 ready_matrix_f0 => ready_matrix_f0,
239 ready_matrix_f0 => ready_matrix_f0,
240 ready_matrix_f1 => ready_matrix_f1,
240 ready_matrix_f1 => ready_matrix_f1,
Show file before | Show file after | Hide comments
@@ -40,10 +40,10 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
42 GENERIC (
42 GENERIC (
43 nb_data_by_buffer_size : INTEGER := 11;
43 nb_data_by_buffer_size : INTEGER := 32;
44 nb_snapshot_param_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 32;
45 delta_vector_size : INTEGER := 20;
45 delta_vector_size : INTEGER := 32;
46 delta_vector_size_f0_2 : INTEGER := 3;
46 delta_vector_size_f0_2 : INTEGER := 7;
47
47
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
@@ -62,7 +62,7 ENTITY lpp_lfr_apbreg IS
62
62
63 ---------------------------------------------------------------------------
63 ---------------------------------------------------------------------------
64 -- Spectral Matrix Reg
64 -- Spectral Matrix Reg
65 run_ms : OUT STD_LOGIC;
65 -- run_ms : OUT STD_LOGIC;
66 -- IN
66 -- IN
67 ready_matrix_f0 : IN STD_LOGIC;
67 ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
@@ -165,7 +165,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
165 TYPE lpp_SpectralMatrix_regs IS RECORD
165 TYPE lpp_SpectralMatrix_regs IS RECORD
166 config_active_interruption_onNewMatrix : STD_LOGIC;
166 config_active_interruption_onNewMatrix : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
168 -- config_ms_run : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
@@ -358,13 +358,22 BEGIN -- beh
358 END PROCESS;
358 END PROCESS;
359
359
360
360
361 reg_sp.length_matrix <= "00" & X"0000C8";
362 reg_sp.config_active_interruption_onError <= '0';
363 reg_wp.delta_f0 <= X"0001280A";
364 reg_wp.delta_f0_2 <= "0110000";
365 reg_wp.delta_f1 <= X"0001283F";
366 reg_wp.delta_f2 <= X"000127FF";
367 reg_wp.nb_data_by_buffer <= X"00000A7F";
368 reg_wp.nb_snapshot_param <= X"00000A80";
369 reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0
370
361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
371 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
362 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
372 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
363 BEGIN -- PROCESS lpp_dma_top
373 BEGIN -- PROCESS lpp_dma_top
364 IF HRESETn = '0' THEN -- asynchronous reset (active low)
374 IF HRESETn = '0' THEN -- asynchronous reset (active low)
365 reg_sp.config_active_interruption_onNewMatrix <= '0';
375 reg_sp.config_active_interruption_onNewMatrix <= '0';
366 reg_sp.config_active_interruption_onError <= '0';
376 -- reg_sp.config_ms_run <= '0';
367 reg_sp.config_ms_run <= '0';
368 reg_sp.status_ready_matrix_f0_0 <= '0';
377 reg_sp.status_ready_matrix_f0_0 <= '0';
369 reg_sp.status_ready_matrix_f1_0 <= '0';
378 reg_sp.status_ready_matrix_f1_0 <= '0';
370 reg_sp.status_ready_matrix_f2_0 <= '0';
379 reg_sp.status_ready_matrix_f2_0 <= '0';
@@ -382,7 +391,7 BEGIN -- beh
382 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
391 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
383 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
392 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
384
393
385 reg_sp.length_matrix <= (OTHERS => '0');
394 -- reg_sp.length_matrix <= (OTHERS => '0');
386
395
387 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
396 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
388 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
397 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
@@ -420,16 +429,16 BEGIN -- beh
420 reg_wp.status_new_err <= (OTHERS => '0');
429 reg_wp.status_new_err <= (OTHERS => '0');
421 reg_wp.error_buffer_full <= (OTHERS => '0');
430 reg_wp.error_buffer_full <= (OTHERS => '0');
422 reg_wp.delta_snapshot <= (OTHERS => '0');
431 reg_wp.delta_snapshot <= (OTHERS => '0');
423 reg_wp.delta_f0 <= (OTHERS => '0');
432 --reg_wp.delta_f0 <= (OTHERS => '0');
424 reg_wp.delta_f0_2 <= (OTHERS => '0');
433 --reg_wp.delta_f0_2 <= (OTHERS => '0');
425 reg_wp.delta_f1 <= (OTHERS => '0');
434 --reg_wp.delta_f1 <= (OTHERS => '0');
426 reg_wp.delta_f2 <= (OTHERS => '0');
435 --reg_wp.delta_f2 <= (OTHERS => '0');
427 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
436 --reg_wp.nb_data_by_buffer <= (OTHERS => '0');
428 reg_wp.nb_snapshot_param <= (OTHERS => '0');
437 --reg_wp.nb_snapshot_param <= (OTHERS => '0');
429 reg_wp.start_date <= (OTHERS => '1');
438 reg_wp.start_date <= (OTHERS => '1');
430
439
431 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
440 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
441 --reg_wp.length_buffer <= (OTHERS => '0');
433
442
434 pirq_temp <= (OTHERS => '0');
443 pirq_temp <= (OTHERS => '0');
435
444
@@ -473,8 +482,8 BEGIN -- beh
473
482
474 WHEN ADDR_LFR_SM_CONFIG =>
483 WHEN ADDR_LFR_SM_CONFIG =>
475 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
484 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
476 prdata(1) <= reg_sp.config_active_interruption_onError;
485 -- prdata(1) <= reg_sp.config_active_interruption_onError;
477 prdata(2) <= reg_sp.config_ms_run;
486 -- prdata(2) <= reg_sp.config_ms_run;
478
487
479 WHEN ADDR_LFR_SM_STATUS =>
488 WHEN ADDR_LFR_SM_STATUS =>
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
489 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
@@ -507,7 +516,7 BEGIN -- beh
507 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
516 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
508 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
517 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
509 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
518 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
510 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
519 -- WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
511 ---------------------------------------------------------------------
520 ---------------------------------------------------------------------
512 WHEN ADDR_LFR_WP_DATASHAPING =>
521 WHEN ADDR_LFR_WP_DATASHAPING =>
513 prdata(0) <= reg_wp.data_shaping_BW;
522 prdata(0) <= reg_wp.data_shaping_BW;
@@ -540,12 +549,12 BEGIN -- beh
540 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
549 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
541
550
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
551 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
552 -- WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
553 -- WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
554 -- WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
555 -- WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
547 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
556 -- WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
548 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
557 -- WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
549 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
558 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
550
559
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
560 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
@@ -568,7 +577,7 BEGIN -- beh
568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
577 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
578 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
570
579
571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
580 -- WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
572
581
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
582 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
583 prdata(31 DOWNTO 16) <= (OTHERS => '0');
@@ -587,8 +596,8 BEGIN -- beh
587 --
596 --
588 WHEN ADDR_LFR_SM_CONFIG =>
597 WHEN ADDR_LFR_SM_CONFIG =>
589 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
598 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
590 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
599 -- reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
591 reg_sp.config_ms_run <= apbi.pwdata(2);
600 -- reg_sp.config_ms_run <= apbi.pwdata(2);
592
601
593 WHEN ADDR_LFR_SM_STATUS =>
602 WHEN ADDR_LFR_SM_STATUS =>
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
603 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
@@ -608,7 +617,7 BEGIN -- beh
608 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
617 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
609 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
618 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
610
619
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
620 -- WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
612 ---------------------------------------------------------------------
621 ---------------------------------------------------------------------
613 WHEN ADDR_LFR_WP_DATASHAPING =>
622 WHEN ADDR_LFR_WP_DATASHAPING =>
614 reg_wp.data_shaping_BW <= apbi.pwdata(0);
623 reg_wp.data_shaping_BW <= apbi.pwdata(0);
@@ -643,15 +652,15 BEGIN -- beh
643 END LOOP all_reg_wp_status_bit;
652 END LOOP all_reg_wp_status_bit;
644
653
645 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
654 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
646 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
655 --WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
647 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
656 --WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
648 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
657 --WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
649 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
658 --WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
650 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
659 --WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
651 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
660 --WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
652 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
661 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
653
662
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
663 --WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
655
664
656 WHEN OTHERS => NULL;
665 WHEN OTHERS => NULL;
657 END CASE;
666 END CASE;
@@ -664,14 +673,15 BEGIN -- beh
664 ready_matrix_f1 OR
673 ready_matrix_f1 OR
665 ready_matrix_f2)
674 ready_matrix_f2)
666 )
675 )
667 OR
676 --OR
668 (reg_sp.config_active_interruption_onError AND (
677 --(reg_sp.config_active_interruption_onError AND
669 -- error_bad_component_error OR
678 -- (
670 error_buffer_full
679 -- error_buffer_full
671 OR error_input_fifo_write(0)
680 -- OR error_input_fifo_write(0)
672 OR error_input_fifo_write(1)
681 -- OR error_input_fifo_write(1)
673 OR error_input_fifo_write(2))
682 -- OR error_input_fifo_write(2))
674 ));
683 -- )
684 );
675 -- apbo.pirq(pirq_wfp)
685 -- apbo.pirq(pirq_wfp)
676 apbo_irq_wfp <= ored_irq_wfp;
686 apbo_irq_wfp <= ored_irq_wfp;
677
687
@@ -721,7 +731,7 BEGIN -- beh
721 irq_wfp_ZERO <= (OTHERS => '0');
731 irq_wfp_ZERO <= (OTHERS => '0');
722 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
732 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
723
733
724 run_ms <= reg_sp.config_ms_run;
734 -- run_ms <= reg_sp.config_ms_run;
725
735
726 -----------------------------------------------------------------------------
736 -----------------------------------------------------------------------------
727 --
737 --
Show file before | Show file after | Hide comments
@@ -282,7 +282,7 PACKAGE lpp_lfr_pkg IS
282 HRESETn : IN STD_ULOGIC;
282 HRESETn : IN STD_ULOGIC;
283 apbi : IN apb_slv_in_type;
283 apbi : IN apb_slv_in_type;
284 apbo : OUT apb_slv_out_type;
284 apbo : OUT apb_slv_out_type;
285 run_ms : OUT STD_LOGIC;
285 -- run_ms : OUT STD_LOGIC;
286 ready_matrix_f0 : IN STD_LOGIC;
286 ready_matrix_f0 : IN STD_LOGIC;
287 ready_matrix_f1 : IN STD_LOGIC;
287 ready_matrix_f1 : IN STD_LOGIC;
288 ready_matrix_f2 : IN STD_LOGIC;
288 ready_matrix_f2 : IN STD_LOGIC;
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