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Ajout du Demux a la VHD_Lib
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity DEMUX is
27 generic(
28 Data_sz : integer range 1 to 32 := 16);
29 port(
30 clk : in std_logic;
31 rstn : in std_logic;
32
33 Read : in std_logic_vector(4 downto 0);
34 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
35
36 EmptyF0a : in std_logic_vector(4 downto 0);
37 EmptyF0b : in std_logic_vector(4 downto 0);
38 EmptyF1 : in std_logic_vector(4 downto 0);
39 EmptyF2 : in std_logic_vector(4 downto 0);
40
41 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
45
46 Read_DEMUX : out std_logic_vector(19 downto 0);
47 Empty : out std_logic_vector(4 downto 0);
48 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
49 );
50 end entity;
51
52
53 architecture ar_DEMUX of DEMUX is
54
55 type etat is (eX,e0,e1,e2,e3);
56 signal ect : etat;
57
58 signal pong : std_logic;
59
60 signal DataCpt_reg : std_logic_vector(3 downto 0);
61 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
62
63 signal Countf0 : integer;
64 signal Countf1 : integer;
65
66 begin
67 process(clk,rstn)
68 begin
69 if(rstn='0')then
70 ect <= e0;
71 pong <= '0';
72 Countf0 <= 1;
73 Countf1 <= 0;
74
75 elsif(clk'event and clk='1')then
76 DataCpt_reg <= DataCpt;
77
78 case ect is
79
80 when e0 =>
81 if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then
82 pong <= not pong;
83 if(Countf0 = 5)then
84 Countf0 <= 0;
85 ect <= e2;
86 else
87 Countf0 <= Countf0 + 1;
88 ect <= e1;
89 end if;
90 end if;
91
92 when e1 =>
93 if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then
94 pong <= not pong;
95 if(Countf0 = 5)then
96 Countf0 <= 0;
97 ect <= e2;
98 else
99 Countf0 <= Countf0 + 1;
100 ect <= e0;
101 end if;
102 end if;
103
104 when e2 =>
105 if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then
106 if(Countf1 = 15)then
107 Countf1 <= 0;
108 ect <= e3;
109 else
110 Countf1 <= Countf1 + 1;
111 if(pong = '0')then
112 ect <= e0;
113 else
114 ect <= e1;
115 end if;
116 end if;
117 end if;
118
119 when e3 =>
120 if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then
121 if(pong = '0')then
122 ect <= e0;
123 else
124 ect <= e1;
125 end if;
126 end if;
127
128 when others =>
129 null;
130
131 end case;
132 end if;
133 end process;
134
135 with ect select
136 Empty <= EmptyF0a when e0,
137 EmptyF0b when e1,
138 EmptyF1 when e2,
139 EmptyF2 when e3,
140 (others => '1') when others;
141
142 with ect select
143 Data <= DataF0a when e0,
144 DataF0b when e1,
145 DataF1 when e2,
146 DataF2 when e3,
147 (others => '0') when others;
148
149 with ect select
150 Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0,
151 Dummy_Read & Dummy_Read & Read & Dummy_Read when e1,
152 Dummy_Read & Read & Dummy_Read & Dummy_Read when e2,
153 Read & Dummy_Read & Dummy_Read & Dummy_Read when e3,
154 (others => '1') when others;
155
156
157
158
159 end architecture;
160
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1 -- WatchFlag.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity WatchFlag is
7 port(
8 clk : in std_logic;
9 rstn : in std_logic;
10
11 FullF0a : in std_logic_vector(4 downto 0);
12 FullF0b : in std_logic_vector(4 downto 0);
13 FullF1 : in std_logic_vector(4 downto 0);
14 FullF2 : in std_logic_vector(4 downto 0);
15
16 EmptyF0a : in std_logic_vector(4 downto 0);
17 EmptyF0b : in std_logic_vector(4 downto 0);
18 EmptyF1 : in std_logic_vector(4 downto 0);
19 EmptyF2 : in std_logic_vector(4 downto 0);
20
21 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
22 );
23 end entity;
24
25
26 architecture ar_WatchFlag of WatchFlag is
27
28 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
29
30 begin
31 process(clk,rstn)
32 begin
33 if(rstn='0')then
34 DataCpt <= (others => '0');
35
36 elsif(clk'event and clk='1')then
37
38 if(FullF0a = FlagSet)then
39 DataCpt(0) <= '1';
40 elsif(EmptyF0a = FlagSet)then
41 DataCpt(0) <= '0';
42 end if;
43
44 if(FullF0b = FlagSet)then
45 DataCpt(1) <= '1';
46 elsif(EmptyF0b = FlagSet)then
47 DataCpt(1) <= '0';
48 end if;
49
50 if(FullF1 = FlagSet)then
51 DataCpt(2) <= '1';
52 elsif(EmptyF1 = FlagSet)then
53 DataCpt(2) <= '0';
54 end if;
55
56 if(FullF2 = FlagSet)then
57 DataCpt(3) <= '1';
58 elsif(EmptyF2 = FlagSet)then
59 DataCpt(3) <= '0';
60 end if;
61
62 end if;
63 end process;
64
65 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
32 package lpp_demux is
33
34 component DEMUX is
35 generic(
36 Data_sz : integer range 1 to 32 := 16);
37 port(
38 clk : in std_logic;
39 rstn : in std_logic;
40
41 Read : in std_logic_vector(4 downto 0);
42 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
61 component WatchFlag is
62 port(
63 clk : in std_logic;
64 rstn : in std_logic;
65
66 FullF0a : in std_logic_vector(4 downto 0);
67 FullF0b : in std_logic_vector(4 downto 0);
68 FullF1 : in std_logic_vector(4 downto 0);
69 FullF2 : in std_logic_vector(4 downto 0);
70
71 EmptyF0a : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
73 EmptyF1 : in std_logic_vector(4 downto 0);
74 EmptyF2 : in std_logic_vector(4 downto 0);
75
76 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
77 );
78 end component;
79
80
81 end; No newline at end of file
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