HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r495:0dee9fea5e79

correction du leon3_soc suite au merge avec la version incluant le memory_controler IAP

pellion -

r495:0dee9fea5e79 (MINI-LFR) WFP_MS-0-1-41 JC

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r495:0dee9fea5e79

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000128")  -- aa.bb.cc version
+                  top_lfr_version        => X"000129")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +10 -3

               SIGNAl mbe        : std_logic;        -- enable memory programming
               SIGNAL mbe_drive  : std_logic;       -- drive the MBE memory signal
               SIGNAL nSRAM_CE_s  : STD_LOGIC_VECTOR(1 downto 0);
+              SIGNAL nSRAM_OE_s    : STD_LOGIC;
               --IRQ
               SIGNAL irqi       : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL irqo       : irq_out_vector(0 TO CFG_NCPU-1);
                 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
                memi.bexcn  <= '1';
                memi.brdyn  <= '1';
+              nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
+              nSRAM_OE_s <= memo.ramoen(0);
             END GENERATE;
             IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
                        i   => mbe,
                        en  => mbe_drive,
                        o   => memi.bexcn );
+              nSRAM_CE_s <= (memo.ramsn(1 downto 0));
+              nSRAM_OE_s <= memo.oen;
             END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
-              nSRAM_CE_s <= (memo.ramsn(1 downto 0));
               rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
-              oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.oen);
+              oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
               nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

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