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Update regsiter to control the MatrixSpectral Module
pellion -
r320:0a6f2549f618 (MINI-LFR) WFP_MS-0-1-4 JC
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@@ -48,6 +48,25 USE lpp.CY7C1061DV33_pkg.ALL;
48 48 ENTITY testbench IS
49 49 END;
50 50
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51 70 ARCHITECTURE behav OF testbench IS
52 71 CONSTANT INDEX_LFR : INTEGER := 15;
53 72 CONSTANT ADDR_LFR : INTEGER := 15;
@@ -56,26 +75,42 ARCHITECTURE behav OF testbench IS
56 75 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
57 76 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
58 77 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
78
59 79 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
60 80 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
61 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
81 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
82 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C";
83
84 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
85 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
86 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
87 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
88
89 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
90 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
91 --X"00000F38";
92 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F";
93
62 94 -- REG WAVEFORM
63 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
64 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
65 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
66 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
67 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
68 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
69 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
70 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
71 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
72 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
73 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
74 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
75 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
76 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
77 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
78 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
95 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
96 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
97 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
98 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
99
100 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
101 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
102 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
103 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
104
105 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60";
106 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64";
107 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68";
108 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C";
109
110 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70";
111 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74";
112 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78";
113 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C";
79 114 -- RAM ADDRESS
80 115 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
81 116 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
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@@ -425,7 +425,7 BEGIN -- beh
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"000103") -- aa.bb.cc version
428 top_lfr_version => X"000104") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
@@ -577,4 +577,4 BEGIN -- beh
577 577 END IF;
578 578 END PROCESS;
579 579
580 END beh; No newline at end of file
580 END beh;
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@@ -288,6 +288,15 ARCHITECTURE beh OF lpp_lfr IS
288 288 SIGNAL data_ms_ren : STD_LOGIC;
289 289 SIGNAL data_ms_done : STD_LOGIC;
290 290
291 SIGNAL run_ms : STD_LOGIC;
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
299
291 300 BEGIN
292 301
293 302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -338,6 +347,9 BEGIN
338 347 HRESETn => rstn,
339 348 apbi => apbi,
340 349 apbo => apbo,
350
351 run_ms => run_ms,
352
341 353 ready_matrix_f0_0 => ready_matrix_f0_0,
342 354 ready_matrix_f0_1 => ready_matrix_f0_1,
343 355 ready_matrix_f1 => ready_matrix_f1,
@@ -353,6 +365,12 BEGIN
353 365 status_error_bad_component_error => status_error_bad_component_error,
354 366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
355 367 config_active_interruption_onError => config_active_interruption_onError,
368
369 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
373
356 374 addr_matrix_f0_0 => addr_matrix_f0_0,
357 375 addr_matrix_f0_1 => addr_matrix_f0_1,
358 376 addr_matrix_f1 => addr_matrix_f1,
@@ -492,44 +510,12 BEGIN
492 510 data_f3_data_out_ren => data_f3_data_out_ren ,
493 511
494 512 -------------------------------------------------------------------------
495 observation_reg => OPEN --observation_reg
496 ---- debug SNAPSHOT_OUT
497 --debug_f0_data => debug_f0_data,
498 --debug_f0_data_valid => debug_f0_data_valid ,
499 --debug_f1_data => debug_f1_data ,
500 --debug_f1_data_valid => debug_f1_data_valid,
501 --debug_f2_data => debug_f2_data ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
503 --debug_f3_data => debug_f3_data ,
504 --debug_f3_data_valid => debug_f3_data_valid,
505
506 ---- debug FIFO_IN
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
513 observation_reg => OPEN
515 514
516 515 );
517 516
518 517
519 518 -----------------------------------------------------------------------------
520 -- DEBUG -- WFP OUT
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
529 -----------------------------------------------------------------------------
530
531
532 -----------------------------------------------------------------------------
533 519 -- TEMP
534 520 -----------------------------------------------------------------------------
535 521
@@ -722,12 +708,16 BEGIN
722 708 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
723 709
724 710 -------------------------------------------------------------------------------
711
712 ms_softandhard_rstn <= rstn AND run_ms AND run;
713
714 -----------------------------------------------------------------------------
725 715 lpp_lfr_ms_1: lpp_lfr_ms
726 716 GENERIC MAP (
727 717 Mem_use => Mem_use )
728 718 PORT MAP (
729 719 clk => clk,
730 rstn => rstn,
720 rstn => ms_softandhard_rstn, --rstn,
731 721
732 722 coarse_time => coarse_time,
733 723 fine_time => fine_time,
@@ -764,6 +754,11 BEGIN
764 754 addr_matrix_f0_0 => addr_matrix_f0_0,
765 755 addr_matrix_f0_1 => addr_matrix_f0_1,
766 756 addr_matrix_f1 => addr_matrix_f1,
767 addr_matrix_f2 => addr_matrix_f2);
757 addr_matrix_f2 => addr_matrix_f2,
758
759 matrix_time_f0_0 => matrix_time_f0_0,
760 matrix_time_f0_1 => matrix_time_f0_1,
761 matrix_time_f1 => matrix_time_f1,
762 matrix_time_f2 => matrix_time_f2);
768 763
769 764 END beh;
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@@ -59,6 +59,7 ENTITY lpp_lfr_apbreg IS
59 59
60 60 ---------------------------------------------------------------------------
61 61 -- Spectral Matrix Reg
62 run_ms : OUT STD_LOGIC;
62 63 -- IN
63 64 ready_matrix_f0_0 : IN STD_LOGIC;
64 65 ready_matrix_f0_1 : IN STD_LOGIC;
@@ -78,10 +79,17 ENTITY lpp_lfr_apbreg IS
78 79
79 80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 81 config_active_interruption_onError : OUT STD_LOGIC;
82
81 83 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 84 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 85 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 86 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87
88 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92
85 93 ---------------------------------------------------------------------------
86 94 ---------------------------------------------------------------------------
87 95 -- WaveForm picker Reg
@@ -148,6 +156,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
148 156 TYPE lpp_SpectralMatrix_regs IS RECORD
149 157 config_active_interruption_onNewMatrix : STD_LOGIC;
150 158 config_active_interruption_onError : STD_LOGIC;
159 config_ms_run : STD_LOGIC;
151 160 status_ready_matrix_f0_0 : STD_LOGIC;
152 161 status_ready_matrix_f0_1 : STD_LOGIC;
153 162 status_ready_matrix_f1 : STD_LOGIC;
@@ -158,6 +167,16 ARCHITECTURE beh OF lpp_lfr_apbreg IS
158 167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 168 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 169 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170
171 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
176 fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
161 180 END RECORD;
162 181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
163 182
@@ -262,6 +281,7 BEGIN -- beh
262 281 IF HRESETn = '0' THEN -- asynchronous reset (active low)
263 282 reg_sp.config_active_interruption_onNewMatrix <= '0';
264 283 reg_sp.config_active_interruption_onError <= '0';
284 reg_sp.config_ms_run <= '1';
265 285 reg_sp.status_ready_matrix_f0_0 <= '0';
266 286 reg_sp.status_ready_matrix_f0_1 <= '0';
267 287 reg_sp.status_ready_matrix_f1 <= '0';
@@ -272,6 +292,16 BEGIN -- beh
272 292 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
273 293 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
274 294 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
295
296 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
300 reg_sp.fine_time_f0_0 <= (OTHERS => '0');
301 reg_sp.fine_time_f0_1 <= (OTHERS => '0');
302 reg_sp.fine_time_f1 <= (OTHERS => '0');
303 reg_sp.fine_time_f2 <= (OTHERS => '0');
304
275 305 prdata <= (OTHERS => '0');
276 306
277 307 apbo.pirq <= (OTHERS => '0');
@@ -308,6 +338,17 BEGIN -- beh
308 338 reg_wp.start_date <= (OTHERS => '0');
309 339
310 340 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
341
342 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
343 reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
346
347 reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
348 reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
349 reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
350 reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
351
311 352 status_full_ack <= (OTHERS => '0');
312 353
313 354 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
@@ -335,6 +376,7 BEGIN -- beh
335 376 --
336 377 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
337 378 prdata(1) <= reg_sp.config_active_interruption_onError;
379 prdata(2) <= reg_sp.config_ms_run;
338 380 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
339 381 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
340 382 prdata(2) <= reg_sp.status_ready_matrix_f1;
@@ -345,14 +387,24 BEGIN -- beh
345 387 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
346 388 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
347 389 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
348 WHEN "000110" => prdata <= debug_reg;
349 --
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
390
391 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
395 WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0;
396 WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1;
397 WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1;
398 WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2;
399
400 WHEN "001111" => prdata <= debug_reg;
401 ---------------------------------------------------------------------
402 WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;
351 403 prdata(1) <= reg_wp.data_shaping_SP0;
352 404 prdata(2) <= reg_wp.data_shaping_SP1;
353 405 prdata(3) <= reg_wp.data_shaping_R0;
354 406 prdata(4) <= reg_wp.data_shaping_R1;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
407 WHEN "010001" => prdata(0) <= reg_wp.enable_f0;
356 408 prdata(1) <= reg_wp.enable_f1;
357 409 prdata(2) <= reg_wp.enable_f2;
358 410 prdata(3) <= reg_wp.enable_f3;
@@ -360,22 +412,22 BEGIN -- beh
360 412 prdata(5) <= reg_wp.burst_f1;
361 413 prdata(6) <= reg_wp.burst_f2;
362 414 prdata(7) <= reg_wp.run;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
415 WHEN "010010" => prdata <= reg_wp.addr_data_f0;
416 WHEN "010011" => prdata <= reg_wp.addr_data_f1;
417 WHEN "010100" => prdata <= reg_wp.addr_data_f2;
418 WHEN "010101" => prdata <= reg_wp.addr_data_f3;
419 WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
368 420 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
369 421 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
422 WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
423 WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
424 WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
425 WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
426 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
427 WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
428 WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
429 WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
430 WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
379 431 ----------------------------------------------------
380 432 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 433 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
@@ -388,6 +440,7 BEGIN -- beh
388 440 ----------------------------------------------------
389 441 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
390 442 WHEN OTHERS => NULL;
443
391 444 END CASE;
392 445 IF (apbi.pwrite AND apbi.penable) = '1' THEN
393 446 -- APB DMA WRITE --
@@ -395,6 +448,7 BEGIN -- beh
395 448 --
396 449 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
397 450 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
451 reg_sp.config_ms_run <= apbi.pwdata(2);
398 452 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
399 453 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
400 454 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
@@ -406,12 +460,12 BEGIN -- beh
406 460 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
407 461 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
408 462 --
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
463 WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
410 464 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
411 465 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
412 466 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
413 467 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
468 WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);
415 469 reg_wp.enable_f1 <= apbi.pwdata(1);
416 470 reg_wp.enable_f2 <= apbi.pwdata(2);
417 471 reg_wp.enable_f3 <= apbi.pwdata(3);
@@ -419,26 +473,26 BEGIN -- beh
419 473 reg_wp.burst_f1 <= apbi.pwdata(5);
420 474 reg_wp.burst_f2 <= apbi.pwdata(6);
421 475 reg_wp.run <= apbi.pwdata(7);
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
476 WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;
477 WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;
478 WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;
479 WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;
480 WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
427 481 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
428 482 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
429 483 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
430 484 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
431 485 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
432 486 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
487 WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
488 WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
489 WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
490 WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
491 WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
492 WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
493 WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
494 WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
495 WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
442 496 --
443 497 WHEN OTHERS => NULL;
444 498 END CASE;
@@ -455,11 +509,6 BEGIN -- beh
455 509 error_bad_component_error)
456 510 ));
457 511
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
462 -- );
463 512 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
464 513
465 514 END IF;
@@ -490,4 +539,6 BEGIN -- beh
490 539 irq_wfp_ZERO <= (OTHERS => '0');
491 540 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
492 541
542 run_ms <= reg_sp.config_ms_run;
543
493 544 END beh;
Show file before | Show file after | Hide comments
@@ -82,7 +82,13 ENTITY lpp_lfr_ms IS
82 82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
91
86 92 );
87 93 END;
88 94
@@ -354,7 +360,13 BEGIN
354 360 addr_matrix_f0_0 => addr_matrix_f0_0,
355 361 addr_matrix_f0_1 => addr_matrix_f0_1,
356 362 addr_matrix_f1 => addr_matrix_f1,
357 addr_matrix_f2 => addr_matrix_f2);
363 addr_matrix_f2 => addr_matrix_f2,
364
365 matrix_time_f0_0 => matrix_time_f0_0,
366 matrix_time_f0_1 => matrix_time_f0_1,
367 matrix_time_f1 => matrix_time_f1,
368 matrix_time_f2 => matrix_time_f2
369 );
358 370
359 371
360 372
Show file before | Show file after | Hide comments
@@ -89,7 +89,12 ENTITY lpp_lfr_ms_fsmdma IS
89 89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
93 98
94 99 );
95 100 END;
@@ -228,10 +233,22 BEGIN
228 233 --
229 234 IF component_type = "0000" THEN
230 235 address <= address_matrix;
231 state <= WRITE_COARSE_TIME;
236 CASE matrix_type IS
237 WHEN "00" => matrix_time_f0_0 <= data_time;
238 WHEN "01" => matrix_time_f0_1 <= data_time;
239 WHEN "10" => matrix_time_f1 <= data_time;
240 WHEN "11" => matrix_time_f2 <= data_time ;
241 WHEN OTHERS => NULL;
242 END CASE;
243
232 244 header_data <= data_time(31 DOWNTO 0);
233 245 fine_time_reg <= data_time(47 DOWNTO 32);
234 header_send <= '1';
246 --state <= WRITE_COARSE_TIME;
247 --header_send <= '1';
248 state <= SEND_DATA;
249 header_send <= '0';
250 component_send <= '1';
251 header_select <= '0';
235 252 ELSE
236 253 state <= SEND_DATA;
237 254 END IF;
@@ -274,7 +291,6 BEGIN
274 291 debug_reg_s(2 DOWNTO 0) <= "011";
275 292
276 293 header_ack <= '0';
277 header_ack <= '0';
278 294
279 295 IF dma_ren = '0' THEN
280 296 header_send <= '0';
@@ -308,6 +324,7 BEGIN
308 324 END IF;
309 325
310 326 WHEN SEND_DATA =>
327 header_ack <= '0';
311 328 debug_reg_s(2 DOWNTO 0) <= "101";
312 329
313 330 IF fifo_empty = '1' THEN
@@ -341,6 +358,7 BEGIN
341 358 END IF;
342 359
343 360 WHEN CHECK_LENGTH =>
361 component_send <= '0';
344 362 debug_reg_s(2 DOWNTO 0) <= "111";
345 363 state <= IDLE;
346 364
Show file before | Show file after | Hide comments
@@ -57,7 +57,12 PACKAGE lpp_lfr_pkg IS
57 57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61
62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
61 66 END COMPONENT;
62 67
63 68 COMPONENT lpp_lfr_ms_fsmdma
@@ -95,7 +100,13 PACKAGE lpp_lfr_pkg IS
95 100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104
105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
109 );
99 110 END COMPONENT;
100 111
101 112
@@ -172,6 +183,7 PACKAGE lpp_lfr_pkg IS
172 183 HRESETn : IN STD_ULOGIC;
173 184 apbi : IN apb_slv_in_type;
174 185 apbo : OUT apb_slv_out_type;
186 run_ms : OUT STD_LOGIC;
175 187 ready_matrix_f0_0 : IN STD_LOGIC;
176 188 ready_matrix_f0_1 : IN STD_LOGIC;
177 189 ready_matrix_f1 : IN STD_LOGIC;
@@ -191,6 +203,12 PACKAGE lpp_lfr_pkg IS
191 203 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
192 204 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
193 205 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
206
207 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
208 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
209 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
210 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
211
194 212 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
195 213 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
196 214 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -257,7 +275,13 PACKAGE lpp_lfr_pkg IS
257 275 apbo : OUT apb_slv_out_type;
258 276 ahbi_ms : IN AHB_Mst_In_Type;
259 277 ahbo_ms : OUT AHB_Mst_Out_Type;
260 data_shaping_BW : OUT STD_LOGIC);
278 data_shaping_BW : OUT STD_LOGIC;
279 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
280 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
281 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
282 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
283
284 );
261 285 END COMPONENT;
262 286
263 287 END lpp_lfr_pkg;
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