@@ -48,6 +48,25 USE lpp.CY7C1061DV33_pkg.ALL; | |||||
48 | ENTITY testbench IS |
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48 | ENTITY testbench IS | |
49 | END; |
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49 | END; | |
50 |
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50 | |||
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51 | ||||
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52 | ||||
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53 | ||||
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54 | ||||
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55 | ||||
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56 | ||||
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57 | ||||
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58 | ||||
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59 | ||||
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60 | ||||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | ||||
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65 | ||||
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66 | ||||
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67 | ||||
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68 | ||||
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69 | ||||
51 | ARCHITECTURE behav OF testbench IS |
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70 | ARCHITECTURE behav OF testbench IS | |
52 | CONSTANT INDEX_LFR : INTEGER := 15; |
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71 | CONSTANT INDEX_LFR : INTEGER := 15; | |
53 | CONSTANT ADDR_LFR : INTEGER := 15; |
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72 | CONSTANT ADDR_LFR : INTEGER := 15; | |
@@ -56,26 +75,42 ARCHITECTURE behav OF testbench IS | |||||
56 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; |
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75 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |
57 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; |
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76 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |
58 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; |
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77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |
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78 | ||||
59 |
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79 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |
60 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; |
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80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |
61 |
CONSTANT ADDR_SPECTRAL_MATRIX_ |
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81 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |
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82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; | |||
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83 | ||||
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84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |||
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85 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |||
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86 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |||
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87 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |||
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88 | ||||
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89 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |||
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90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |||
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91 | --X"00000F38"; | |||
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92 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F"; | |||
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93 | ||||
62 | -- REG WAVEFORM |
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94 | -- REG WAVEFORM | |
63 |
CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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95 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
64 |
CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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96 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
65 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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97 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
66 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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98 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
67 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
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99 | ||
68 |
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100 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
69 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
70 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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102 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
71 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA |
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103 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
72 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
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104 | ||
73 |
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105 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; | |
74 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 |
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106 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; | |
75 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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107 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; | |
76 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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108 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; | |
77 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
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109 | ||
78 |
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110 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; | |
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111 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; | |||
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112 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; | |||
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113 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; | |||
79 | -- RAM ADDRESS |
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114 | -- RAM ADDRESS | |
80 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
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115 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; | |
81 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
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116 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
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425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
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426 | pirq_wfp => 14, | |
427 | hindex => 2, |
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427 | hindex => 2, | |
428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000104") -- aa.bb.cc version | |
429 | PORT MAP ( |
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429 | PORT MAP ( | |
430 | clk => clk_25, |
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430 | clk => clk_25, | |
431 | rstn => reset, |
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431 | rstn => reset, | |
@@ -577,4 +577,4 BEGIN -- beh | |||||
577 | END IF; |
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577 | END IF; | |
578 | END PROCESS; |
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578 | END PROCESS; | |
579 |
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579 | |||
580 | END beh; No newline at end of file |
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580 | END beh; |
@@ -288,6 +288,15 ARCHITECTURE beh OF lpp_lfr IS | |||||
288 | SIGNAL data_ms_ren : STD_LOGIC; |
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288 | SIGNAL data_ms_ren : STD_LOGIC; | |
289 | SIGNAL data_ms_done : STD_LOGIC; |
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289 | SIGNAL data_ms_done : STD_LOGIC; | |
290 |
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290 | |||
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291 | SIGNAL run_ms : STD_LOGIC; | |||
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292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |||
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293 | ||||
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294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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298 | ||||
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299 | ||||
291 | BEGIN |
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300 | BEGIN | |
292 |
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301 | |||
293 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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302 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
@@ -338,6 +347,9 BEGIN | |||||
338 | HRESETn => rstn, |
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347 | HRESETn => rstn, | |
339 | apbi => apbi, |
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348 | apbi => apbi, | |
340 | apbo => apbo, |
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349 | apbo => apbo, | |
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350 | ||||
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351 | run_ms => run_ms, | |||
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352 | ||||
341 | ready_matrix_f0_0 => ready_matrix_f0_0, |
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353 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
342 | ready_matrix_f0_1 => ready_matrix_f0_1, |
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354 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
343 | ready_matrix_f1 => ready_matrix_f1, |
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355 | ready_matrix_f1 => ready_matrix_f1, | |
@@ -353,6 +365,12 BEGIN | |||||
353 | status_error_bad_component_error => status_error_bad_component_error, |
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365 | status_error_bad_component_error => status_error_bad_component_error, | |
354 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
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366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
355 | config_active_interruption_onError => config_active_interruption_onError, |
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367 | config_active_interruption_onError => config_active_interruption_onError, | |
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368 | ||||
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369 | matrix_time_f0_0 => matrix_time_f0_0, | |||
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370 | matrix_time_f0_1 => matrix_time_f0_1, | |||
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371 | matrix_time_f1 => matrix_time_f1, | |||
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372 | matrix_time_f2 => matrix_time_f2, | |||
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373 | ||||
356 |
addr_matrix_f0_0 |
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374 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
357 |
addr_matrix_f0_1 |
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375 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
358 |
addr_matrix_f1 |
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376 | addr_matrix_f1 => addr_matrix_f1, | |
@@ -492,44 +510,12 BEGIN | |||||
492 | data_f3_data_out_ren => data_f3_data_out_ren , |
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510 | data_f3_data_out_ren => data_f3_data_out_ren , | |
493 |
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511 | |||
494 | ------------------------------------------------------------------------- |
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512 | ------------------------------------------------------------------------- | |
495 |
observation_reg => OPEN |
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513 | observation_reg => OPEN | |
496 | ---- debug SNAPSHOT_OUT |
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497 | --debug_f0_data => debug_f0_data, |
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498 | --debug_f0_data_valid => debug_f0_data_valid , |
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499 | --debug_f1_data => debug_f1_data , |
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500 | --debug_f1_data_valid => debug_f1_data_valid, |
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501 | --debug_f2_data => debug_f2_data , |
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502 | --debug_f2_data_valid => debug_f2_data_valid , |
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503 | --debug_f3_data => debug_f3_data , |
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504 | --debug_f3_data_valid => debug_f3_data_valid, |
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505 |
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506 | ---- debug FIFO_IN |
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507 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
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508 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
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509 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
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510 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
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511 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
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512 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
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513 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
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514 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
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515 |
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514 | ||
516 |
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515 | ); | |
517 |
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516 | |||
518 |
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517 | |||
519 | ----------------------------------------------------------------------------- |
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518 | ----------------------------------------------------------------------------- | |
520 | -- DEBUG -- WFP OUT |
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521 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
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522 | --debug_f0_data_fifo_out <= data_f0_data_out; |
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523 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
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524 | --debug_f1_data_fifo_out <= data_f1_data_out; |
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525 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
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526 | --debug_f2_data_fifo_out <= data_f2_data_out; |
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527 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
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528 | --debug_f3_data_fifo_out <= data_f3_data_out; |
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529 | ----------------------------------------------------------------------------- |
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530 |
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531 |
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532 | ----------------------------------------------------------------------------- |
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533 | -- TEMP |
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519 | -- TEMP | |
534 | ----------------------------------------------------------------------------- |
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520 | ----------------------------------------------------------------------------- | |
535 |
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521 | |||
@@ -722,12 +708,16 BEGIN | |||||
722 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
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708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
723 |
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709 | |||
724 | ------------------------------------------------------------------------------- |
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710 | ------------------------------------------------------------------------------- | |
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711 | ||||
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712 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |||
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713 | ||||
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714 | ----------------------------------------------------------------------------- | |||
725 | lpp_lfr_ms_1: lpp_lfr_ms |
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715 | lpp_lfr_ms_1 : lpp_lfr_ms | |
726 | GENERIC MAP ( |
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716 | GENERIC MAP ( | |
727 |
Mem_use => Mem_use |
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717 | Mem_use => Mem_use) | |
728 | PORT MAP ( |
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718 | PORT MAP ( | |
729 | clk => clk, |
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719 | clk => clk, | |
730 | rstn => rstn, |
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720 | rstn => ms_softandhard_rstn, --rstn, | |
731 |
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721 | |||
732 |
coarse_time |
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722 | coarse_time => coarse_time, | |
733 |
fine_time |
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723 | fine_time => fine_time, | |
@@ -764,6 +754,11 BEGIN | |||||
764 | addr_matrix_f0_0 => addr_matrix_f0_0, |
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754 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
765 | addr_matrix_f0_1 => addr_matrix_f0_1, |
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755 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
766 | addr_matrix_f1 => addr_matrix_f1, |
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756 | addr_matrix_f1 => addr_matrix_f1, | |
767 |
addr_matrix_f2 => addr_matrix_f2 |
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757 | addr_matrix_f2 => addr_matrix_f2, | |
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758 | ||||
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759 | matrix_time_f0_0 => matrix_time_f0_0, | |||
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760 | matrix_time_f0_1 => matrix_time_f0_1, | |||
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761 | matrix_time_f1 => matrix_time_f1, | |||
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762 | matrix_time_f2 => matrix_time_f2); | |||
768 |
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763 | |||
769 | END beh; |
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764 | END beh; |
@@ -59,6 +59,7 ENTITY lpp_lfr_apbreg IS | |||||
59 |
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59 | |||
60 | --------------------------------------------------------------------------- |
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60 | --------------------------------------------------------------------------- | |
61 | -- Spectral Matrix Reg |
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61 | -- Spectral Matrix Reg | |
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62 | run_ms : OUT STD_LOGIC; | |||
62 | -- IN |
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63 | -- IN | |
63 | ready_matrix_f0_0 : IN STD_LOGIC; |
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64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
64 | ready_matrix_f0_1 : IN STD_LOGIC; |
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65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
@@ -78,10 +79,17 ENTITY lpp_lfr_apbreg IS | |||||
78 |
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79 | |||
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
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80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
80 | config_active_interruption_onError : OUT STD_LOGIC; |
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81 | config_active_interruption_onError : OUT STD_LOGIC; | |
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82 | ||||
81 |
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83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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87 | ||||
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88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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92 | ||||
85 |
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93 | --------------------------------------------------------------------------- | |
86 | --------------------------------------------------------------------------- |
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94 | --------------------------------------------------------------------------- | |
87 | -- WaveForm picker Reg |
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95 | -- WaveForm picker Reg | |
@@ -148,6 +156,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
148 | TYPE lpp_SpectralMatrix_regs IS RECORD |
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156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
149 | config_active_interruption_onNewMatrix : STD_LOGIC; |
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157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
150 | config_active_interruption_onError : STD_LOGIC; |
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158 | config_active_interruption_onError : STD_LOGIC; | |
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159 | config_ms_run : STD_LOGIC; | |||
151 | status_ready_matrix_f0_0 : STD_LOGIC; |
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160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
152 | status_ready_matrix_f0_1 : STD_LOGIC; |
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161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
153 | status_ready_matrix_f1 : STD_LOGIC; |
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162 | status_ready_matrix_f1 : STD_LOGIC; | |
@@ -158,6 +167,16 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
158 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
159 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
160 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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170 | ||||
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171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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175 | ||||
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176 | fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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177 | fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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178 | fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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179 | fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
161 | END RECORD; |
|
180 | END RECORD; | |
162 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
163 |
|
182 | |||
@@ -262,6 +281,7 BEGIN -- beh | |||||
262 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
263 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
264 | reg_sp.config_active_interruption_onError <= '0'; |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
|
284 | reg_sp.config_ms_run <= '1'; | |||
265 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
266 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
267 | reg_sp.status_ready_matrix_f1 <= '0'; |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
@@ -272,6 +292,16 BEGIN -- beh | |||||
272 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
273 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
274 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
295 | ||||
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |||
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |||
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |||
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |||
|
300 | reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |||
|
301 | reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |||
|
302 | reg_sp.fine_time_f1 <= (OTHERS => '0'); | |||
|
303 | reg_sp.fine_time_f2 <= (OTHERS => '0'); | |||
|
304 | ||||
275 |
|
|
305 | prdata <= (OTHERS => '0'); | |
276 |
|
306 | |||
277 | apbo.pirq <= (OTHERS => '0'); |
|
307 | apbo.pirq <= (OTHERS => '0'); | |
@@ -308,6 +338,17 BEGIN -- beh | |||||
308 | reg_wp.start_date <= (OTHERS => '0'); |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
309 |
|
339 | |||
310 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |||
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |||
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |||
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |||
|
346 | ||||
|
347 | reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |||
|
348 | reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |||
|
349 | reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |||
|
350 | reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |||
|
351 | ||||
311 |
|
|
352 | status_full_ack <= (OTHERS => '0'); | |
312 |
|
353 | |||
313 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
@@ -335,6 +376,7 BEGIN -- beh | |||||
335 | -- |
|
376 | -- | |
336 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
337 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |||
338 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
339 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
340 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
@@ -345,14 +387,24 BEGIN -- beh | |||||
345 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
346 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
347 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
348 | WHEN "000110" => prdata <= debug_reg; |
|
390 | ||
349 | -- |
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
350 |
WHEN "00 |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |||
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |||
|
395 | WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0; | |||
|
396 | WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1; | |||
|
397 | WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1; | |||
|
398 | WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2; | |||
|
399 | ||||
|
400 | WHEN "001111" => prdata <= debug_reg; | |||
|
401 | --------------------------------------------------------------------- | |||
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |||
351 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
352 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
353 | prdata(3) <= reg_wp.data_shaping_R0; |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
354 | prdata(4) <= reg_wp.data_shaping_R1; |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
355 |
WHEN "0 |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
356 | prdata(1) <= reg_wp.enable_f1; |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
357 | prdata(2) <= reg_wp.enable_f2; |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
358 | prdata(3) <= reg_wp.enable_f3; |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
@@ -360,22 +412,22 BEGIN -- beh | |||||
360 | prdata(5) <= reg_wp.burst_f1; |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
361 | prdata(6) <= reg_wp.burst_f2; |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
362 | prdata(7) <= reg_wp.run; |
|
414 | prdata(7) <= reg_wp.run; | |
363 |
WHEN "0 |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
364 |
WHEN "0 |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
365 |
WHEN "0 |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
366 |
WHEN "0 |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
367 |
WHEN "0 |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
368 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
369 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
370 |
WHEN "0 |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
371 |
WHEN "01 |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
372 |
WHEN "01 |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
373 |
WHEN "01 |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
374 |
WHEN "01 |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
375 |
WHEN "01 |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
376 |
WHEN "01 |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
377 |
WHEN "01 |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
378 |
WHEN "01 |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
379 | ---------------------------------------------------- |
|
431 | ---------------------------------------------------- | |
380 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
381 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
@@ -388,6 +440,7 BEGIN -- beh | |||||
388 | ---------------------------------------------------- |
|
440 | ---------------------------------------------------- | |
389 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
390 | WHEN OTHERS => NULL; |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||||
391 |
|
|
444 | END CASE; | |
392 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
393 | -- APB DMA WRITE -- |
|
446 | -- APB DMA WRITE -- | |
@@ -395,6 +448,7 BEGIN -- beh | |||||
395 | -- |
|
448 | -- | |
396 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
397 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |||
398 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
399 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
400 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
@@ -406,12 +460,12 BEGIN -- beh | |||||
406 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
407 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
408 | -- |
|
462 | -- | |
409 |
WHEN "0 |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
410 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
411 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
412 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
413 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
414 |
WHEN "0 |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
415 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
416 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
417 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
@@ -419,26 +473,26 BEGIN -- beh | |||||
419 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
420 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
421 | reg_wp.run <= apbi.pwdata(7); |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
422 |
WHEN "0 |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
423 |
WHEN "0 |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
424 |
WHEN "0 |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
425 |
WHEN "0 |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
426 |
WHEN "0 |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
427 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
428 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
429 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
430 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
431 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
432 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
433 |
WHEN "0 |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
434 |
WHEN "01 |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
435 |
WHEN "01 |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
436 |
WHEN "01 |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
437 |
WHEN "01 |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
438 |
WHEN "01 |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
439 |
WHEN "01 |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
440 |
WHEN "01 |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
441 |
WHEN "01 |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
442 | -- |
|
496 | -- | |
443 | WHEN OTHERS => NULL; |
|
497 | WHEN OTHERS => NULL; | |
444 | END CASE; |
|
498 | END CASE; | |
@@ -455,11 +509,6 BEGIN -- beh | |||||
455 | error_bad_component_error) |
|
509 | error_bad_component_error) | |
456 | )); |
|
510 | )); | |
457 |
|
511 | |||
458 | --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR |
|
|||
459 | -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR |
|
|||
460 | -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR |
|
|||
461 | -- status_full(3) OR status_full_err(3) OR status_new_err(3) |
|
|||
462 | -- ); |
|
|||
463 |
|
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
464 |
|
513 | |||
465 | END IF; |
|
514 | END IF; | |
@@ -490,4 +539,6 BEGIN -- beh | |||||
490 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
491 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
492 |
|
541 | |||
|
542 | run_ms <= reg_sp.config_ms_run; | |||
|
543 | ||||
493 | END beh; |
|
544 | END beh; |
@@ -82,7 +82,13 ENTITY lpp_lfr_ms IS | |||||
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
91 | ||||
86 | ); |
|
92 | ); | |
87 | END; |
|
93 | END; | |
88 |
|
94 | |||
@@ -354,7 +360,13 BEGIN | |||||
354 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
360 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
355 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
361 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
356 | addr_matrix_f1 => addr_matrix_f1, |
|
362 | addr_matrix_f1 => addr_matrix_f1, | |
357 |
addr_matrix_f2 => addr_matrix_f2 |
|
363 | addr_matrix_f2 => addr_matrix_f2, | |
|
364 | ||||
|
365 | matrix_time_f0_0 => matrix_time_f0_0, | |||
|
366 | matrix_time_f0_1 => matrix_time_f0_1, | |||
|
367 | matrix_time_f1 => matrix_time_f1, | |||
|
368 | matrix_time_f2 => matrix_time_f2 | |||
|
369 | ); | |||
358 |
|
370 | |||
359 |
|
371 | |||
360 |
|
372 |
@@ -89,7 +89,12 ENTITY lpp_lfr_ms_fsmdma IS | |||||
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
93 | ||||
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
93 |
|
98 | |||
94 | ); |
|
99 | ); | |
95 | END; |
|
100 | END; | |
@@ -228,10 +233,22 BEGIN | |||||
228 | -- |
|
233 | -- | |
229 | IF component_type = "0000" THEN |
|
234 | IF component_type = "0000" THEN | |
230 | address <= address_matrix; |
|
235 | address <= address_matrix; | |
231 | state <= WRITE_COARSE_TIME; |
|
236 | CASE matrix_type IS | |
|
237 | WHEN "00" => matrix_time_f0_0 <= data_time; | |||
|
238 | WHEN "01" => matrix_time_f0_1 <= data_time; | |||
|
239 | WHEN "10" => matrix_time_f1 <= data_time; | |||
|
240 | WHEN "11" => matrix_time_f2 <= data_time ; | |||
|
241 | WHEN OTHERS => NULL; | |||
|
242 | END CASE; | |||
|
243 | ||||
232 |
|
|
244 | header_data <= data_time(31 DOWNTO 0); | |
233 | fine_time_reg <= data_time(47 DOWNTO 32); |
|
245 | fine_time_reg <= data_time(47 DOWNTO 32); | |
234 | header_send <= '1'; |
|
246 | --state <= WRITE_COARSE_TIME; | |
|
247 | --header_send <= '1'; | |||
|
248 | state <= SEND_DATA; | |||
|
249 | header_send <= '0'; | |||
|
250 | component_send <= '1'; | |||
|
251 | header_select <= '0'; | |||
235 | ELSE |
|
252 | ELSE | |
236 | state <= SEND_DATA; |
|
253 | state <= SEND_DATA; | |
237 | END IF; |
|
254 | END IF; | |
@@ -274,7 +291,6 BEGIN | |||||
274 | debug_reg_s(2 DOWNTO 0) <= "011"; |
|
291 | debug_reg_s(2 DOWNTO 0) <= "011"; | |
275 |
|
292 | |||
276 | header_ack <= '0'; |
|
293 | header_ack <= '0'; | |
277 | header_ack <= '0'; |
|
|||
278 |
|
294 | |||
279 | IF dma_ren = '0' THEN |
|
295 | IF dma_ren = '0' THEN | |
280 | header_send <= '0'; |
|
296 | header_send <= '0'; | |
@@ -308,6 +324,7 BEGIN | |||||
308 | END IF; |
|
324 | END IF; | |
309 |
|
325 | |||
310 | WHEN SEND_DATA => |
|
326 | WHEN SEND_DATA => | |
|
327 | header_ack <= '0'; | |||
311 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
328 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
312 |
|
329 | |||
313 | IF fifo_empty = '1' THEN |
|
330 | IF fifo_empty = '1' THEN | |
@@ -341,6 +358,7 BEGIN | |||||
341 | END IF; |
|
358 | END IF; | |
342 |
|
359 | |||
343 | WHEN CHECK_LENGTH => |
|
360 | WHEN CHECK_LENGTH => | |
|
361 | component_send <= '0'; | |||
344 | debug_reg_s(2 DOWNTO 0) <= "111"; |
|
362 | debug_reg_s(2 DOWNTO 0) <= "111"; | |
345 | state <= IDLE; |
|
363 | state <= IDLE; | |
346 |
|
364 |
@@ -57,7 +57,12 PACKAGE lpp_lfr_pkg IS | |||||
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
61 | ||||
|
62 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
64 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
65 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |||
61 | END COMPONENT; |
|
66 | END COMPONENT; | |
62 |
|
67 | |||
63 | COMPONENT lpp_lfr_ms_fsmdma |
|
68 | COMPONENT lpp_lfr_ms_fsmdma | |
@@ -95,7 +100,13 PACKAGE lpp_lfr_pkg IS | |||||
95 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
96 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
97 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
104 | ||||
|
105 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
107 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
108 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
109 | ); | |||
99 | END COMPONENT; |
|
110 | END COMPONENT; | |
100 |
|
111 | |||
101 |
|
112 | |||
@@ -172,6 +183,7 PACKAGE lpp_lfr_pkg IS | |||||
172 | HRESETn : IN STD_ULOGIC; |
|
183 | HRESETn : IN STD_ULOGIC; | |
173 | apbi : IN apb_slv_in_type; |
|
184 | apbi : IN apb_slv_in_type; | |
174 | apbo : OUT apb_slv_out_type; |
|
185 | apbo : OUT apb_slv_out_type; | |
|
186 | run_ms : OUT STD_LOGIC; | |||
175 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
187 | ready_matrix_f0_0 : IN STD_LOGIC; | |
176 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
188 | ready_matrix_f0_1 : IN STD_LOGIC; | |
177 | ready_matrix_f1 : IN STD_LOGIC; |
|
189 | ready_matrix_f1 : IN STD_LOGIC; | |
@@ -191,6 +203,12 PACKAGE lpp_lfr_pkg IS | |||||
191 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
205 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
206 | ||||
|
207 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
208 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
209 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
210 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
211 | ||||
194 |
|
|
212 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
195 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
213 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
196 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
214 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
@@ -257,7 +275,13 PACKAGE lpp_lfr_pkg IS | |||||
257 | apbo : OUT apb_slv_out_type; |
|
275 | apbo : OUT apb_slv_out_type; | |
258 | ahbi_ms : IN AHB_Mst_In_Type; |
|
276 | ahbi_ms : IN AHB_Mst_In_Type; | |
259 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
277 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
260 |
data_shaping_BW : OUT STD_LOGIC |
|
278 | data_shaping_BW : OUT STD_LOGIC; | |
|
279 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
280 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
281 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
282 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
283 | ||||
|
284 | ); | |||
261 | END COMPONENT; |
|
285 | END COMPONENT; | |
262 |
|
286 | |||
263 | END lpp_lfr_pkg; |
|
287 | END lpp_lfr_pkg; |
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