@@ -48,6 +48,25 USE lpp.CY7C1061DV33_pkg.ALL; | |||||
48 | ENTITY testbench IS |
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48 | ENTITY testbench IS | |
49 | END; |
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49 | END; | |
50 |
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50 | |||
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51 | ||||
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52 | ||||
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53 | ||||
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54 | ||||
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55 | ||||
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56 | ||||
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57 | ||||
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58 | ||||
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59 | ||||
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60 | ||||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | ||||
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65 | ||||
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66 | ||||
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67 | ||||
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68 | ||||
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69 | ||||
51 | ARCHITECTURE behav OF testbench IS |
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70 | ARCHITECTURE behav OF testbench IS | |
52 | CONSTANT INDEX_LFR : INTEGER := 15; |
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71 | CONSTANT INDEX_LFR : INTEGER := 15; | |
53 | CONSTANT ADDR_LFR : INTEGER := 15; |
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72 | CONSTANT ADDR_LFR : INTEGER := 15; | |
@@ -56,26 +75,42 ARCHITECTURE behav OF testbench IS | |||||
56 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; |
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75 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |
57 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; |
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76 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |
58 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; |
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77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |
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78 | ||||
59 |
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79 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |
60 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; |
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80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |
61 |
CONSTANT ADDR_SPECTRAL_MATRIX_ |
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81 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |
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82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; | |||
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83 | ||||
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84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |||
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85 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |||
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86 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |||
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87 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |||
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88 | ||||
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89 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |||
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90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |||
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91 | --X"00000F38"; | |||
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92 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F"; | |||
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93 | ||||
62 | -- REG WAVEFORM |
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94 | -- REG WAVEFORM | |
63 |
CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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95 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
64 |
CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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96 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
65 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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97 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
66 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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98 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
67 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
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99 | ||
68 |
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100 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
69 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
70 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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102 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
71 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA |
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103 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
72 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
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104 | ||
73 |
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105 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; | |
74 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 |
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106 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; | |
75 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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107 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; | |
76 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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108 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; | |
77 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
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109 | ||
78 |
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110 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; | |
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111 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; | |||
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112 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; | |||
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113 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; | |||
79 | -- RAM ADDRESS |
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114 | -- RAM ADDRESS | |
80 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
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115 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; | |
81 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
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116 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
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425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
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426 | pirq_wfp => 14, | |
427 | hindex => 2, |
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427 | hindex => 2, | |
428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000104") -- aa.bb.cc version | |
429 | PORT MAP ( |
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429 | PORT MAP ( | |
430 | clk => clk_25, |
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430 | clk => clk_25, | |
431 | rstn => reset, |
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431 | rstn => reset, | |
@@ -577,4 +577,4 BEGIN -- beh | |||||
577 | END IF; |
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577 | END IF; | |
578 | END PROCESS; |
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578 | END PROCESS; | |
579 |
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579 | |||
580 | END beh; No newline at end of file |
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580 | END beh; |
@@ -62,7 +62,7 ENTITY lpp_lfr IS | |||||
62 | data_shaping_BW : OUT STD_LOGIC; |
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62 | data_shaping_BW : OUT STD_LOGIC; | |
63 | -- |
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63 | -- | |
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
65 |
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65 | |||
66 | --debug |
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66 | --debug | |
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | --debug_f0_data_valid : OUT STD_LOGIC; |
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68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
@@ -233,9 +233,9 ARCHITECTURE beh OF lpp_lfr IS | |||||
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
236 |
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236 | |||
237 |
SIGNAL dma_rr_grant |
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237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
238 |
SIGNAL dma_sel |
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238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
239 |
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239 | |||
240 | ----------------------------------------------------------------------------- |
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240 | ----------------------------------------------------------------------------- | |
241 | -- DMA_REG |
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241 | -- DMA_REG | |
@@ -280,13 +280,22 ARCHITECTURE beh OF lpp_lfr IS | |||||
280 | ----------------------------------------------------------------------------- |
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280 | ----------------------------------------------------------------------------- | |
281 | -- MS |
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281 | -- MS | |
282 | ----------------------------------------------------------------------------- |
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282 | ----------------------------------------------------------------------------- | |
283 |
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283 | |||
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | SIGNAL data_ms_valid : STD_LOGIC; |
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286 | SIGNAL data_ms_valid : STD_LOGIC; | |
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
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287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
288 | SIGNAL data_ms_ren : STD_LOGIC; |
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288 | SIGNAL data_ms_ren : STD_LOGIC; | |
289 | SIGNAL data_ms_done : STD_LOGIC; |
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289 | SIGNAL data_ms_done : STD_LOGIC; | |
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290 | ||||
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291 | SIGNAL run_ms : STD_LOGIC; | |||
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292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |||
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293 | ||||
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294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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298 | ||||
290 |
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299 | ||
291 | BEGIN |
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300 | BEGIN | |
292 |
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301 | |||
@@ -334,10 +343,13 BEGIN | |||||
334 | pirq_wfp => pirq_wfp, |
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343 | pirq_wfp => pirq_wfp, | |
335 | top_lfr_version => top_lfr_version) |
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344 | top_lfr_version => top_lfr_version) | |
336 | PORT MAP ( |
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345 | PORT MAP ( | |
337 | HCLK => clk, |
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346 | HCLK => clk, | |
338 | HRESETn => rstn, |
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347 | HRESETn => rstn, | |
339 | apbi => apbi, |
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348 | apbi => apbi, | |
340 | apbo => apbo, |
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349 | apbo => apbo, | |
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350 | ||||
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351 | run_ms => run_ms, | |||
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352 | ||||
341 | ready_matrix_f0_0 => ready_matrix_f0_0, |
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353 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
342 | ready_matrix_f0_1 => ready_matrix_f0_1, |
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354 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
343 | ready_matrix_f1 => ready_matrix_f1, |
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355 | ready_matrix_f1 => ready_matrix_f1, | |
@@ -353,49 +365,55 BEGIN | |||||
353 | status_error_bad_component_error => status_error_bad_component_error, |
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365 | status_error_bad_component_error => status_error_bad_component_error, | |
354 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
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366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
355 | config_active_interruption_onError => config_active_interruption_onError, |
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367 | config_active_interruption_onError => config_active_interruption_onError, | |
356 | addr_matrix_f0_0 => addr_matrix_f0_0, |
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368 | ||
357 | addr_matrix_f0_1 => addr_matrix_f0_1, |
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369 | matrix_time_f0_0 => matrix_time_f0_0, | |
358 | addr_matrix_f1 => addr_matrix_f1, |
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370 | matrix_time_f0_1 => matrix_time_f0_1, | |
359 | addr_matrix_f2 => addr_matrix_f2, |
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371 | matrix_time_f1 => matrix_time_f1, | |
360 | status_full => status_full, |
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372 | matrix_time_f2 => matrix_time_f2, | |
361 | status_full_ack => status_full_ack, |
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373 | ||
362 | status_full_err => status_full_err, |
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374 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
363 | status_new_err => status_new_err, |
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375 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
364 | data_shaping_BW => data_shaping_BW, |
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376 | addr_matrix_f1 => addr_matrix_f1, | |
365 | data_shaping_SP0 => data_shaping_SP0, |
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377 | addr_matrix_f2 => addr_matrix_f2, | |
366 | data_shaping_SP1 => data_shaping_SP1, |
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378 | status_full => status_full, | |
367 | data_shaping_R0 => data_shaping_R0, |
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379 | status_full_ack => status_full_ack, | |
368 | data_shaping_R1 => data_shaping_R1, |
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380 | status_full_err => status_full_err, | |
369 | delta_snapshot => delta_snapshot, |
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381 | status_new_err => status_new_err, | |
370 | delta_f0 => delta_f0, |
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382 | data_shaping_BW => data_shaping_BW, | |
371 | delta_f0_2 => delta_f0_2, |
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383 | data_shaping_SP0 => data_shaping_SP0, | |
372 | delta_f1 => delta_f1, |
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384 | data_shaping_SP1 => data_shaping_SP1, | |
373 | delta_f2 => delta_f2, |
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385 | data_shaping_R0 => data_shaping_R0, | |
374 | nb_data_by_buffer => nb_data_by_buffer, |
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386 | data_shaping_R1 => data_shaping_R1, | |
375 | nb_word_by_buffer => nb_word_by_buffer, |
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387 | delta_snapshot => delta_snapshot, | |
376 | nb_snapshot_param => nb_snapshot_param, |
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388 | delta_f0 => delta_f0, | |
377 | enable_f0 => enable_f0, |
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389 | delta_f0_2 => delta_f0_2, | |
378 |
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390 | delta_f1 => delta_f1, | |
379 |
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391 | delta_f2 => delta_f2, | |
380 | enable_f3 => enable_f3, |
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392 | nb_data_by_buffer => nb_data_by_buffer, | |
381 | burst_f0 => burst_f0, |
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393 | nb_word_by_buffer => nb_word_by_buffer, | |
382 | burst_f1 => burst_f1, |
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394 | nb_snapshot_param => nb_snapshot_param, | |
383 | burst_f2 => burst_f2, |
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395 | enable_f0 => enable_f0, | |
384 | run => run, |
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396 | enable_f1 => enable_f1, | |
385 | addr_data_f0 => addr_data_f0, |
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397 | enable_f2 => enable_f2, | |
386 | addr_data_f1 => addr_data_f1, |
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398 | enable_f3 => enable_f3, | |
387 | addr_data_f2 => addr_data_f2, |
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399 | burst_f0 => burst_f0, | |
388 | addr_data_f3 => addr_data_f3, |
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400 | burst_f1 => burst_f1, | |
389 | start_date => start_date, |
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401 | burst_f2 => burst_f2, | |
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402 | run => run, | |||
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403 | addr_data_f0 => addr_data_f0, | |||
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404 | addr_data_f1 => addr_data_f1, | |||
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405 | addr_data_f2 => addr_data_f2, | |||
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406 | addr_data_f3 => addr_data_f3, | |||
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407 | start_date => start_date, | |||
390 | --------------------------------------------------------------------------- |
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408 | --------------------------------------------------------------------------- | |
391 |
debug_reg0 |
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409 | debug_reg0 => debug_reg0, | |
392 |
debug_reg1 |
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410 | debug_reg1 => debug_reg1, | |
393 |
debug_reg2 |
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411 | debug_reg2 => debug_reg2, | |
394 |
debug_reg3 |
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412 | debug_reg3 => debug_reg3, | |
395 |
debug_reg4 |
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413 | debug_reg4 => debug_reg4, | |
396 |
debug_reg5 |
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414 | debug_reg5 => debug_reg5, | |
397 |
debug_reg6 |
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415 | debug_reg6 => debug_reg6, | |
398 |
debug_reg7 |
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416 | debug_reg7 => debug_reg7); | |
399 |
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417 | |||
400 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
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418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
401 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
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419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
@@ -492,44 +510,12 BEGIN | |||||
492 | data_f3_data_out_ren => data_f3_data_out_ren , |
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510 | data_f3_data_out_ren => data_f3_data_out_ren , | |
493 |
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511 | |||
494 | ------------------------------------------------------------------------- |
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512 | ------------------------------------------------------------------------- | |
495 |
observation_reg => OPEN |
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513 | observation_reg => OPEN | |
496 | ---- debug SNAPSHOT_OUT |
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497 | --debug_f0_data => debug_f0_data, |
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498 | --debug_f0_data_valid => debug_f0_data_valid , |
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499 | --debug_f1_data => debug_f1_data , |
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500 | --debug_f1_data_valid => debug_f1_data_valid, |
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501 | --debug_f2_data => debug_f2_data , |
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502 | --debug_f2_data_valid => debug_f2_data_valid , |
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503 | --debug_f3_data => debug_f3_data , |
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504 | --debug_f3_data_valid => debug_f3_data_valid, |
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505 |
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506 | ---- debug FIFO_IN |
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507 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
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508 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
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509 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
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510 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
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511 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
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512 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
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513 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
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514 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
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515 |
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514 | ||
516 |
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515 | ); | |
517 |
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516 | |||
518 |
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517 | |||
519 | ----------------------------------------------------------------------------- |
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518 | ----------------------------------------------------------------------------- | |
520 | -- DEBUG -- WFP OUT |
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521 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
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522 | --debug_f0_data_fifo_out <= data_f0_data_out; |
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523 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
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524 | --debug_f1_data_fifo_out <= data_f1_data_out; |
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525 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
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526 | --debug_f2_data_fifo_out <= data_f2_data_out; |
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527 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
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|||
528 | --debug_f3_data_fifo_out <= data_f3_data_out; |
|
|||
529 | ----------------------------------------------------------------------------- |
|
|||
530 |
|
||||
531 |
|
||||
532 | ----------------------------------------------------------------------------- |
|
|||
533 | -- TEMP |
|
519 | -- TEMP | |
534 | ----------------------------------------------------------------------------- |
|
520 | ----------------------------------------------------------------------------- | |
535 |
|
521 | |||
@@ -581,7 +567,7 BEGIN | |||||
581 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
582 | dma_rr_valid_ms(2) <= '0'; |
|
568 | dma_rr_valid_ms(2) <= '0'; | |
583 | dma_rr_valid_ms(3) <= '0'; |
|
569 | dma_rr_valid_ms(3) <= '0'; | |
584 |
|
570 | |||
585 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
571 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
586 | PORT MAP ( |
|
572 | PORT MAP ( | |
587 | clk => clk, |
|
573 | clk => clk, | |
@@ -590,7 +576,7 BEGIN | |||||
590 | out_grant => dma_rr_grant_ms); |
|
576 | out_grant => dma_rr_grant_ms); | |
591 |
|
577 | |||
592 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
593 |
|
579 | |||
594 |
|
580 | |||
595 | ----------------------------------------------------------------------------- |
|
581 | ----------------------------------------------------------------------------- | |
596 | -- in : dma_rr_grant |
|
582 | -- in : dma_rr_grant | |
@@ -711,40 +697,44 BEGIN | |||||
711 | -- Matrix Spectral |
|
697 | -- Matrix Spectral | |
712 | ----------------------------------------------------------------------------- |
|
698 | ----------------------------------------------------------------------------- | |
713 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
714 |
NOT(sample_f0_val) & NOT(sample_f0_val) |
|
700 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
715 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
716 |
NOT(sample_f1_val) & NOT(sample_f1_val) |
|
702 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
717 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
718 |
NOT(sample_f3_val) & NOT(sample_f3_val) |
|
704 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
719 |
|
705 | |||
720 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
721 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
722 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
723 |
|
709 | |||
724 | ------------------------------------------------------------------------------- |
|
710 | ------------------------------------------------------------------------------- | |
725 | lpp_lfr_ms_1: lpp_lfr_ms |
|
711 | ||
|
712 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |||
|
713 | ||||
|
714 | ----------------------------------------------------------------------------- | |||
|
715 | lpp_lfr_ms_1 : lpp_lfr_ms | |||
726 | GENERIC MAP ( |
|
716 | GENERIC MAP ( | |
727 |
Mem_use => Mem_use |
|
717 | Mem_use => Mem_use) | |
728 | PORT MAP ( |
|
718 | PORT MAP ( | |
729 | clk => clk, |
|
719 | clk => clk, | |
730 | rstn => rstn, |
|
720 | rstn => ms_softandhard_rstn, --rstn, | |
731 |
|
721 | |||
732 |
coarse_time |
|
722 | coarse_time => coarse_time, | |
733 |
fine_time |
|
723 | fine_time => fine_time, | |
734 |
|
||||
735 | sample_f0_wen => sample_f0_wen, |
|
|||
736 | sample_f0_wdata => sample_f0_wdata, |
|
|||
737 | sample_f1_wen => sample_f1_wen, |
|
|||
738 | sample_f1_wdata => sample_f1_wdata, |
|
|||
739 | sample_f3_wen => sample_f3_wen, |
|
|||
740 | sample_f3_wdata => sample_f3_wdata, |
|
|||
741 |
|
724 | |||
742 | dma_addr => data_ms_addr, -- |
|
725 | sample_f0_wen => sample_f0_wen, | |
743 | dma_data => data_ms_data, -- |
|
726 | sample_f0_wdata => sample_f0_wdata, | |
744 | dma_valid => data_ms_valid, -- |
|
727 | sample_f1_wen => sample_f1_wen, | |
745 | dma_valid_burst => data_ms_valid_burst, -- |
|
728 | sample_f1_wdata => sample_f1_wdata, | |
746 | dma_ren => data_ms_ren, -- |
|
729 | sample_f3_wen => sample_f3_wen, | |
747 | dma_done => data_ms_done, -- |
|
730 | sample_f3_wdata => sample_f3_wdata, | |
|
731 | ||||
|
732 | dma_addr => data_ms_addr, -- | |||
|
733 | dma_data => data_ms_data, -- | |||
|
734 | dma_valid => data_ms_valid, -- | |||
|
735 | dma_valid_burst => data_ms_valid_burst, -- | |||
|
736 | dma_ren => data_ms_ren, -- | |||
|
737 | dma_done => data_ms_done, -- | |||
748 |
|
738 | |||
749 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
739 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
750 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
740 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
@@ -752,7 +742,7 BEGIN | |||||
752 | ready_matrix_f2 => ready_matrix_f2, |
|
742 | ready_matrix_f2 => ready_matrix_f2, | |
753 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
743 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
754 | error_bad_component_error => error_bad_component_error, |
|
744 | error_bad_component_error => error_bad_component_error, | |
755 | debug_reg => observation_reg,--debug_reg, |
|
745 | debug_reg => observation_reg, --debug_reg, | |
756 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
746 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
757 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
747 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
758 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
748 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
@@ -764,6 +754,11 BEGIN | |||||
764 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
754 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
765 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
755 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
766 | addr_matrix_f1 => addr_matrix_f1, |
|
756 | addr_matrix_f1 => addr_matrix_f1, | |
767 |
addr_matrix_f2 => addr_matrix_f2 |
|
757 | addr_matrix_f2 => addr_matrix_f2, | |
768 |
|
758 | |||
|
759 | matrix_time_f0_0 => matrix_time_f0_0, | |||
|
760 | matrix_time_f0_1 => matrix_time_f0_1, | |||
|
761 | matrix_time_f1 => matrix_time_f1, | |||
|
762 | matrix_time_f2 => matrix_time_f2); | |||
|
763 | ||||
769 | END beh; |
|
764 | END beh; |
This diff has been collapsed as it changes many lines, (1037 lines changed) Show them Hide them | |||||
@@ -1,493 +1,544 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
31 | USE lpp.lpp_amba.ALL; |
|
31 | USE lpp.lpp_amba.ALL; | |
32 | USE lpp.apb_devices_list.ALL; |
|
32 | USE lpp.apb_devices_list.ALL; | |
33 | USE lpp.lpp_memory.ALL; |
|
33 | USE lpp.lpp_memory.ALL; | |
34 | LIBRARY techmap; |
|
34 | LIBRARY techmap; | |
35 | USE techmap.gencomp.ALL; |
|
35 | USE techmap.gencomp.ALL; | |
36 |
|
36 | |||
37 | ENTITY lpp_lfr_apbreg IS |
|
37 | ENTITY lpp_lfr_apbreg IS | |
38 | GENERIC ( |
|
38 | GENERIC ( | |
39 | nb_data_by_buffer_size : INTEGER := 11; |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
40 | nb_word_by_buffer_size : INTEGER := 11; |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
41 | nb_snapshot_param_size : INTEGER := 11; |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
42 | delta_vector_size : INTEGER := 20; |
|
42 | delta_vector_size : INTEGER := 20; | |
43 | delta_vector_size_f0_2 : INTEGER := 3; |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
44 |
|
44 | |||
45 | pindex : INTEGER := 4; |
|
45 | pindex : INTEGER := 4; | |
46 | paddr : INTEGER := 4; |
|
46 | paddr : INTEGER := 4; | |
47 | pmask : INTEGER := 16#fff#; |
|
47 | pmask : INTEGER := 16#fff#; | |
48 | pirq_ms : INTEGER := 0; |
|
48 | pirq_ms : INTEGER := 0; | |
49 | pirq_wfp : INTEGER := 1; |
|
49 | pirq_wfp : INTEGER := 1; | |
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
51 | PORT ( |
|
51 | PORT ( | |
52 | -- AMBA AHB system signals |
|
52 | -- AMBA AHB system signals | |
53 | HCLK : IN STD_ULOGIC; |
|
53 | HCLK : IN STD_ULOGIC; | |
54 | HRESETn : IN STD_ULOGIC; |
|
54 | HRESETn : IN STD_ULOGIC; | |
55 |
|
55 | |||
56 | -- AMBA APB Slave Interface |
|
56 | -- AMBA APB Slave Interface | |
57 | apbi : IN apb_slv_in_type; |
|
57 | apbi : IN apb_slv_in_type; | |
58 | apbo : OUT apb_slv_out_type; |
|
58 | apbo : OUT apb_slv_out_type; | |
59 |
|
59 | |||
60 | --------------------------------------------------------------------------- |
|
60 | --------------------------------------------------------------------------- | |
61 | -- Spectral Matrix Reg |
|
61 | -- Spectral Matrix Reg | |
62 | -- IN |
|
62 | run_ms : OUT STD_LOGIC; | |
63 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
63 | -- IN | |
64 |
ready_matrix_f0_ |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
65 | ready_matrix_f1 : IN STD_LOGIC; |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
66 |
ready_matrix_f |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
68 |
error_ |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
69 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
70 |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
71 | -- OUT |
|
71 | ||
72 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
72 | -- OUT | |
73 |
status_ready_matrix_f0_ |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
74 |
status_ready_matrix_f1 |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
75 |
status_ready_matrix_f |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
76 |
status_ |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
77 |
status_error_ |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
78 |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | ||
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
79 | ||
80 |
config_active_interruption_on |
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
81 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
82 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | ||
83 |
|
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 |
addr_matrix_f |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | --------------------------------------------------------------------------- |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | --------------------------------------------------------------------------- |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 | -- WaveForm picker Reg |
|
87 | ||
88 |
|
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 |
|
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 |
|
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
91 |
|
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
92 |
|
92 | |||
93 | -- OUT |
|
93 | --------------------------------------------------------------------------- | |
94 | data_shaping_BW : OUT STD_LOGIC; |
|
94 | --------------------------------------------------------------------------- | |
95 | data_shaping_SP0 : OUT STD_LOGIC; |
|
95 | -- WaveForm picker Reg | |
96 | data_shaping_SP1 : OUT STD_LOGIC; |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
97 | data_shaping_R0 : OUT STD_LOGIC; |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
98 | data_shaping_R1 : OUT STD_LOGIC; |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | ||
100 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
100 | ||
101 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
101 | -- OUT | |
102 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
103 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
104 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
105 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
106 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
107 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
107 | ||
108 |
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | ||
109 | enable_f0 : OUT STD_LOGIC; |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
110 | enable_f1 : OUT STD_LOGIC; |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
111 | enable_f2 : OUT STD_LOGIC; |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
112 | enable_f3 : OUT STD_LOGIC; |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | ||
114 | burst_f0 : OUT STD_LOGIC; |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
115 | burst_f1 : OUT STD_LOGIC; |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
116 | burst_f2 : OUT STD_LOGIC; |
|
116 | ||
117 |
|
117 | enable_f0 : OUT STD_LOGIC; | ||
118 |
|
|
118 | enable_f1 : OUT STD_LOGIC; | |
119 |
|
119 | enable_f2 : OUT STD_LOGIC; | ||
120 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | enable_f3 : OUT STD_LOGIC; | |
121 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | ||
122 |
|
|
122 | burst_f0 : OUT STD_LOGIC; | |
123 |
|
|
123 | burst_f1 : OUT STD_LOGIC; | |
124 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
124 | burst_f2 : OUT STD_LOGIC; | |
125 | --------------------------------------------------------------------------- |
|
125 | ||
126 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
126 | run : OUT STD_LOGIC; | |
127 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | ||
128 |
|
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 |
|
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 |
|
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 |
|
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
132 |
|
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
133 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
133 | --------------------------------------------------------------------------- | |
134 |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
135 | --------------------------------------------------------------------------- |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | ); |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
138 | END lpp_lfr_apbreg; |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
140 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | ||
142 | CONSTANT REVISION : INTEGER := 1; |
|
142 | ||
143 |
|
143 | --------------------------------------------------------------------------- | ||
144 | CONSTANT pconfig : apb_config_type := ( |
|
144 | ); | |
145 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
145 | ||
146 | 1 => apb_iobar(paddr, pmask)); |
|
146 | END lpp_lfr_apbreg; | |
147 |
|
147 | |||
148 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
149 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | ||
150 | config_active_interruption_onError : STD_LOGIC; |
|
150 | CONSTANT REVISION : INTEGER := 1; | |
151 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
151 | ||
152 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
152 | CONSTANT pconfig : apb_config_type := ( | |
153 | status_ready_matrix_f1 : STD_LOGIC; |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
154 | status_ready_matrix_f2 : STD_LOGIC; |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
155 | status_error_anticipating_empty_fifo : STD_LOGIC; |
|
155 | ||
156 | status_error_bad_component_error : STD_LOGIC; |
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
157 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
158 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
159 |
|
|
159 | config_ms_run : STD_LOGIC; | |
160 |
|
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
161 | END RECORD; |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
162 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
163 |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | ||
164 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
165 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
166 |
|
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 |
|
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 | data_shaping_BW : STD_LOGIC; |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 | data_shaping_SP0 : STD_LOGIC; |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 | data_shaping_SP1 : STD_LOGIC; |
|
170 | ||
171 | data_shaping_R0 : STD_LOGIC; |
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
172 | data_shaping_R1 : STD_LOGIC; |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
174 |
|
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
175 | ||
176 |
|
|
176 | fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
177 |
|
|
177 | fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
178 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
178 | fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
179 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
179 | fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
180 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
180 | END RECORD; | |
181 | enable_f0 : STD_LOGIC; |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
182 | enable_f1 : STD_LOGIC; |
|
182 | ||
183 | enable_f2 : STD_LOGIC; |
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
184 |
|
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | burst_f0 : STD_LOGIC; |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | burst_f1 : STD_LOGIC; |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 |
|
|
187 | data_shaping_BW : STD_LOGIC; | |
188 | run : STD_LOGIC; |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
189 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
190 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
190 | data_shaping_R0 : STD_LOGIC; | |
191 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | data_shaping_R1 : STD_LOGIC; | |
192 |
|
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
193 |
|
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
194 | END RECORD; |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
195 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
196 |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | ||
197 |
|
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
198 |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | ||
199 | ----------------------------------------------------------------------------- |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
200 | -- IRQ |
|
200 | enable_f0 : STD_LOGIC; | |
201 | ----------------------------------------------------------------------------- |
|
201 | enable_f1 : STD_LOGIC; | |
202 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
202 | enable_f2 : STD_LOGIC; | |
203 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
203 | enable_f3 : STD_LOGIC; | |
204 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
204 | burst_f0 : STD_LOGIC; | |
205 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
205 | burst_f1 : STD_LOGIC; | |
206 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
206 | burst_f2 : STD_LOGIC; | |
207 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
207 | run : STD_LOGIC; | |
208 |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
209 | BEGIN -- beh |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
211 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
212 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
213 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
213 | END RECORD; | |
214 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
215 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
|
215 | ||
216 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 |
|
217 | |||
218 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
218 | ----------------------------------------------------------------------------- | |
219 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
219 | -- IRQ | |
220 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
220 | ----------------------------------------------------------------------------- | |
221 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
222 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
223 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
224 |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | ||
225 |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | ||
226 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
227 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
227 | ||
228 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
228 | BEGIN -- beh | |
229 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
229 | ||
230 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
231 |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | ||
232 | delta_snapshot <= reg_wp.delta_snapshot; |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
233 | delta_f0 <= reg_wp.delta_f0; |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
234 | delta_f0_2 <= reg_wp.delta_f0_2; |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
235 | delta_f1 <= reg_wp.delta_f1; |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
236 | delta_f2 <= reg_wp.delta_f2; |
|
236 | ||
237 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
238 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
239 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
240 |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | ||
241 | enable_f0 <= reg_wp.enable_f0; |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
242 | enable_f1 <= reg_wp.enable_f1; |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
243 | enable_f2 <= reg_wp.enable_f2; |
|
243 | ||
244 | enable_f3 <= reg_wp.enable_f3; |
|
244 | ||
245 |
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | ||
246 | burst_f0 <= reg_wp.burst_f0; |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
247 | burst_f1 <= reg_wp.burst_f1; |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
248 | burst_f2 <= reg_wp.burst_f2; |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
249 |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | ||
250 | run <= reg_wp.run; |
|
250 | ||
251 |
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | ||
252 |
|
|
252 | delta_f0 <= reg_wp.delta_f0; | |
253 |
|
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
254 |
|
|
254 | delta_f1 <= reg_wp.delta_f1; | |
255 |
|
|
255 | delta_f2 <= reg_wp.delta_f2; | |
256 |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | ||
257 | start_date <= reg_wp.start_date; |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
258 |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | ||
259 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
259 | ||
260 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
260 | enable_f0 <= reg_wp.enable_f0; | |
261 | BEGIN -- PROCESS lpp_dma_top |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
262 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
263 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
264 | reg_sp.config_active_interruption_onError <= '0'; |
|
264 | ||
265 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
265 | burst_f0 <= reg_wp.burst_f0; | |
266 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
267 | reg_sp.status_ready_matrix_f1 <= '0'; |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
268 | reg_sp.status_ready_matrix_f2 <= '0'; |
|
268 | ||
269 | reg_sp.status_error_anticipating_empty_fifo <= '0'; |
|
269 | run <= reg_wp.run; | |
270 | reg_sp.status_error_bad_component_error <= '0'; |
|
270 | ||
271 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
272 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
273 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
274 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
275 | prdata <= (OTHERS => '0'); |
|
275 | ||
276 |
|
276 | start_date <= reg_wp.start_date; | ||
277 | apbo.pirq <= (OTHERS => '0'); |
|
277 | ||
278 |
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | ||
279 | status_full_ack <= (OTHERS => '0'); |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
280 |
|
280 | BEGIN -- PROCESS lpp_dma_top | ||
281 | reg_wp.data_shaping_BW <= '0'; |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
282 | reg_wp.data_shaping_SP0 <= '0'; |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
283 | reg_wp.data_shaping_SP1 <= '0'; |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
284 | reg_wp.data_shaping_R0 <= '0'; |
|
284 | reg_sp.config_ms_run <= '1'; | |
285 |
reg_ |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
286 |
reg_ |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
287 |
reg_ |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
288 |
reg_ |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
289 | reg_wp.enable_f3 <= '0'; |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
290 | reg_wp.burst_f0 <= '0'; |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
291 |
reg_ |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
292 |
reg_ |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
293 |
reg_ |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
294 |
reg_ |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
295 | reg_wp.addr_data_f1 <= (OTHERS => '0'); |
|
295 | ||
296 |
|
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
297 |
reg_ |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
298 |
reg_ |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
299 |
reg_ |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
300 |
reg_ |
|
300 | reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
301 |
reg_ |
|
301 | reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
302 |
reg_ |
|
302 | reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
303 |
reg_ |
|
303 | reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
304 | reg_wp.delta_f1 <= (OTHERS => '0'); |
|
304 | ||
305 |
|
|
305 | prdata <= (OTHERS => '0'); | |
306 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
306 | ||
307 |
|
|
307 | apbo.pirq <= (OTHERS => '0'); | |
308 | reg_wp.start_date <= (OTHERS => '0'); |
|
308 | ||
309 |
|
309 | status_full_ack <= (OTHERS => '0'); | ||
310 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
310 | ||
311 | status_full_ack <= (OTHERS => '0'); |
|
311 | reg_wp.data_shaping_BW <= '0'; | |
312 |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | ||
313 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
314 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
315 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
316 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
316 | reg_wp.enable_f0 <= '0'; | |
317 |
|
317 | reg_wp.enable_f1 <= '0'; | ||
318 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
318 | reg_wp.enable_f2 <= '0'; | |
319 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
319 | reg_wp.enable_f3 <= '0'; | |
320 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
|
320 | reg_wp.burst_f0 <= '0'; | |
321 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
321 | reg_wp.burst_f1 <= '0'; | |
322 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
322 | reg_wp.burst_f2 <= '0'; | |
323 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
323 | reg_wp.run <= '0'; | |
324 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
325 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
326 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
327 | END LOOP all_status; |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
328 |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | ||
329 | paddr := "000000"; |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
330 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
331 |
|
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
332 | IF apbi.psel(pindex) = '1' THEN |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
333 | -- APB DMA READ -- |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
334 | CASE paddr(7 DOWNTO 2) IS |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
335 | -- |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
336 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
337 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
338 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
339 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
339 | ||
340 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
341 | prdata(3) <= reg_sp.status_ready_matrix_f2; |
|
341 | ||
342 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; |
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
343 | prdata(5) <= reg_sp.status_error_bad_component_error; |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
344 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
345 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
346 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
|
346 | ||
347 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
347 | reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
348 | WHEN "000110" => prdata <= debug_reg; |
|
348 | reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
349 | -- |
|
349 | reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
350 | WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; |
|
350 | reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
351 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
351 | ||
352 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
352 | status_full_ack <= (OTHERS => '0'); | |
353 | prdata(3) <= reg_wp.data_shaping_R0; |
|
353 | ||
354 | prdata(4) <= reg_wp.data_shaping_R1; |
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
355 | WHEN "001001" => prdata(0) <= reg_wp.enable_f0; |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
356 | prdata(1) <= reg_wp.enable_f1; |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
357 | prdata(2) <= reg_wp.enable_f2; |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
358 | prdata(3) <= reg_wp.enable_f3; |
|
358 | ||
359 | prdata(4) <= reg_wp.burst_f0; |
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
360 | prdata(5) <= reg_wp.burst_f1; |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
361 | prdata(6) <= reg_wp.burst_f2; |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
362 | prdata(7) <= reg_wp.run; |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
363 | WHEN "001010" => prdata <= reg_wp.addr_data_f0; |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
364 | WHEN "001011" => prdata <= reg_wp.addr_data_f1; |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
365 | WHEN "001100" => prdata <= reg_wp.addr_data_f2; |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
366 | WHEN "001101" => prdata <= reg_wp.addr_data_f3; |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
367 | WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
368 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
368 | END LOOP all_status; | |
369 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
369 | ||
370 | WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
370 | paddr := "000000"; | |
371 | WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
372 | WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
372 | prdata <= (OTHERS => '0'); | |
373 | WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
374 | WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
374 | -- APB DMA READ -- | |
375 | WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
376 | WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
376 | -- | |
377 | WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
378 | WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
379 | ---------------------------------------------------- |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
380 |
WHEN " |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
381 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
382 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
383 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
384 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
385 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
386 |
WHEN " |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
387 |
WHEN " |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
388 | ---------------------------------------------------- |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
389 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
390 | WHEN OTHERS => NULL; |
|
390 | ||
391 | END CASE; |
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
392 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
393 | -- APB DMA WRITE -- |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
394 | CASE paddr(7 DOWNTO 2) IS |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
395 | -- |
|
395 | WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0; | |
396 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
396 | WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1; | |
397 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
397 | WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1; | |
398 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
398 | WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2; | |
399 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
|
399 | ||
400 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
400 | WHEN "001111" => prdata <= debug_reg; | |
401 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
|
401 | --------------------------------------------------------------------- | |
402 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
403 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
404 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
405 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
406 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
407 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
408 |
|
|
408 | prdata(1) <= reg_wp.enable_f1; | |
409 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
410 |
|
|
410 | prdata(3) <= reg_wp.enable_f3; | |
411 |
|
|
411 | prdata(4) <= reg_wp.burst_f0; | |
412 |
|
|
412 | prdata(5) <= reg_wp.burst_f1; | |
413 |
|
|
413 | prdata(6) <= reg_wp.burst_f2; | |
414 | WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); |
|
414 | prdata(7) <= reg_wp.run; | |
415 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
416 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
417 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
418 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
419 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
420 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
421 | reg_wp.run <= apbi.pwdata(7); |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
422 | WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
423 | WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
424 | WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
425 | WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
426 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
427 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
428 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
429 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
430 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
431 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
431 | ---------------------------------------------------- | |
432 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
433 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
434 | WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
435 | WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
436 | WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
437 | WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
438 | WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
439 | WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
440 | WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
440 | ---------------------------------------------------- | |
441 | WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
442 | -- |
|
442 | WHEN OTHERS => NULL; | |
443 | WHEN OTHERS => NULL; |
|
443 | ||
444 |
|
|
444 | END CASE; | |
445 | END IF; |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
446 | END IF; |
|
446 | -- APB DMA WRITE -- | |
447 |
|
447 | CASE paddr(7 DOWNTO 2) IS | ||
448 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR |
|
448 | -- | |
449 | ready_matrix_f0_1 OR |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
450 | ready_matrix_f1 OR |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
451 | ready_matrix_f2) |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
452 | ) |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
453 | OR |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
454 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
455 | error_bad_component_error) |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
456 | )); |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
457 |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | ||
458 | --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
459 | -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
460 | -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
461 | -- status_full(3) OR status_full_err(3) OR status_new_err(3) |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
462 |
|
|
462 | -- | |
463 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
464 |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | ||
465 | END IF; |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
466 | END PROCESS lpp_lfr_apbreg; |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
467 |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | ||
468 | apbo.pindex <= pindex; |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
469 | apbo.pconfig <= pconfig; |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
470 | apbo.prdata <= prdata; |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
471 |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | ||
472 | ----------------------------------------------------------------------------- |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
473 | -- IRQ |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
474 | ----------------------------------------------------------------------------- |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
475 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
476 |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | ||
477 | PROCESS (HCLK, HRESETn) |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
478 | BEGIN -- PROCESS |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
479 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
480 | irq_wfp_reg <= (OTHERS => '0'); |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
481 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
482 | irq_wfp_reg <= irq_wfp_reg_s; |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
483 | END IF; |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
484 | END PROCESS; |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
485 |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | ||
486 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
487 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
488 | END GENERATE all_irq_wfp; |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
489 |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | ||
490 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
491 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
492 |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | ||
493 | END beh; |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |||
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |||
|
496 | -- | |||
|
497 | WHEN OTHERS => NULL; | |||
|
498 | END CASE; | |||
|
499 | END IF; | |||
|
500 | END IF; | |||
|
501 | ||||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |||
|
503 | ready_matrix_f0_1 OR | |||
|
504 | ready_matrix_f1 OR | |||
|
505 | ready_matrix_f2) | |||
|
506 | ) | |||
|
507 | OR | |||
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |||
|
509 | error_bad_component_error) | |||
|
510 | )); | |||
|
511 | ||||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |||
|
513 | ||||
|
514 | END IF; | |||
|
515 | END PROCESS lpp_lfr_apbreg; | |||
|
516 | ||||
|
517 | apbo.pindex <= pindex; | |||
|
518 | apbo.pconfig <= pconfig; | |||
|
519 | apbo.prdata <= prdata; | |||
|
520 | ||||
|
521 | ----------------------------------------------------------------------------- | |||
|
522 | -- IRQ | |||
|
523 | ----------------------------------------------------------------------------- | |||
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |||
|
525 | ||||
|
526 | PROCESS (HCLK, HRESETn) | |||
|
527 | BEGIN -- PROCESS | |||
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |||
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |||
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |||
|
532 | END IF; | |||
|
533 | END PROCESS; | |||
|
534 | ||||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |||
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |||
|
537 | END GENERATE all_irq_wfp; | |||
|
538 | ||||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |||
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |||
|
541 | ||||
|
542 | run_ms <= reg_sp.config_ms_run; | |||
|
543 | ||||
|
544 | END beh; |
@@ -82,7 +82,13 ENTITY lpp_lfr_ms IS | |||||
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
91 | ||||
86 | ); |
|
92 | ); | |
87 | END; |
|
93 | END; | |
88 |
|
94 | |||
@@ -354,7 +360,13 BEGIN | |||||
354 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
360 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
355 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
361 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
356 | addr_matrix_f1 => addr_matrix_f1, |
|
362 | addr_matrix_f1 => addr_matrix_f1, | |
357 |
addr_matrix_f2 => addr_matrix_f2 |
|
363 | addr_matrix_f2 => addr_matrix_f2, | |
|
364 | ||||
|
365 | matrix_time_f0_0 => matrix_time_f0_0, | |||
|
366 | matrix_time_f0_1 => matrix_time_f0_1, | |||
|
367 | matrix_time_f1 => matrix_time_f1, | |||
|
368 | matrix_time_f2 => matrix_time_f2 | |||
|
369 | ); | |||
358 |
|
370 | |||
359 |
|
371 | |||
360 |
|
372 |
@@ -89,7 +89,12 ENTITY lpp_lfr_ms_fsmdma IS | |||||
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
93 | ||||
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
93 |
|
98 | |||
94 | ); |
|
99 | ); | |
95 | END; |
|
100 | END; | |
@@ -228,10 +233,22 BEGIN | |||||
228 | -- |
|
233 | -- | |
229 | IF component_type = "0000" THEN |
|
234 | IF component_type = "0000" THEN | |
230 | address <= address_matrix; |
|
235 | address <= address_matrix; | |
231 | state <= WRITE_COARSE_TIME; |
|
236 | CASE matrix_type IS | |
|
237 | WHEN "00" => matrix_time_f0_0 <= data_time; | |||
|
238 | WHEN "01" => matrix_time_f0_1 <= data_time; | |||
|
239 | WHEN "10" => matrix_time_f1 <= data_time; | |||
|
240 | WHEN "11" => matrix_time_f2 <= data_time ; | |||
|
241 | WHEN OTHERS => NULL; | |||
|
242 | END CASE; | |||
|
243 | ||||
232 |
|
|
244 | header_data <= data_time(31 DOWNTO 0); | |
233 | fine_time_reg <= data_time(47 DOWNTO 32); |
|
245 | fine_time_reg <= data_time(47 DOWNTO 32); | |
234 | header_send <= '1'; |
|
246 | --state <= WRITE_COARSE_TIME; | |
|
247 | --header_send <= '1'; | |||
|
248 | state <= SEND_DATA; | |||
|
249 | header_send <= '0'; | |||
|
250 | component_send <= '1'; | |||
|
251 | header_select <= '0'; | |||
235 | ELSE |
|
252 | ELSE | |
236 | state <= SEND_DATA; |
|
253 | state <= SEND_DATA; | |
237 | END IF; |
|
254 | END IF; | |
@@ -274,7 +291,6 BEGIN | |||||
274 | debug_reg_s(2 DOWNTO 0) <= "011"; |
|
291 | debug_reg_s(2 DOWNTO 0) <= "011"; | |
275 |
|
292 | |||
276 | header_ack <= '0'; |
|
293 | header_ack <= '0'; | |
277 | header_ack <= '0'; |
|
|||
278 |
|
294 | |||
279 | IF dma_ren = '0' THEN |
|
295 | IF dma_ren = '0' THEN | |
280 | header_send <= '0'; |
|
296 | header_send <= '0'; | |
@@ -308,6 +324,7 BEGIN | |||||
308 | END IF; |
|
324 | END IF; | |
309 |
|
325 | |||
310 | WHEN SEND_DATA => |
|
326 | WHEN SEND_DATA => | |
|
327 | header_ack <= '0'; | |||
311 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
328 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
312 |
|
329 | |||
313 | IF fifo_empty = '1' THEN |
|
330 | IF fifo_empty = '1' THEN | |
@@ -341,6 +358,7 BEGIN | |||||
341 | END IF; |
|
358 | END IF; | |
342 |
|
359 | |||
343 | WHEN CHECK_LENGTH => |
|
360 | WHEN CHECK_LENGTH => | |
|
361 | component_send <= '0'; | |||
344 | debug_reg_s(2 DOWNTO 0) <= "111"; |
|
362 | debug_reg_s(2 DOWNTO 0) <= "111"; | |
345 | state <= IDLE; |
|
363 | state <= IDLE; | |
346 |
|
364 |
@@ -57,7 +57,12 PACKAGE lpp_lfr_pkg IS | |||||
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
61 | ||||
|
62 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
64 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
65 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |||
61 | END COMPONENT; |
|
66 | END COMPONENT; | |
62 |
|
67 | |||
63 | COMPONENT lpp_lfr_ms_fsmdma |
|
68 | COMPONENT lpp_lfr_ms_fsmdma | |
@@ -95,7 +100,13 PACKAGE lpp_lfr_pkg IS | |||||
95 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
96 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
97 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
104 | ||||
|
105 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
107 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
108 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
109 | ); | |||
99 | END COMPONENT; |
|
110 | END COMPONENT; | |
100 |
|
111 | |||
101 |
|
112 | |||
@@ -172,6 +183,7 PACKAGE lpp_lfr_pkg IS | |||||
172 | HRESETn : IN STD_ULOGIC; |
|
183 | HRESETn : IN STD_ULOGIC; | |
173 | apbi : IN apb_slv_in_type; |
|
184 | apbi : IN apb_slv_in_type; | |
174 | apbo : OUT apb_slv_out_type; |
|
185 | apbo : OUT apb_slv_out_type; | |
|
186 | run_ms : OUT STD_LOGIC; | |||
175 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
187 | ready_matrix_f0_0 : IN STD_LOGIC; | |
176 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
188 | ready_matrix_f0_1 : IN STD_LOGIC; | |
177 | ready_matrix_f1 : IN STD_LOGIC; |
|
189 | ready_matrix_f1 : IN STD_LOGIC; | |
@@ -191,6 +203,12 PACKAGE lpp_lfr_pkg IS | |||||
191 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
205 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
206 | ||||
|
207 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
208 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
209 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
210 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
211 | ||||
194 |
|
|
212 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
195 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
213 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
196 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
214 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
@@ -257,7 +275,13 PACKAGE lpp_lfr_pkg IS | |||||
257 | apbo : OUT apb_slv_out_type; |
|
275 | apbo : OUT apb_slv_out_type; | |
258 | ahbi_ms : IN AHB_Mst_In_Type; |
|
276 | ahbi_ms : IN AHB_Mst_In_Type; | |
259 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
277 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
260 |
data_shaping_BW : OUT STD_LOGIC |
|
278 | data_shaping_BW : OUT STD_LOGIC; | |
|
279 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
280 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
281 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
282 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
|
283 | ||||
|
284 | ); | |||
261 | END COMPONENT; |
|
285 | END COMPONENT; | |
262 |
|
286 | |||
263 | END lpp_lfr_pkg; |
|
287 | END lpp_lfr_pkg; |
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