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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- LEON3 Demonstration design test bench |
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3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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4 | 4 | ------------------------------------------------------------------------------ |
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5 | 5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
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6 | 6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
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7 | 7 | -- |
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8 | 8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
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9 | 9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
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10 | 10 | -- IN ADVANCE IN WRITING. |
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11 | 11 | ------------------------------------------------------------------------------ |
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12 | 12 | |
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13 | 13 | LIBRARY ieee; |
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14 | 14 | USE ieee.std_logic_1164.ALL; |
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15 | 15 | |
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16 | 16 | --LIBRARY std; |
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17 | 17 | --USE std.textio.ALL; |
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18 | 18 | |
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19 | 19 | LIBRARY grlib; |
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20 | 20 | USE grlib.amba.ALL; |
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21 | 21 | USE grlib.stdlib.ALL; |
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22 | 22 | USE grlib.AMBA_TestPackage.ALL; |
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23 | 23 | LIBRARY gaisler; |
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24 | 24 | USE gaisler.memctrl.ALL; |
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25 | 25 | USE gaisler.leon3.ALL; |
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26 | 26 | USE gaisler.uart.ALL; |
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27 | 27 | USE gaisler.misc.ALL; |
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28 | 28 | USE gaisler.libdcom.ALL; |
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29 | 29 | USE gaisler.sim.ALL; |
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30 | 30 | USE gaisler.jtagtst.ALL; |
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31 | 31 | USE gaisler.misc.ALL; |
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32 | 32 | LIBRARY techmap; |
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33 | 33 | USE techmap.gencomp.ALL; |
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34 | 34 | LIBRARY esa; |
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35 | 35 | USE esa.memoryctrl.ALL; |
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36 | 36 | --LIBRARY micron; |
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37 | 37 | --USE micron.components.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_waveform_pkg.ALL; |
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40 | 40 | USE lpp.lpp_memory.ALL; |
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41 | 41 | USE lpp.lpp_ad_conv.ALL; |
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42 | 42 | USE lpp.testbench_package.ALL; |
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43 | 43 | USE lpp.lpp_lfr_pkg.ALL; |
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44 | 44 | USE lpp.iir_filter.ALL; |
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45 | 45 | USE lpp.general_purpose.ALL; |
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46 | 46 | USE lpp.CY7C1061DV33_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY testbench IS |
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49 | 49 | END; |
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50 | 50 | |
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51 | ||
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52 | ||
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53 | ||
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54 | ||
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55 | ||
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56 | ||
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57 | ||
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58 | ||
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59 | ||
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60 | ||
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61 | ||
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62 | ||
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63 | ||
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64 | ||
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65 | ||
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66 | ||
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67 | ||
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68 | ||
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69 | ||
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51 | 70 | ARCHITECTURE behav OF testbench IS |
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52 | 71 | CONSTANT INDEX_LFR : INTEGER := 15; |
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53 | 72 | CONSTANT ADDR_LFR : INTEGER := 15; |
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54 | 73 | -- REG MS |
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55 | 74 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; |
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56 | 75 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; |
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57 | 76 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; |
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58 | 77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; |
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78 | ||
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59 | 79 |
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60 | 80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; |
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61 |
CONSTANT ADDR_SPECTRAL_MATRIX_ |
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81 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |
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82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; | |
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83 | ||
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84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
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85 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
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86 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
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87 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |
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88 | ||
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89 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
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90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |
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91 | --X"00000F38"; | |
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92 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F"; | |
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93 | ||
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62 | 94 | -- REG WAVEFORM |
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63 |
CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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64 |
CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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65 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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66 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F |
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67 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
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68 |
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69 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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70 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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71 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA |
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72 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
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73 |
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74 |
CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 |
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75 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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76 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
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77 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
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78 |
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95 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
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96 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
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97 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
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98 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
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99 | ||
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100 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
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101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
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102 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
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103 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
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104 | ||
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105 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; | |
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106 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; | |
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107 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; | |
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108 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; | |
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109 | ||
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110 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; | |
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111 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; | |
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112 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; | |
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113 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; | |
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79 | 114 | -- RAM ADDRESS |
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80 | 115 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
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81 | 116 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
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82 | 117 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
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83 | 118 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
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84 | 119 | |
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85 | 120 | |
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86 | 121 | -- Common signal |
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87 | 122 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
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88 | 123 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
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89 | 124 | SIGNAL rstn : STD_LOGIC := '0'; |
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90 | 125 | |
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91 | 126 | -- ADC interface |
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92 | 127 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
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93 | 128 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
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94 | 129 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
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95 | 130 | |
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96 | 131 | -- AD Converter RHF1401 |
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97 | 132 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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98 | 133 | SIGNAL sample_val : STD_LOGIC; |
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99 | 134 | |
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100 | 135 | -- AHB/APB SIGNAL |
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101 | 136 | SIGNAL apbi : apb_slv_in_type; |
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102 | 137 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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103 | 138 | SIGNAL ahbsi : ahb_slv_in_type; |
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104 | 139 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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105 | 140 | SIGNAL ahbmi : ahb_mst_in_type; |
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106 | 141 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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107 | 142 | |
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108 | 143 | SIGNAL bias_fail_bw : STD_LOGIC; |
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109 | 144 | |
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110 | 145 | ----------------------------------------------------------------------------- |
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111 | 146 | -- LPP_WAVEFORM |
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112 | 147 | ----------------------------------------------------------------------------- |
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113 | 148 | CONSTANT data_size : INTEGER := 96; |
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114 | 149 | CONSTANT nb_burst_available_size : INTEGER := 50; |
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115 | 150 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
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116 | 151 | CONSTANT delta_vector_size : INTEGER := 2; |
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117 | 152 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
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118 | 153 | |
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119 | 154 | SIGNAL reg_run : STD_LOGIC; |
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120 | 155 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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121 | 156 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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122 | 157 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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123 | 158 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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124 | 159 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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125 | 160 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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126 | 161 | SIGNAL enable_f0 : STD_LOGIC; |
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127 | 162 | SIGNAL enable_f1 : STD_LOGIC; |
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128 | 163 | SIGNAL enable_f2 : STD_LOGIC; |
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129 | 164 | SIGNAL enable_f3 : STD_LOGIC; |
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130 | 165 | SIGNAL burst_f0 : STD_LOGIC; |
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131 | 166 | SIGNAL burst_f1 : STD_LOGIC; |
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132 | 167 | SIGNAL burst_f2 : STD_LOGIC; |
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133 | 168 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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134 | 169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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135 | 170 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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136 | 171 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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137 | 172 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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138 | 173 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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139 | 174 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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140 | 175 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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141 | 176 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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142 | 177 | SIGNAL data_f0_in_valid : STD_LOGIC; |
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143 | 178 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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144 | 179 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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145 | 180 | SIGNAL data_f1_in_valid : STD_LOGIC; |
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146 | 181 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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147 | 182 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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148 | 183 | SIGNAL data_f2_in_valid : STD_LOGIC; |
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149 | 184 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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150 | 185 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 186 | SIGNAL data_f3_in_valid : STD_LOGIC; |
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152 | 187 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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153 | 188 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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154 | 189 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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155 | 190 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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156 | 191 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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157 | 192 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
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158 | 193 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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159 | 194 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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160 | 195 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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161 | 196 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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162 | 197 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
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163 | 198 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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164 | 199 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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165 | 200 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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166 | 201 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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167 | 202 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
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168 | 203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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169 | 204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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170 | 205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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171 | 206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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172 | 207 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
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173 | 208 | |
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174 | 209 | --MEM CTRLR |
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175 | 210 | SIGNAL memi : memory_in_type; |
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176 | 211 | SIGNAL memo : memory_out_type; |
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177 | 212 | SIGNAL wpo : wprot_out_type; |
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178 | 213 | SIGNAL sdo : sdram_out_type; |
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179 | 214 | |
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180 | 215 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; |
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181 | 216 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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182 | 217 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
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183 | 218 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
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184 | 219 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
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185 | 220 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
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186 | 221 | SIGNAL nSRAM_WE : STD_LOGIC; |
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187 | 222 | SIGNAL nSRAM_CE : STD_LOGIC; |
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188 | 223 | SIGNAL nSRAM_OE : STD_LOGIC; |
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189 | 224 | |
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190 | 225 | CONSTANT padtech : INTEGER := inferred; |
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191 | 226 | SIGNAL not_ramsn_0 : STD_LOGIC; |
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192 | 227 | |
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193 | 228 | ----------------------------------------------------------------------------- |
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194 | 229 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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195 | 230 | SIGNAL read_buffer : STD_LOGIC; |
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196 | 231 | ----------------------------------------------------------------------------- |
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197 | 232 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; |
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198 | 233 | SIGNAL state_read_buffer_on_going : STD_LOGIC; |
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199 | 234 | CONSTANT hindex : INTEGER := 1; |
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200 | 235 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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201 | 236 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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202 | 237 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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203 | 238 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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204 | 239 | |
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205 | 240 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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206 | 241 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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207 | 242 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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208 | 243 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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209 | 244 | |
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210 | 245 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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211 | 246 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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212 | 247 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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213 | 248 | |
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214 | 249 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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215 | 250 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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216 | 251 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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217 | 252 | |
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218 | 253 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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219 | 254 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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220 | 255 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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221 | 256 | |
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222 | 257 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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223 | 258 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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224 | 259 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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225 | 260 | |
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226 | 261 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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227 | 262 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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228 | 263 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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229 | 264 | |
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230 | 265 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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231 | 266 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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232 | 267 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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233 | 268 | ----------------------------------------------------------------------------- |
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234 | 269 | |
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235 | 270 | SIGNAL current_data : INTEGER; |
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236 | 271 | SIGNAL LIMIT_DATA : INTEGER := 64; |
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237 | 272 | |
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238 | 273 | SIGNAL read_buffer_temp : STD_LOGIC; |
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239 | 274 | SIGNAL read_buffer_temp_2 : STD_LOGIC; |
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240 | 275 | |
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241 | 276 | |
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242 | 277 | BEGIN |
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243 | 278 | |
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244 | 279 | ----------------------------------------------------------------------------- |
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245 | 280 | |
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246 | 281 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
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247 | 282 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
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248 | 283 | |
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249 | 284 | ----------------------------------------------------------------------------- |
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250 | 285 | |
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251 | 286 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
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252 | 287 | TestModule_RHF1401_1 : TestModule_RHF1401 |
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253 | 288 | GENERIC MAP ( |
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254 | 289 | freq => 24*(I+1), |
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255 | 290 | amplitude => 8000/(I+1), |
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256 | 291 | impulsion => 0) |
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257 | 292 | PORT MAP ( |
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258 | 293 | ADC_smpclk => ADC_smpclk, |
|
259 | 294 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
260 | 295 | ADC_data => ADC_data); |
|
261 | 296 | END GENERATE MODULE_RHF1401; |
|
262 | 297 | |
|
263 | 298 | ----------------------------------------------------------------------------- |
|
264 | 299 | |
|
265 | 300 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
266 | 301 | GENERIC MAP ( |
|
267 | 302 | ChanelCount => 8, |
|
268 | 303 | ncycle_cnv_high => 79, |
|
269 | 304 | ncycle_cnv => 500) |
|
270 | 305 | PORT MAP ( |
|
271 | 306 | cnv_clk => clk49_152MHz, |
|
272 | 307 | cnv_rstn => rstn, |
|
273 | 308 | cnv => ADC_smpclk, |
|
274 | 309 | clk => clk25MHz, |
|
275 | 310 | rstn => rstn, |
|
276 | 311 | ADC_data => ADC_data, |
|
277 | 312 | ADC_nOE => ADC_OEB_bar_CH, |
|
278 | 313 | sample => sample, |
|
279 | 314 | sample_val => sample_val); |
|
280 | 315 | |
|
281 | 316 | ----------------------------------------------------------------------------- |
|
282 | 317 | |
|
283 | 318 | lpp_lfr_1 : lpp_lfr |
|
284 | 319 | GENERIC MAP ( |
|
285 | 320 | Mem_use => use_CEL, -- use_RAM |
|
286 | 321 | nb_data_by_buffer_size => 32, |
|
287 | 322 | nb_word_by_buffer_size => 30, |
|
288 | 323 | nb_snapshot_param_size => 32, |
|
289 | 324 | delta_vector_size => 32, |
|
290 | 325 | delta_vector_size_f0_2 => 32, |
|
291 | 326 | pindex => INDEX_LFR, |
|
292 | 327 | paddr => ADDR_LFR, |
|
293 | 328 | pmask => 16#fff#, |
|
294 | 329 | pirq_ms => 6, |
|
295 | 330 | pirq_wfp => 14, |
|
296 | 331 | hindex => 0, |
|
297 | 332 | top_lfr_version => X"000001") |
|
298 | 333 | PORT MAP ( |
|
299 | 334 | clk => clk25MHz, |
|
300 | 335 | rstn => rstn, |
|
301 | 336 | sample_B => sample(2 DOWNTO 0), |
|
302 | 337 | sample_E => sample(7 DOWNTO 3), |
|
303 | 338 | sample_val => sample_val, |
|
304 | 339 | apbi => apbi, |
|
305 | 340 | apbo => apbo(15), |
|
306 | 341 | ahbi => ahbmi, |
|
307 | 342 | ahbo => ahbmo(0), |
|
308 | 343 | coarse_time => coarse_time, |
|
309 | 344 | fine_time => fine_time, |
|
310 | 345 | data_shaping_BW => bias_fail_bw); |
|
311 | 346 | |
|
312 | 347 | ----------------------------------------------------------------------------- |
|
313 | 348 | --- AHB CONTROLLER ------------------------------------------------- |
|
314 | 349 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
315 | 350 | GENERIC MAP (defmast => 0, split => 0, |
|
316 | 351 | rrobin => 1, ioaddr => 16#FFF#, |
|
317 | 352 | ioen => 0, nahbm => 2, nahbs => 1) |
|
318 | 353 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
319 | 354 | |
|
320 | 355 | |
|
321 | 356 | |
|
322 | 357 | --- AHB RAM ---------------------------------------------------------- |
|
323 | 358 | --ahbram0 : ahbram |
|
324 | 359 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
325 | 360 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
326 | 361 | --ahbram1 : ahbram |
|
327 | 362 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
328 | 363 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
329 | 364 | --ahbram2 : ahbram |
|
330 | 365 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
331 | 366 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
332 | 367 | --ahbram3 : ahbram |
|
333 | 368 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
334 | 369 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
335 | 370 | |
|
336 | 371 | ----------------------------------------------------------------------------- |
|
337 | 372 | ---------------------------------------------------------------------- |
|
338 | 373 | --- Memory controllers --------------------------------------------- |
|
339 | 374 | ---------------------------------------------------------------------- |
|
340 | 375 | memctrlr : mctrl GENERIC MAP ( |
|
341 | 376 | hindex => 0, |
|
342 | 377 | pindex => 0, |
|
343 | 378 | paddr => 0, |
|
344 | 379 | srbanks => 1 |
|
345 | 380 | ) |
|
346 | 381 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
347 | 382 | |
|
348 | 383 | memi.brdyn <= '1'; |
|
349 | 384 | memi.bexcn <= '1'; |
|
350 | 385 | memi.writen <= '1'; |
|
351 | 386 | memi.wrn <= "1111"; |
|
352 | 387 | memi.bwidth <= "10"; |
|
353 | 388 | |
|
354 | 389 | bdr : FOR i IN 0 TO 3 GENERATE |
|
355 | 390 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
356 | 391 | PORT MAP ( |
|
357 | 392 | data(31-i*8 DOWNTO 24-i*8), |
|
358 | 393 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
359 | 394 | memo.bdrive(i), |
|
360 | 395 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
361 | 396 | END GENERATE; |
|
362 | 397 | |
|
363 | 398 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
364 | 399 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
365 | 400 | |
|
366 | 401 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
367 | 402 | |
|
368 | 403 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
369 | 404 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
370 | 405 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
371 | 406 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
372 | 407 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
373 | 408 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
374 | 409 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
375 | 410 | |
|
376 | 411 | async_1Mx16_0: CY7C1061DV33 |
|
377 | 412 | GENERIC MAP ( |
|
378 | 413 | ADDR_BITS => 20, |
|
379 | 414 | DATA_BITS => 16, |
|
380 | 415 | depth => 1048576, |
|
381 | 416 | MEM_ARRAY_DEBUG => 32, |
|
382 | 417 | TimingInfo => TRUE, |
|
383 | 418 | TimingChecks => '1') |
|
384 | 419 | PORT MAP ( |
|
385 | 420 | CE1_b => '0', |
|
386 | 421 | CE2 => nSRAM_CE, |
|
387 | 422 | WE_b => nSRAM_WE, |
|
388 | 423 | OE_b => nSRAM_OE, |
|
389 | 424 | BHE_b => nSRAM_BE1, |
|
390 | 425 | BLE_b => nSRAM_BE0, |
|
391 | 426 | A => address, |
|
392 | 427 | DQ => data(15 DOWNTO 0)); |
|
393 | 428 | |
|
394 | 429 | async_1Mx16_1: CY7C1061DV33 |
|
395 | 430 | GENERIC MAP ( |
|
396 | 431 | ADDR_BITS => 20, |
|
397 | 432 | DATA_BITS => 16, |
|
398 | 433 | depth => 1048576, |
|
399 | 434 | MEM_ARRAY_DEBUG => 32, |
|
400 | 435 | TimingInfo => TRUE, |
|
401 | 436 | TimingChecks => '1') |
|
402 | 437 | PORT MAP ( |
|
403 | 438 | CE1_b => '0', |
|
404 | 439 | CE2 => nSRAM_CE, |
|
405 | 440 | WE_b => nSRAM_WE, |
|
406 | 441 | OE_b => nSRAM_OE, |
|
407 | 442 | BHE_b => nSRAM_BE3, |
|
408 | 443 | BLE_b => nSRAM_BE2, |
|
409 | 444 | A => address, |
|
410 | 445 | DQ => data(31 DOWNTO 16)); |
|
411 | 446 | |
|
412 | 447 | |
|
413 | 448 | ----------------------------------------------------------------------------- |
|
414 | 449 | |
|
415 | 450 | WaveGen_Proc : PROCESS |
|
416 | 451 | BEGIN |
|
417 | 452 | |
|
418 | 453 | -- insert signal assignments here |
|
419 | 454 | WAIT UNTIL clk25MHz = '1'; |
|
420 | 455 | rstn <= '0'; |
|
421 | 456 | apbi.psel(15) <= '0'; |
|
422 | 457 | apbi.pwrite <= '0'; |
|
423 | 458 | apbi.penable <= '0'; |
|
424 | 459 | apbi.paddr <= (OTHERS => '0'); |
|
425 | 460 | apbi.pwdata <= (OTHERS => '0'); |
|
426 | 461 | fine_time <= (OTHERS => '0'); |
|
427 | 462 | coarse_time <= (OTHERS => '0'); |
|
428 | 463 | WAIT UNTIL clk25MHz = '1'; |
|
429 | 464 | -- ahbmi.HGRANT(2) <= '1'; |
|
430 | 465 | -- ahbmi.HREADY <= '1'; |
|
431 | 466 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
432 | 467 | |
|
433 | 468 | WAIT UNTIL clk25MHz = '1'; |
|
434 | 469 | WAIT UNTIL clk25MHz = '1'; |
|
435 | 470 | rstn <= '1'; |
|
436 | 471 | WAIT UNTIL clk25MHz = '1'; |
|
437 | 472 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); |
|
438 | 473 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); |
|
439 | 474 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); |
|
440 | 475 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); |
|
441 | 476 | |
|
442 | 477 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); |
|
443 | 478 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); |
|
444 | 479 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); |
|
445 | 480 | WAIT UNTIL clk25MHz = '1'; |
|
446 | 481 | --------------------------------------------------------------------------- |
|
447 | 482 | -- CONFIGURATION STEP |
|
448 | 483 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
449 | 484 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); |
|
450 | 485 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); |
|
451 | 486 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); |
|
452 | 487 | |
|
453 | 488 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" |
|
454 | 489 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" |
|
455 | 490 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" |
|
456 | 491 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" |
|
457 | 492 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" |
|
458 | 493 | |
|
459 | 494 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" |
|
460 | 495 | -- |
|
461 | 496 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); |
|
462 | 497 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
463 | 498 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); |
|
464 | 499 | |
|
465 | 500 | |
|
466 | 501 | WAIT UNTIL clk25MHz = '1'; |
|
467 | 502 | WAIT UNTIL clk25MHz = '1'; |
|
468 | 503 | |
|
469 | 504 | |
|
470 | 505 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); |
|
471 | 506 | WAIT UNTIL clk25MHz = '1'; |
|
472 | 507 | WAIT UNTIL clk25MHz = '1'; |
|
473 | 508 | WAIT UNTIL clk25MHz = '1'; |
|
474 | 509 | WAIT UNTIL clk25MHz = '1'; |
|
475 | 510 | WAIT UNTIL clk25MHz = '1'; |
|
476 | 511 | WAIT UNTIL clk25MHz = '1'; |
|
477 | 512 | WAIT FOR 1 us; |
|
478 | 513 | coarse_time <= X"00000001"; |
|
479 | 514 | --------------------------------------------------------------------------- |
|
480 | 515 | -- RUN STEP |
|
481 | 516 | WAIT FOR 200 ms; |
|
482 | 517 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
483 | 518 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
484 | 519 | WAIT FOR 10 us; |
|
485 | 520 | WAIT UNTIL clk25MHz = '1'; |
|
486 | 521 | WAIT UNTIL clk25MHz = '1'; |
|
487 | 522 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
488 | 523 | WAIT UNTIL clk25MHz = '1'; |
|
489 | 524 | coarse_time <= X"00000010"; |
|
490 | 525 | WAIT FOR 100 ms; |
|
491 | 526 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
492 | 527 | WAIT FOR 10 us; |
|
493 | 528 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
494 | 529 | WAIT FOR 200 ms; |
|
495 | 530 | REPORT "*** END simulation ***" SEVERITY failure; |
|
496 | 531 | |
|
497 | 532 | |
|
498 | 533 | WAIT; |
|
499 | 534 | |
|
500 | 535 | END PROCESS WaveGen_Proc; |
|
501 | 536 | ----------------------------------------------------------------------------- |
|
502 | 537 | |
|
503 | 538 | ----------------------------------------------------------------------------- |
|
504 | 539 | -- IRQ |
|
505 | 540 | ----------------------------------------------------------------------------- |
|
506 | 541 | PROCESS (clk25MHz, rstn) |
|
507 | 542 | BEGIN -- PROCESS |
|
508 | 543 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
509 | 544 | |
|
510 | 545 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
511 | 546 | |
|
512 | 547 | END IF; |
|
513 | 548 | END PROCESS; |
|
514 | 549 | ----------------------------------------------------------------------------- |
|
515 | 550 | |
|
516 | 551 | END; |
@@ -1,580 +1,580 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk_50 : IN STD_LOGIC; |
|
52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
|
62 | 62 | TXD1 : IN STD_LOGIC; |
|
63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
|
67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
|
70 | 70 | nDTR2 : IN STD_LOGIC; |
|
71 | 71 | nRTS2 : IN STD_LOGIC; |
|
72 | 72 | nDCD2 : OUT STD_LOGIC; |
|
73 | 73 | |
|
74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
|
80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
|
83 | 83 | IO8 : INOUT STD_LOGIC; |
|
84 | 84 | IO9 : INOUT STD_LOGIC; |
|
85 | 85 | IO10 : INOUT STD_LOGIC; |
|
86 | 86 | IO11 : INOUT STD_LOGIC; |
|
87 | 87 | |
|
88 | 88 | --SPACE WIRE |
|
89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
98 | 98 | -- MINI LFR ADC INPUTS |
|
99 | 99 | ADC_nCS : OUT STD_LOGIC; |
|
100 | 100 | ADC_CLK : OUT STD_LOGIC; |
|
101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 | -- SRAM |
|
104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
|
105 | 105 | SRAM_CE : OUT STD_LOGIC; |
|
106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
|
107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
110 | 110 | ); |
|
111 | 111 | |
|
112 | 112 | END MINI_LFR_top; |
|
113 | 113 | |
|
114 | 114 | |
|
115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
122 | 122 | -- |
|
123 | 123 | SIGNAL errorn : STD_LOGIC; |
|
124 | 124 | -- UART AHB --------------------------------------------------------------- |
|
125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
127 | 127 | |
|
128 | 128 | -- UART APB --------------------------------------------------------------- |
|
129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
131 | 131 | -- |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
|
133 | 133 | |
|
134 | 134 | -- CONSTANTS |
|
135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
136 | 136 | -- |
|
137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
140 | 140 | |
|
141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
147 | 147 | |
|
148 | 148 | -- Spacewire signals |
|
149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
|
155 | 155 | SIGNAL swni : grspw_in_type; |
|
156 | 156 | SIGNAL swno : grspw_out_type; |
|
157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
|
159 | 159 | |
|
160 | 160 | --GPIO |
|
161 | 161 | SIGNAL gpioi : gpio_in_type; |
|
162 | 162 | SIGNAL gpioo : gpio_out_type; |
|
163 | 163 | |
|
164 | 164 | -- AD Converter ADS7886 |
|
165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
166 | 166 | SIGNAL sample_val : STD_LOGIC; |
|
167 | 167 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
168 | 168 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
169 | 169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
170 | 170 | |
|
171 | 171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
172 | 172 | |
|
173 | 173 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | 174 | ----------------------------------------------------------------------------- |
|
175 | 175 | |
|
176 | 176 | BEGIN -- beh |
|
177 | 177 | |
|
178 | 178 | ----------------------------------------------------------------------------- |
|
179 | 179 | -- CLK |
|
180 | 180 | ----------------------------------------------------------------------------- |
|
181 | 181 | |
|
182 | 182 | PROCESS(clk_50) |
|
183 | 183 | BEGIN |
|
184 | 184 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
185 | 185 | clk_50_s <= NOT clk_50_s; |
|
186 | 186 | END IF; |
|
187 | 187 | END PROCESS; |
|
188 | 188 | |
|
189 | 189 | PROCESS(clk_50_s) |
|
190 | 190 | BEGIN |
|
191 | 191 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
192 | 192 | clk_25 <= NOT clk_25; |
|
193 | 193 | END IF; |
|
194 | 194 | END PROCESS; |
|
195 | 195 | |
|
196 | 196 | PROCESS(clk_49) |
|
197 | 197 | BEGIN |
|
198 | 198 | IF clk_49'EVENT AND clk_49 = '1' THEN |
|
199 | 199 | clk_24 <= NOT clk_24; |
|
200 | 200 | END IF; |
|
201 | 201 | END PROCESS; |
|
202 | 202 | |
|
203 | 203 | ----------------------------------------------------------------------------- |
|
204 | 204 | |
|
205 | 205 | PROCESS (clk_25, reset) |
|
206 | 206 | BEGIN -- PROCESS |
|
207 | 207 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
208 | 208 | LED0 <= '0'; |
|
209 | 209 | LED1 <= '0'; |
|
210 | 210 | LED2 <= '0'; |
|
211 | 211 | --IO1 <= '0'; |
|
212 | 212 | --IO2 <= '1'; |
|
213 | 213 | --IO3 <= '0'; |
|
214 | 214 | --IO4 <= '0'; |
|
215 | 215 | --IO5 <= '0'; |
|
216 | 216 | --IO6 <= '0'; |
|
217 | 217 | --IO7 <= '0'; |
|
218 | 218 | --IO8 <= '0'; |
|
219 | 219 | --IO9 <= '0'; |
|
220 | 220 | --IO10 <= '0'; |
|
221 | 221 | --IO11 <= '0'; |
|
222 | 222 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
223 | 223 | LED0 <= '0'; |
|
224 | 224 | LED1 <= '1'; |
|
225 | 225 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
226 | 226 | --IO1 <= '1'; |
|
227 | 227 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
228 | 228 | --IO3 <= ADC_SDO(0); |
|
229 | 229 | --IO4 <= ADC_SDO(1); |
|
230 | 230 | --IO5 <= ADC_SDO(2); |
|
231 | 231 | --IO6 <= ADC_SDO(3); |
|
232 | 232 | --IO7 <= ADC_SDO(4); |
|
233 | 233 | --IO8 <= ADC_SDO(5); |
|
234 | 234 | --IO9 <= ADC_SDO(6); |
|
235 | 235 | --IO10 <= ADC_SDO(7); |
|
236 | 236 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
237 | 237 | END IF; |
|
238 | 238 | END PROCESS; |
|
239 | 239 | |
|
240 | 240 | PROCESS (clk_24, reset) |
|
241 | 241 | BEGIN -- PROCESS |
|
242 | 242 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
243 | 243 | I00_s <= '0'; |
|
244 | 244 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
245 | 245 | I00_s <= NOT I00_s ; |
|
246 | 246 | END IF; |
|
247 | 247 | END PROCESS; |
|
248 | 248 | -- IO0 <= I00_s; |
|
249 | 249 | |
|
250 | 250 | --UARTs |
|
251 | 251 | nCTS1 <= '1'; |
|
252 | 252 | nCTS2 <= '1'; |
|
253 | 253 | nDCD2 <= '1'; |
|
254 | 254 | |
|
255 | 255 | --EXT CONNECTOR |
|
256 | 256 | |
|
257 | 257 | --SPACE WIRE |
|
258 | 258 | |
|
259 | 259 | leon3_soc_1 : leon3_soc |
|
260 | 260 | GENERIC MAP ( |
|
261 | 261 | fabtech => apa3e, |
|
262 | 262 | memtech => apa3e, |
|
263 | 263 | padtech => inferred, |
|
264 | 264 | clktech => inferred, |
|
265 | 265 | disas => 0, |
|
266 | 266 | dbguart => 0, |
|
267 | 267 | pclow => 2, |
|
268 | 268 | clk_freq => 25000, |
|
269 | 269 | NB_CPU => 1, |
|
270 | 270 | ENABLE_FPU => 1, |
|
271 | 271 | FPU_NETLIST => 0, |
|
272 | 272 | ENABLE_DSU => 1, |
|
273 | 273 | ENABLE_AHB_UART => 1, |
|
274 | 274 | ENABLE_APB_UART => 1, |
|
275 | 275 | ENABLE_IRQMP => 1, |
|
276 | 276 | ENABLE_GPT => 1, |
|
277 | 277 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
278 | 278 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
279 | 279 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
280 | 280 | PORT MAP ( |
|
281 | 281 | clk => clk_25, |
|
282 | 282 | reset => reset, |
|
283 | 283 | errorn => errorn, |
|
284 | 284 | ahbrxd => TXD1, |
|
285 | 285 | ahbtxd => RXD1, |
|
286 | 286 | urxd1 => TXD2, |
|
287 | 287 | utxd1 => RXD2, |
|
288 | 288 | address => SRAM_A, |
|
289 | 289 | data => SRAM_DQ, |
|
290 | 290 | nSRAM_BE0 => SRAM_nBE(0), |
|
291 | 291 | nSRAM_BE1 => SRAM_nBE(1), |
|
292 | 292 | nSRAM_BE2 => SRAM_nBE(2), |
|
293 | 293 | nSRAM_BE3 => SRAM_nBE(3), |
|
294 | 294 | nSRAM_WE => SRAM_nWE, |
|
295 | 295 | nSRAM_CE => SRAM_CE, |
|
296 | 296 | nSRAM_OE => SRAM_nOE, |
|
297 | 297 | |
|
298 | 298 | apbi_ext => apbi_ext, |
|
299 | 299 | apbo_ext => apbo_ext, |
|
300 | 300 | ahbi_s_ext => ahbi_s_ext, |
|
301 | 301 | ahbo_s_ext => ahbo_s_ext, |
|
302 | 302 | ahbi_m_ext => ahbi_m_ext, |
|
303 | 303 | ahbo_m_ext => ahbo_m_ext); |
|
304 | 304 | |
|
305 | 305 | ------------------------------------------------------------------------------- |
|
306 | 306 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
307 | 307 | ------------------------------------------------------------------------------- |
|
308 | 308 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
309 | 309 | GENERIC MAP ( |
|
310 | 310 | pindex => 6, |
|
311 | 311 | paddr => 6, |
|
312 | 312 | pmask => 16#fff#, |
|
313 | 313 | pirq => 12, |
|
314 | 314 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 |
|
315 | 315 | PORT MAP ( |
|
316 | 316 | clk25MHz => clk_25, |
|
317 | 317 | clk49_152MHz => clk_24, -- 49.152MHz/2 |
|
318 | 318 | resetn => reset, |
|
319 | 319 | grspw_tick => swno.tickout, |
|
320 | 320 | apbi => apbi_ext, |
|
321 | 321 | apbo => apbo_ext(6), |
|
322 | 322 | coarse_time => coarse_time, |
|
323 | 323 | fine_time => fine_time); |
|
324 | 324 | |
|
325 | 325 | ----------------------------------------------------------------------- |
|
326 | 326 | --- SpaceWire -------------------------------------------------------- |
|
327 | 327 | ----------------------------------------------------------------------- |
|
328 | 328 | |
|
329 | 329 | SPW_EN <= '1'; |
|
330 | 330 | |
|
331 | 331 | spw_clk <= clk_50_s; |
|
332 | 332 | spw_rxtxclk <= spw_clk; |
|
333 | 333 | spw_rxclkn <= NOT spw_rxtxclk; |
|
334 | 334 | |
|
335 | 335 | -- PADS for SPW1 |
|
336 | 336 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
337 | 337 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
338 | 338 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | 339 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
340 | 340 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
341 | 341 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
342 | 342 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | 343 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
344 | 344 | -- PADS FOR SPW2 |
|
345 | 345 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
346 | 346 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
347 | 347 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | 348 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
349 | 349 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | 350 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
351 | 351 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | 352 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
353 | 353 | |
|
354 | 354 | -- GRSPW PHY |
|
355 | 355 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
356 | 356 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
357 | 357 | spw_phy0 : grspw_phy |
|
358 | 358 | GENERIC MAP( |
|
359 | 359 | tech => apa3e, |
|
360 | 360 | rxclkbuftype => 1, |
|
361 | 361 | scantest => 0) |
|
362 | 362 | PORT MAP( |
|
363 | 363 | rxrst => swno.rxrst, |
|
364 | 364 | di => dtmp(j), |
|
365 | 365 | si => stmp(j), |
|
366 | 366 | rxclko => spw_rxclk(j), |
|
367 | 367 | do => swni.d(j), |
|
368 | 368 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
369 | 369 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
370 | 370 | END GENERATE spw_inputloop; |
|
371 | 371 | |
|
372 | 372 | -- SPW core |
|
373 | 373 | sw0 : grspwm GENERIC MAP( |
|
374 | 374 | tech => apa3e, |
|
375 | 375 | hindex => 1, |
|
376 | 376 | pindex => 5, |
|
377 | 377 | paddr => 5, |
|
378 | 378 | pirq => 11, |
|
379 | 379 | sysfreq => 25000, -- CPU_FREQ |
|
380 | 380 | rmap => 1, |
|
381 | 381 | rmapcrc => 1, |
|
382 | 382 | fifosize1 => 16, |
|
383 | 383 | fifosize2 => 16, |
|
384 | 384 | rxclkbuftype => 1, |
|
385 | 385 | rxunaligned => 0, |
|
386 | 386 | rmapbufs => 4, |
|
387 | 387 | ft => 0, |
|
388 | 388 | netlist => 0, |
|
389 | 389 | ports => 2, |
|
390 | 390 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
391 | 391 | memtech => apa3e, |
|
392 | 392 | destkey => 2, |
|
393 | 393 | spwcore => 1 |
|
394 | 394 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
395 | 395 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
396 | 396 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
397 | 397 | ) |
|
398 | 398 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
399 | 399 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
400 | 400 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
401 | 401 | swni, swno); |
|
402 | 402 | |
|
403 | 403 | swni.tickin <= '0'; |
|
404 | 404 | swni.rmapen <= '1'; |
|
405 | 405 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | 406 | swni.tickinraw <= '0'; |
|
407 | 407 | swni.timein <= (OTHERS => '0'); |
|
408 | 408 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | 409 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | 410 | |
|
411 | 411 | ------------------------------------------------------------------------------- |
|
412 | 412 | -- LFR ------------------------------------------------------------------------ |
|
413 | 413 | ------------------------------------------------------------------------------- |
|
414 | 414 | lpp_lfr_1 : lpp_lfr |
|
415 | 415 | GENERIC MAP ( |
|
416 | 416 | Mem_use => use_RAM, |
|
417 | 417 | nb_data_by_buffer_size => 32, |
|
418 | 418 | nb_word_by_buffer_size => 30, |
|
419 | 419 | nb_snapshot_param_size => 32, |
|
420 | 420 | delta_vector_size => 32, |
|
421 | 421 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | 422 | pindex => 15, |
|
423 | 423 | paddr => 15, |
|
424 | 424 | pmask => 16#fff#, |
|
425 | 425 | pirq_ms => 6, |
|
426 | 426 | pirq_wfp => 14, |
|
427 | 427 | hindex => 2, |
|
428 |
top_lfr_version => X"00010 |
|
|
428 | top_lfr_version => X"000104") -- aa.bb.cc version | |
|
429 | 429 | PORT MAP ( |
|
430 | 430 | clk => clk_25, |
|
431 | 431 | rstn => reset, |
|
432 | 432 | sample_B => sample(2 DOWNTO 0), |
|
433 | 433 | sample_E => sample(7 DOWNTO 3), |
|
434 | 434 | sample_val => sample_val, |
|
435 | 435 | apbi => apbi_ext, |
|
436 | 436 | apbo => apbo_ext(15), |
|
437 | 437 | ahbi => ahbi_m_ext, |
|
438 | 438 | ahbo => ahbo_m_ext(2), |
|
439 | 439 | coarse_time => coarse_time, |
|
440 | 440 | fine_time => fine_time, |
|
441 | 441 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | 442 | observation_reg => observation_reg); |
|
443 | 443 | |
|
444 | 444 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
445 | 445 | GENERIC MAP( |
|
446 | 446 | ChannelCount => 8, |
|
447 | 447 | SampleNbBits => 14, |
|
448 | 448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
449 | 449 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
450 | 450 | PORT MAP ( |
|
451 | 451 | -- CONV |
|
452 | 452 | cnv_clk => clk_24, |
|
453 | 453 | cnv_rstn => reset, |
|
454 | 454 | cnv => ADC_nCS_sig, |
|
455 | 455 | -- DATA |
|
456 | 456 | clk => clk_25, |
|
457 | 457 | rstn => reset, |
|
458 | 458 | sck => ADC_CLK_sig, |
|
459 | 459 | sdo => ADC_SDO_sig, |
|
460 | 460 | -- SAMPLE |
|
461 | 461 | sample => sample, |
|
462 | 462 | sample_val => sample_val); |
|
463 | 463 | |
|
464 | 464 | --IO10 <= ADC_SDO_sig(5); |
|
465 | 465 | --IO9 <= ADC_SDO_sig(4); |
|
466 | 466 | --IO8 <= ADC_SDO_sig(3); |
|
467 | 467 | |
|
468 | 468 | ADC_nCS <= ADC_nCS_sig; |
|
469 | 469 | ADC_CLK <= ADC_CLK_sig; |
|
470 | 470 | ADC_SDO_sig <= ADC_SDO; |
|
471 | 471 | |
|
472 | 472 | ---------------------------------------------------------------------- |
|
473 | 473 | --- GPIO ----------------------------------------------------------- |
|
474 | 474 | ---------------------------------------------------------------------- |
|
475 | 475 | |
|
476 | 476 | grgpio0 : grgpio |
|
477 | 477 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
478 | 478 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
479 | 479 | |
|
480 | 480 | --pio_pad_0 : iopad |
|
481 | 481 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
482 | 482 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
483 | 483 | --pio_pad_1 : iopad |
|
484 | 484 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
485 | 485 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
486 | 486 | --pio_pad_2 : iopad |
|
487 | 487 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | 488 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
489 | 489 | --pio_pad_3 : iopad |
|
490 | 490 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | 491 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
492 | 492 | --pio_pad_4 : iopad |
|
493 | 493 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | 494 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
495 | 495 | --pio_pad_5 : iopad |
|
496 | 496 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | 497 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
498 | 498 | --pio_pad_6 : iopad |
|
499 | 499 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | 500 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
501 | 501 | --pio_pad_7 : iopad |
|
502 | 502 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | 503 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
504 | 504 | |
|
505 | 505 | PROCESS (clk_25, reset) |
|
506 | 506 | BEGIN -- PROCESS |
|
507 | 507 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
508 | 508 | IO0 <= '0'; |
|
509 | 509 | IO1 <= '0'; |
|
510 | 510 | IO2 <= '0'; |
|
511 | 511 | IO3 <= '0'; |
|
512 | 512 | IO4 <= '0'; |
|
513 | 513 | IO5 <= '0'; |
|
514 | 514 | IO6 <= '0'; |
|
515 | 515 | IO7 <= '0'; |
|
516 | 516 | IO8 <= '0'; |
|
517 | 517 | IO9 <= '0'; |
|
518 | 518 | IO10 <= '0'; |
|
519 | 519 | IO11 <= '0'; |
|
520 | 520 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
521 | 521 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
522 | 522 | WHEN "00" => |
|
523 | 523 | IO0 <= observation_reg(0 ); |
|
524 | 524 | IO1 <= observation_reg(1 ); |
|
525 | 525 | IO2 <= observation_reg(2 ); |
|
526 | 526 | IO3 <= observation_reg(3 ); |
|
527 | 527 | IO4 <= observation_reg(4 ); |
|
528 | 528 | IO5 <= observation_reg(5 ); |
|
529 | 529 | IO6 <= observation_reg(6 ); |
|
530 | 530 | IO7 <= observation_reg(7 ); |
|
531 | 531 | IO8 <= observation_reg(8 ); |
|
532 | 532 | IO9 <= observation_reg(9 ); |
|
533 | 533 | IO10 <= observation_reg(10); |
|
534 | 534 | IO11 <= observation_reg(11); |
|
535 | 535 | WHEN "01" => |
|
536 | 536 | IO0 <= observation_reg(0 + 12); |
|
537 | 537 | IO1 <= observation_reg(1 + 12); |
|
538 | 538 | IO2 <= observation_reg(2 + 12); |
|
539 | 539 | IO3 <= observation_reg(3 + 12); |
|
540 | 540 | IO4 <= observation_reg(4 + 12); |
|
541 | 541 | IO5 <= observation_reg(5 + 12); |
|
542 | 542 | IO6 <= observation_reg(6 + 12); |
|
543 | 543 | IO7 <= observation_reg(7 + 12); |
|
544 | 544 | IO8 <= observation_reg(8 + 12); |
|
545 | 545 | IO9 <= observation_reg(9 + 12); |
|
546 | 546 | IO10 <= observation_reg(10 + 12); |
|
547 | 547 | IO11 <= observation_reg(11 + 12); |
|
548 | 548 | WHEN "10" => |
|
549 | 549 | IO0 <= observation_reg(0 + 12 + 12); |
|
550 | 550 | IO1 <= observation_reg(1 + 12 + 12); |
|
551 | 551 | IO2 <= observation_reg(2 + 12 + 12); |
|
552 | 552 | IO3 <= observation_reg(3 + 12 + 12); |
|
553 | 553 | IO4 <= observation_reg(4 + 12 + 12); |
|
554 | 554 | IO5 <= observation_reg(5 + 12 + 12); |
|
555 | 555 | IO6 <= observation_reg(6 + 12 + 12); |
|
556 | 556 | IO7 <= observation_reg(7 + 12 + 12); |
|
557 | 557 | IO8 <= '0'; |
|
558 | 558 | IO9 <= '0'; |
|
559 | 559 | IO10 <= '0'; |
|
560 | 560 | IO11 <= '0'; |
|
561 | 561 | WHEN "11" => |
|
562 | 562 | IO0 <= '0'; |
|
563 | 563 | IO1 <= '0'; |
|
564 | 564 | IO2 <= '0'; |
|
565 | 565 | IO3 <= '0'; |
|
566 | 566 | IO4 <= '0'; |
|
567 | 567 | IO5 <= '0'; |
|
568 | 568 | IO6 <= '0'; |
|
569 | 569 | IO7 <= '0'; |
|
570 | 570 | IO8 <= '0'; |
|
571 | 571 | IO9 <= '0'; |
|
572 | 572 | IO10 <= '0'; |
|
573 | 573 | IO11 <= '0'; |
|
574 | 574 | WHEN OTHERS => NULL; |
|
575 | 575 | END CASE; |
|
576 | 576 | |
|
577 | 577 | END IF; |
|
578 | 578 | END PROCESS; |
|
579 | 579 | |
|
580 | END beh; No newline at end of file | |
|
580 | END beh; |
@@ -1,769 +1,764 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
|
12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY techmap; |
|
17 | 17 | USE techmap.gencomp.ALL; |
|
18 | 18 | |
|
19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
|
21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | USE grlib.devices.ALL; |
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
24 | 24 | |
|
25 | 25 | ENTITY lpp_lfr IS |
|
26 | 26 | GENERIC ( |
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
29 | 29 | nb_word_by_buffer_size : INTEGER := 11; |
|
30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
|
31 | 31 | delta_vector_size : INTEGER := 20; |
|
32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
33 | 33 | |
|
34 | 34 | pindex : INTEGER := 4; |
|
35 | 35 | paddr : INTEGER := 4; |
|
36 | 36 | pmask : INTEGER := 16#fff#; |
|
37 | 37 | pirq_ms : INTEGER := 0; |
|
38 | 38 | pirq_wfp : INTEGER := 1; |
|
39 | 39 | |
|
40 | 40 | hindex : INTEGER := 2; |
|
41 | 41 | |
|
42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
43 | 43 | |
|
44 | 44 | ); |
|
45 | 45 | PORT ( |
|
46 | 46 | clk : IN STD_LOGIC; |
|
47 | 47 | rstn : IN STD_LOGIC; |
|
48 | 48 | -- SAMPLE |
|
49 | 49 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
50 | 50 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
51 | 51 | sample_val : IN STD_LOGIC; |
|
52 | 52 | -- APB |
|
53 | 53 | apbi : IN apb_slv_in_type; |
|
54 | 54 | apbo : OUT apb_slv_out_type; |
|
55 | 55 | -- AHB |
|
56 | 56 | ahbi : IN AHB_Mst_In_Type; |
|
57 | 57 | ahbo : OUT AHB_Mst_Out_Type; |
|
58 | 58 | -- TIME |
|
59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
61 | 61 | -- |
|
62 | 62 | data_shaping_BW : OUT STD_LOGIC; |
|
63 | 63 | -- |
|
64 | 64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
65 | ||
|
65 | ||
|
66 | 66 | --debug |
|
67 | 67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
68 | 68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
69 | 69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
70 | 70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
71 | 71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
72 | 72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
73 | 73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
74 | 74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
75 | 75 | |
|
76 | 76 | ---- debug FIFO_IN |
|
77 | 77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
79 | 79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | 80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
81 | 81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | 82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
83 | 83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
85 | 85 | |
|
86 | 86 | ----debug FIFO OUT |
|
87 | 87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | 88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
89 | 89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
91 | 91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
93 | 93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
94 | 94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
95 | 95 | |
|
96 | 96 | ----debug DMA IN |
|
97 | 97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | 98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
99 | 99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | 100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
101 | 101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
102 | 102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
103 | 103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
104 | 104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
105 | 105 | ); |
|
106 | 106 | END lpp_lfr; |
|
107 | 107 | |
|
108 | 108 | ARCHITECTURE beh OF lpp_lfr IS |
|
109 | 109 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
110 | 110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
111 | 111 | -- |
|
112 | 112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
113 | 113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
114 | 114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
115 | 115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
116 | 116 | -- |
|
117 | 117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | 118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | 119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
120 | 120 | -- |
|
121 | 121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
122 | 122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
123 | 123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
124 | 124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
125 | 125 | -- |
|
126 | 126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | 127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | 128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | 129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
130 | 130 | -- |
|
131 | 131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | 132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | 133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
134 | 134 | |
|
135 | 135 | -- SM |
|
136 | 136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
137 | 137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
138 | 138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
139 | 139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
140 | 140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
141 | 141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
142 | 142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | 143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
144 | 144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
145 | 145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
146 | 146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
147 | 147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
148 | 148 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
149 | 149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
150 | 150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
151 | 151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | 152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | 153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | 154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | 155 | |
|
156 | 156 | -- WFP |
|
157 | 157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | 158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | 159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | 160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
161 | 161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | 162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
163 | 163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
164 | 164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | 165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
166 | 166 | |
|
167 | 167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
168 | 168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
169 | 169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
170 | 170 | SIGNAL enable_f0 : STD_LOGIC; |
|
171 | 171 | SIGNAL enable_f1 : STD_LOGIC; |
|
172 | 172 | SIGNAL enable_f2 : STD_LOGIC; |
|
173 | 173 | SIGNAL enable_f3 : STD_LOGIC; |
|
174 | 174 | SIGNAL burst_f0 : STD_LOGIC; |
|
175 | 175 | SIGNAL burst_f1 : STD_LOGIC; |
|
176 | 176 | SIGNAL burst_f2 : STD_LOGIC; |
|
177 | 177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | 178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | 179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | 180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
181 | 181 | |
|
182 | 182 | SIGNAL run : STD_LOGIC; |
|
183 | 183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
184 | 184 | |
|
185 | 185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | 186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
187 | 187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
188 | 188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
189 | 189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
190 | 190 | --f1 |
|
191 | 191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | 192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | 193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
194 | 194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
195 | 195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
196 | 196 | --f2 |
|
197 | 197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | 198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
199 | 199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
200 | 200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
201 | 201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
202 | 202 | --f3 |
|
203 | 203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | 204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
205 | 205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
206 | 206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
207 | 207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
208 | 208 | |
|
209 | 209 | ----------------------------------------------------------------------------- |
|
210 | 210 | -- |
|
211 | 211 | ----------------------------------------------------------------------------- |
|
212 | 212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
213 | 213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
214 | 214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
215 | 215 | --f1 |
|
216 | 216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | 217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
218 | 218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
219 | 219 | --f2 |
|
220 | 220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | 221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
222 | 222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
223 | 223 | --f3 |
|
224 | 224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
225 | 225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
226 | 226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
227 | 227 | |
|
228 | 228 | ----------------------------------------------------------------------------- |
|
229 | 229 | -- DMA RR |
|
230 | 230 | ----------------------------------------------------------------------------- |
|
231 | 231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
232 | 232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | 233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | 234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | 235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
236 | ||
|
237 |
SIGNAL dma_rr_grant |
|
|
238 |
SIGNAL dma_sel |
|
|
236 | ||
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
239 | 239 | |
|
240 | 240 | ----------------------------------------------------------------------------- |
|
241 | 241 | -- DMA_REG |
|
242 | 242 | ----------------------------------------------------------------------------- |
|
243 | 243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
244 | 244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
245 | 245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
246 | 246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
247 | 247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | 248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
249 | 249 | |
|
250 | 250 | |
|
251 | 251 | ----------------------------------------------------------------------------- |
|
252 | 252 | -- DMA |
|
253 | 253 | ----------------------------------------------------------------------------- |
|
254 | 254 | SIGNAL dma_send : STD_LOGIC; |
|
255 | 255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
256 | 256 | SIGNAL dma_done : STD_LOGIC; |
|
257 | 257 | SIGNAL dma_ren : STD_LOGIC; |
|
258 | 258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | 259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | 260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
261 | 261 | |
|
262 | 262 | ----------------------------------------------------------------------------- |
|
263 | 263 | -- DEBUG |
|
264 | 264 | ----------------------------------------------------------------------------- |
|
265 | 265 | -- |
|
266 | 266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
267 | 267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
268 | 268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
269 | 269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
270 | 270 | |
|
271 | 271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | 272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | 273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | 274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | 275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | 276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
277 | 277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
278 | 278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
279 | 279 | |
|
280 | 280 | ----------------------------------------------------------------------------- |
|
281 | 281 | -- MS |
|
282 | 282 | ----------------------------------------------------------------------------- |
|
283 | ||
|
283 | ||
|
284 | 284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | 285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
286 | 286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
287 | 287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
288 | 288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
289 | 289 | SIGNAL data_ms_done : STD_LOGIC; |
|
290 | ||
|
291 | SIGNAL run_ms : STD_LOGIC; | |
|
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
|
293 | ||
|
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
298 | ||
|
290 | 299 |
|
|
291 | 300 | BEGIN |
|
292 | 301 | |
|
293 | 302 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
294 | 303 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
295 | 304 | |
|
296 | 305 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
297 | 306 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
298 | 307 | END GENERATE all_channel; |
|
299 | 308 | |
|
300 | 309 | ----------------------------------------------------------------------------- |
|
301 | 310 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
302 | 311 | GENERIC MAP ( |
|
303 | 312 | Mem_use => Mem_use) |
|
304 | 313 | PORT MAP ( |
|
305 | 314 | sample => sample_s, |
|
306 | 315 | sample_val => sample_val, |
|
307 | 316 | clk => clk, |
|
308 | 317 | rstn => rstn, |
|
309 | 318 | data_shaping_SP0 => data_shaping_SP0, |
|
310 | 319 | data_shaping_SP1 => data_shaping_SP1, |
|
311 | 320 | data_shaping_R0 => data_shaping_R0, |
|
312 | 321 | data_shaping_R1 => data_shaping_R1, |
|
313 | 322 | sample_f0_val => sample_f0_val, |
|
314 | 323 | sample_f1_val => sample_f1_val, |
|
315 | 324 | sample_f2_val => sample_f2_val, |
|
316 | 325 | sample_f3_val => sample_f3_val, |
|
317 | 326 | sample_f0_wdata => sample_f0_data, |
|
318 | 327 | sample_f1_wdata => sample_f1_data, |
|
319 | 328 | sample_f2_wdata => sample_f2_data, |
|
320 | 329 | sample_f3_wdata => sample_f3_data); |
|
321 | 330 | |
|
322 | 331 | ----------------------------------------------------------------------------- |
|
323 | 332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
324 | 333 | GENERIC MAP ( |
|
325 | 334 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
326 | 335 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
327 | 336 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
328 | 337 | delta_vector_size => delta_vector_size, |
|
329 | 338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
330 | 339 | pindex => pindex, |
|
331 | 340 | paddr => paddr, |
|
332 | 341 | pmask => pmask, |
|
333 | 342 | pirq_ms => pirq_ms, |
|
334 | 343 | pirq_wfp => pirq_wfp, |
|
335 | 344 | top_lfr_version => top_lfr_version) |
|
336 | 345 | PORT MAP ( |
|
337 | HCLK => clk, | |
|
338 | HRESETn => rstn, | |
|
339 | apbi => apbi, | |
|
340 | apbo => apbo, | |
|
346 | HCLK => clk, | |
|
347 | HRESETn => rstn, | |
|
348 | apbi => apbi, | |
|
349 | apbo => apbo, | |
|
350 | ||
|
351 | run_ms => run_ms, | |
|
352 | ||
|
341 | 353 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
342 | 354 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
343 | 355 | ready_matrix_f1 => ready_matrix_f1, |
|
344 | 356 | ready_matrix_f2 => ready_matrix_f2, |
|
345 | 357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
346 | 358 | error_bad_component_error => error_bad_component_error, |
|
347 | 359 | debug_reg => debug_reg, |
|
348 | 360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
349 | 361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
350 | 362 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
351 | 363 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
352 | 364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
353 | 365 | status_error_bad_component_error => status_error_bad_component_error, |
|
354 | 366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
355 | 367 | config_active_interruption_onError => config_active_interruption_onError, |
|
356 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
357 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
358 | addr_matrix_f1 => addr_matrix_f1, | |
|
359 | addr_matrix_f2 => addr_matrix_f2, | |
|
360 | status_full => status_full, | |
|
361 | status_full_ack => status_full_ack, | |
|
362 | status_full_err => status_full_err, | |
|
363 | status_new_err => status_new_err, | |
|
364 | data_shaping_BW => data_shaping_BW, | |
|
365 | data_shaping_SP0 => data_shaping_SP0, | |
|
366 | data_shaping_SP1 => data_shaping_SP1, | |
|
367 | data_shaping_R0 => data_shaping_R0, | |
|
368 | data_shaping_R1 => data_shaping_R1, | |
|
369 | delta_snapshot => delta_snapshot, | |
|
370 | delta_f0 => delta_f0, | |
|
371 | delta_f0_2 => delta_f0_2, | |
|
372 | delta_f1 => delta_f1, | |
|
373 | delta_f2 => delta_f2, | |
|
374 | nb_data_by_buffer => nb_data_by_buffer, | |
|
375 | nb_word_by_buffer => nb_word_by_buffer, | |
|
376 | nb_snapshot_param => nb_snapshot_param, | |
|
377 | enable_f0 => enable_f0, | |
|
378 |
|
|
|
379 |
|
|
|
380 | enable_f3 => enable_f3, | |
|
381 | burst_f0 => burst_f0, | |
|
382 | burst_f1 => burst_f1, | |
|
383 | burst_f2 => burst_f2, | |
|
384 | run => run, | |
|
385 | addr_data_f0 => addr_data_f0, | |
|
386 | addr_data_f1 => addr_data_f1, | |
|
387 | addr_data_f2 => addr_data_f2, | |
|
388 | addr_data_f3 => addr_data_f3, | |
|
389 | start_date => start_date, | |
|
368 | ||
|
369 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
370 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
371 | matrix_time_f1 => matrix_time_f1, | |
|
372 | matrix_time_f2 => matrix_time_f2, | |
|
373 | ||
|
374 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
375 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
376 | addr_matrix_f1 => addr_matrix_f1, | |
|
377 | addr_matrix_f2 => addr_matrix_f2, | |
|
378 | status_full => status_full, | |
|
379 | status_full_ack => status_full_ack, | |
|
380 | status_full_err => status_full_err, | |
|
381 | status_new_err => status_new_err, | |
|
382 | data_shaping_BW => data_shaping_BW, | |
|
383 | data_shaping_SP0 => data_shaping_SP0, | |
|
384 | data_shaping_SP1 => data_shaping_SP1, | |
|
385 | data_shaping_R0 => data_shaping_R0, | |
|
386 | data_shaping_R1 => data_shaping_R1, | |
|
387 | delta_snapshot => delta_snapshot, | |
|
388 | delta_f0 => delta_f0, | |
|
389 | delta_f0_2 => delta_f0_2, | |
|
390 | delta_f1 => delta_f1, | |
|
391 | delta_f2 => delta_f2, | |
|
392 | nb_data_by_buffer => nb_data_by_buffer, | |
|
393 | nb_word_by_buffer => nb_word_by_buffer, | |
|
394 | nb_snapshot_param => nb_snapshot_param, | |
|
395 | enable_f0 => enable_f0, | |
|
396 | enable_f1 => enable_f1, | |
|
397 | enable_f2 => enable_f2, | |
|
398 | enable_f3 => enable_f3, | |
|
399 | burst_f0 => burst_f0, | |
|
400 | burst_f1 => burst_f1, | |
|
401 | burst_f2 => burst_f2, | |
|
402 | run => run, | |
|
403 | addr_data_f0 => addr_data_f0, | |
|
404 | addr_data_f1 => addr_data_f1, | |
|
405 | addr_data_f2 => addr_data_f2, | |
|
406 | addr_data_f3 => addr_data_f3, | |
|
407 | start_date => start_date, | |
|
390 | 408 | --------------------------------------------------------------------------- |
|
391 |
debug_reg0 |
|
|
392 |
debug_reg1 |
|
|
393 |
debug_reg2 |
|
|
394 |
debug_reg3 |
|
|
395 |
debug_reg4 |
|
|
396 |
debug_reg5 |
|
|
397 |
debug_reg6 |
|
|
398 |
debug_reg7 |
|
|
409 | debug_reg0 => debug_reg0, | |
|
410 | debug_reg1 => debug_reg1, | |
|
411 | debug_reg2 => debug_reg2, | |
|
412 | debug_reg3 => debug_reg3, | |
|
413 | debug_reg4 => debug_reg4, | |
|
414 | debug_reg5 => debug_reg5, | |
|
415 | debug_reg6 => debug_reg6, | |
|
416 | debug_reg7 => debug_reg7); | |
|
399 | 417 | |
|
400 | 418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
401 | 419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
402 | 420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
403 | 421 | ----------------------------------------------------------------------------- |
|
404 | 422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
405 | 423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
406 | 424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
407 | 425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
408 | 426 | |
|
409 | 427 | |
|
410 | 428 | ----------------------------------------------------------------------------- |
|
411 | 429 | lpp_waveform_1 : lpp_waveform |
|
412 | 430 | GENERIC MAP ( |
|
413 | 431 | tech => inferred, |
|
414 | 432 | data_size => 6*16, |
|
415 | 433 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
416 | 434 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
417 | 435 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
418 | 436 | delta_vector_size => delta_vector_size, |
|
419 | 437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
420 | 438 | ) |
|
421 | 439 | PORT MAP ( |
|
422 | 440 | clk => clk, |
|
423 | 441 | rstn => rstn, |
|
424 | 442 | |
|
425 | 443 | reg_run => run, |
|
426 | 444 | reg_start_date => start_date, |
|
427 | 445 | reg_delta_snapshot => delta_snapshot, |
|
428 | 446 | reg_delta_f0 => delta_f0, |
|
429 | 447 | reg_delta_f0_2 => delta_f0_2, |
|
430 | 448 | reg_delta_f1 => delta_f1, |
|
431 | 449 | reg_delta_f2 => delta_f2, |
|
432 | 450 | |
|
433 | 451 | enable_f0 => enable_f0, |
|
434 | 452 | enable_f1 => enable_f1, |
|
435 | 453 | enable_f2 => enable_f2, |
|
436 | 454 | enable_f3 => enable_f3, |
|
437 | 455 | burst_f0 => burst_f0, |
|
438 | 456 | burst_f1 => burst_f1, |
|
439 | 457 | burst_f2 => burst_f2, |
|
440 | 458 | |
|
441 | 459 | nb_data_by_buffer => nb_data_by_buffer, |
|
442 | 460 | nb_word_by_buffer => nb_word_by_buffer, |
|
443 | 461 | nb_snapshot_param => nb_snapshot_param, |
|
444 | 462 | status_full => status_full, |
|
445 | 463 | status_full_ack => status_full_ack, |
|
446 | 464 | status_full_err => status_full_err, |
|
447 | 465 | status_new_err => status_new_err, |
|
448 | 466 | |
|
449 | 467 | coarse_time => coarse_time, |
|
450 | 468 | fine_time => fine_time, |
|
451 | 469 | |
|
452 | 470 | --f0 |
|
453 | 471 | addr_data_f0 => addr_data_f0, |
|
454 | 472 | data_f0_in_valid => sample_f0_val, |
|
455 | 473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
456 | 474 | --f1 |
|
457 | 475 | addr_data_f1 => addr_data_f1, |
|
458 | 476 | data_f1_in_valid => sample_f1_val, |
|
459 | 477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
460 | 478 | --f2 |
|
461 | 479 | addr_data_f2 => addr_data_f2, |
|
462 | 480 | data_f2_in_valid => sample_f2_val, |
|
463 | 481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
464 | 482 | --f3 |
|
465 | 483 | addr_data_f3 => addr_data_f3, |
|
466 | 484 | data_f3_in_valid => sample_f3_val, |
|
467 | 485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
468 | 486 | -- OUTPUT -- DMA interface |
|
469 | 487 | --f0 |
|
470 | 488 | data_f0_addr_out => data_f0_addr_out_s, |
|
471 | 489 | data_f0_data_out => data_f0_data_out, |
|
472 | 490 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
473 | 491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
474 | 492 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
475 | 493 | --f1 |
|
476 | 494 | data_f1_addr_out => data_f1_addr_out_s, |
|
477 | 495 | data_f1_data_out => data_f1_data_out, |
|
478 | 496 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
479 | 497 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
480 | 498 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
481 | 499 | --f2 |
|
482 | 500 | data_f2_addr_out => data_f2_addr_out_s, |
|
483 | 501 | data_f2_data_out => data_f2_data_out, |
|
484 | 502 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
485 | 503 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
486 | 504 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
487 | 505 | --f3 |
|
488 | 506 | data_f3_addr_out => data_f3_addr_out_s, |
|
489 | 507 | data_f3_data_out => data_f3_data_out, |
|
490 | 508 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
491 | 509 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
492 | 510 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
493 | 511 | |
|
494 | 512 | ------------------------------------------------------------------------- |
|
495 |
observation_reg => OPEN |
|
|
496 | ---- debug SNAPSHOT_OUT | |
|
497 | --debug_f0_data => debug_f0_data, | |
|
498 | --debug_f0_data_valid => debug_f0_data_valid , | |
|
499 | --debug_f1_data => debug_f1_data , | |
|
500 | --debug_f1_data_valid => debug_f1_data_valid, | |
|
501 | --debug_f2_data => debug_f2_data , | |
|
502 | --debug_f2_data_valid => debug_f2_data_valid , | |
|
503 | --debug_f3_data => debug_f3_data , | |
|
504 | --debug_f3_data_valid => debug_f3_data_valid, | |
|
505 | ||
|
506 | ---- debug FIFO_IN | |
|
507 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , | |
|
508 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, | |
|
509 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , | |
|
510 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, | |
|
511 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , | |
|
512 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, | |
|
513 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , | |
|
514 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid | |
|
513 | observation_reg => OPEN | |
|
515 | 514 |
|
|
516 | 515 |
|
|
517 | 516 | |
|
518 | 517 | |
|
519 | 518 | ----------------------------------------------------------------------------- |
|
520 | -- DEBUG -- WFP OUT | |
|
521 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; | |
|
522 | --debug_f0_data_fifo_out <= data_f0_data_out; | |
|
523 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; | |
|
524 | --debug_f1_data_fifo_out <= data_f1_data_out; | |
|
525 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; | |
|
526 | --debug_f2_data_fifo_out <= data_f2_data_out; | |
|
527 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; | |
|
528 | --debug_f3_data_fifo_out <= data_f3_data_out; | |
|
529 | ----------------------------------------------------------------------------- | |
|
530 | ||
|
531 | ||
|
532 | ----------------------------------------------------------------------------- | |
|
533 | 519 | -- TEMP |
|
534 | 520 | ----------------------------------------------------------------------------- |
|
535 | 521 | |
|
536 | 522 | PROCESS (clk, rstn) |
|
537 | 523 | BEGIN -- PROCESS |
|
538 | 524 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
539 | 525 | data_f0_data_out_valid <= '0'; |
|
540 | 526 | data_f0_data_out_valid_burst <= '0'; |
|
541 | 527 | data_f1_data_out_valid <= '0'; |
|
542 | 528 | data_f1_data_out_valid_burst <= '0'; |
|
543 | 529 | data_f2_data_out_valid <= '0'; |
|
544 | 530 | data_f2_data_out_valid_burst <= '0'; |
|
545 | 531 | data_f3_data_out_valid <= '0'; |
|
546 | 532 | data_f3_data_out_valid_burst <= '0'; |
|
547 | 533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
548 | 534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
549 | 535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
550 | 536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
551 | 537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
552 | 538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
553 | 539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
554 | 540 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
555 | 541 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
556 | 542 | END IF; |
|
557 | 543 | END PROCESS; |
|
558 | 544 | |
|
559 | 545 | data_f0_addr_out <= data_f0_addr_out_s; |
|
560 | 546 | data_f1_addr_out <= data_f1_addr_out_s; |
|
561 | 547 | data_f2_addr_out <= data_f2_addr_out_s; |
|
562 | 548 | data_f3_addr_out <= data_f3_addr_out_s; |
|
563 | 549 | |
|
564 | 550 | ----------------------------------------------------------------------------- |
|
565 | 551 | -- RoundRobin Selection For DMA |
|
566 | 552 | ----------------------------------------------------------------------------- |
|
567 | 553 | |
|
568 | 554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
569 | 555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
570 | 556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
571 | 557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
572 | 558 | |
|
573 | 559 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
574 | 560 | PORT MAP ( |
|
575 | 561 | clk => clk, |
|
576 | 562 | rstn => rstn, |
|
577 | 563 | in_valid => dma_rr_valid, |
|
578 | 564 | out_grant => dma_rr_grant_s); |
|
579 | 565 | |
|
580 | 566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
581 | 567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
582 | 568 | dma_rr_valid_ms(2) <= '0'; |
|
583 | 569 | dma_rr_valid_ms(3) <= '0'; |
|
584 | ||
|
570 | ||
|
585 | 571 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
586 | 572 | PORT MAP ( |
|
587 | 573 | clk => clk, |
|
588 | 574 | rstn => rstn, |
|
589 | 575 | in_valid => dma_rr_valid_ms, |
|
590 | 576 | out_grant => dma_rr_grant_ms); |
|
591 | 577 | |
|
592 | 578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
593 | ||
|
579 | ||
|
594 | 580 | |
|
595 | 581 | ----------------------------------------------------------------------------- |
|
596 | 582 | -- in : dma_rr_grant |
|
597 | 583 | -- send |
|
598 | 584 | -- out : dma_sel |
|
599 | 585 | -- dma_valid_burst |
|
600 | 586 | -- dma_sel_valid |
|
601 | 587 | ----------------------------------------------------------------------------- |
|
602 | 588 | PROCESS (clk, rstn) |
|
603 | 589 | BEGIN -- PROCESS |
|
604 | 590 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
605 | 591 | dma_sel <= (OTHERS => '0'); |
|
606 | 592 | dma_send <= '0'; |
|
607 | 593 | dma_valid_burst <= '0'; |
|
608 | 594 | data_ms_done <= '0'; |
|
609 | 595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
610 | 596 | IF run = '1' THEN |
|
611 | 597 | data_ms_done <= '0'; |
|
612 | 598 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
613 | 599 | dma_sel <= dma_rr_grant; |
|
614 | 600 | IF dma_rr_grant(0) = '1' THEN |
|
615 | 601 | dma_send <= '1'; |
|
616 | 602 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
617 | 603 | dma_sel_valid <= data_f0_data_out_valid; |
|
618 | 604 | ELSIF dma_rr_grant(1) = '1' THEN |
|
619 | 605 | dma_send <= '1'; |
|
620 | 606 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
621 | 607 | dma_sel_valid <= data_f1_data_out_valid; |
|
622 | 608 | ELSIF dma_rr_grant(2) = '1' THEN |
|
623 | 609 | dma_send <= '1'; |
|
624 | 610 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
625 | 611 | dma_sel_valid <= data_f2_data_out_valid; |
|
626 | 612 | ELSIF dma_rr_grant(3) = '1' THEN |
|
627 | 613 | dma_send <= '1'; |
|
628 | 614 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
629 | 615 | dma_sel_valid <= data_f3_data_out_valid; |
|
630 | 616 | ELSIF dma_rr_grant(4) = '1' THEN |
|
631 | 617 | dma_send <= '1'; |
|
632 | 618 | dma_valid_burst <= data_ms_valid_burst; |
|
633 | 619 | dma_sel_valid <= data_ms_valid; |
|
634 | 620 | END IF; |
|
635 | 621 | |
|
636 | 622 | IF dma_sel(4) = '1' THEN |
|
637 | 623 | data_ms_done <= '1'; |
|
638 | 624 | END IF; |
|
639 | 625 | ELSE |
|
640 | 626 | dma_sel <= dma_sel; |
|
641 | 627 | dma_send <= '0'; |
|
642 | 628 | END IF; |
|
643 | 629 | ELSE |
|
644 | 630 | data_ms_done <= '0'; |
|
645 | 631 | dma_sel <= (OTHERS => '0'); |
|
646 | 632 | dma_send <= '0'; |
|
647 | 633 | dma_valid_burst <= '0'; |
|
648 | 634 | END IF; |
|
649 | 635 | END IF; |
|
650 | 636 | END PROCESS; |
|
651 | 637 | |
|
652 | 638 | |
|
653 | 639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
654 | 640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
655 | 641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
656 | 642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
657 | 643 | data_ms_addr; |
|
658 | 644 | |
|
659 | 645 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
660 | 646 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
661 | 647 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
662 | 648 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
663 | 649 | data_ms_data; |
|
664 | 650 | |
|
665 | 651 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
666 | 652 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
667 | 653 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
668 | 654 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
669 | 655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
670 | 656 | |
|
671 | 657 | dma_data_2 <= dma_data; |
|
672 | 658 | |
|
673 | 659 | |
|
674 | 660 | |
|
675 | 661 | |
|
676 | 662 | |
|
677 | 663 | ----------------------------------------------------------------------------- |
|
678 | 664 | -- DEBUG -- DMA IN |
|
679 | 665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
680 | 666 | --debug_f0_data_dma_in <= dma_data; |
|
681 | 667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
682 | 668 | --debug_f1_data_dma_in <= dma_data; |
|
683 | 669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
684 | 670 | --debug_f2_data_dma_in <= dma_data; |
|
685 | 671 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
686 | 672 | --debug_f3_data_dma_in <= dma_data; |
|
687 | 673 | ----------------------------------------------------------------------------- |
|
688 | 674 | |
|
689 | 675 | ----------------------------------------------------------------------------- |
|
690 | 676 | -- DMA |
|
691 | 677 | ----------------------------------------------------------------------------- |
|
692 | 678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
693 | 679 | GENERIC MAP ( |
|
694 | 680 | tech => inferred, |
|
695 | 681 | hindex => hindex) |
|
696 | 682 | PORT MAP ( |
|
697 | 683 | HCLK => clk, |
|
698 | 684 | HRESETn => rstn, |
|
699 | 685 | run => run, |
|
700 | 686 | AHB_Master_In => ahbi, |
|
701 | 687 | AHB_Master_Out => ahbo, |
|
702 | 688 | |
|
703 | 689 | send => dma_send, |
|
704 | 690 | valid_burst => dma_valid_burst, |
|
705 | 691 | done => dma_done, |
|
706 | 692 | ren => dma_ren, |
|
707 | 693 | address => dma_address, |
|
708 | 694 | data => dma_data_2); |
|
709 | 695 | |
|
710 | 696 | ----------------------------------------------------------------------------- |
|
711 | 697 | -- Matrix Spectral |
|
712 | 698 | ----------------------------------------------------------------------------- |
|
713 | 699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
714 |
NOT(sample_f0_val) & NOT(sample_f0_val) |
|
|
700 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
|
715 | 701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
716 |
NOT(sample_f1_val) & NOT(sample_f1_val) |
|
|
702 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
|
717 | 703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
718 |
NOT(sample_f3_val) & NOT(sample_f3_val) |
|
|
704 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
|
719 | 705 | |
|
720 | 706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
721 | 707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
722 | 708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
723 | ||
|
709 | ||
|
724 | 710 | ------------------------------------------------------------------------------- |
|
725 | lpp_lfr_ms_1: lpp_lfr_ms | |
|
711 | ||
|
712 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
|
713 | ||
|
714 | ----------------------------------------------------------------------------- | |
|
715 | lpp_lfr_ms_1 : lpp_lfr_ms | |
|
726 | 716 | GENERIC MAP ( |
|
727 |
Mem_use => Mem_use |
|
|
717 | Mem_use => Mem_use) | |
|
728 | 718 | PORT MAP ( |
|
729 | clk => clk, | |
|
730 | rstn => rstn, | |
|
719 | clk => clk, | |
|
720 | rstn => ms_softandhard_rstn, --rstn, | |
|
731 | 721 | |
|
732 |
coarse_time |
|
|
733 |
fine_time |
|
|
734 | ||
|
735 | sample_f0_wen => sample_f0_wen, | |
|
736 | sample_f0_wdata => sample_f0_wdata, | |
|
737 | sample_f1_wen => sample_f1_wen, | |
|
738 | sample_f1_wdata => sample_f1_wdata, | |
|
739 | sample_f3_wen => sample_f3_wen, | |
|
740 | sample_f3_wdata => sample_f3_wdata, | |
|
722 | coarse_time => coarse_time, | |
|
723 | fine_time => fine_time, | |
|
741 | 724 | |
|
742 | dma_addr => data_ms_addr, -- | |
|
743 | dma_data => data_ms_data, -- | |
|
744 | dma_valid => data_ms_valid, -- | |
|
745 | dma_valid_burst => data_ms_valid_burst, -- | |
|
746 | dma_ren => data_ms_ren, -- | |
|
747 | dma_done => data_ms_done, -- | |
|
725 | sample_f0_wen => sample_f0_wen, | |
|
726 | sample_f0_wdata => sample_f0_wdata, | |
|
727 | sample_f1_wen => sample_f1_wen, | |
|
728 | sample_f1_wdata => sample_f1_wdata, | |
|
729 | sample_f3_wen => sample_f3_wen, | |
|
730 | sample_f3_wdata => sample_f3_wdata, | |
|
731 | ||
|
732 | dma_addr => data_ms_addr, -- | |
|
733 | dma_data => data_ms_data, -- | |
|
734 | dma_valid => data_ms_valid, -- | |
|
735 | dma_valid_burst => data_ms_valid_burst, -- | |
|
736 | dma_ren => data_ms_ren, -- | |
|
737 | dma_done => data_ms_done, -- | |
|
748 | 738 | |
|
749 | 739 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
750 | 740 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
751 | 741 | ready_matrix_f1 => ready_matrix_f1, |
|
752 | 742 | ready_matrix_f2 => ready_matrix_f2, |
|
753 | 743 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
754 | 744 | error_bad_component_error => error_bad_component_error, |
|
755 | debug_reg => observation_reg,--debug_reg, | |
|
745 | debug_reg => observation_reg, --debug_reg, | |
|
756 | 746 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
757 | 747 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
758 | 748 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
759 | 749 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
760 | 750 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
761 | 751 | status_error_bad_component_error => status_error_bad_component_error, |
|
762 | 752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
763 | 753 | config_active_interruption_onError => config_active_interruption_onError, |
|
764 | 754 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
765 | 755 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
766 | 756 | addr_matrix_f1 => addr_matrix_f1, |
|
767 |
addr_matrix_f2 => addr_matrix_f2 |
|
|
768 | ||
|
757 | addr_matrix_f2 => addr_matrix_f2, | |
|
758 | ||
|
759 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
760 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
761 | matrix_time_f1 => matrix_time_f1, | |
|
762 | matrix_time_f2 => matrix_time_f2); | |
|
763 | ||
|
769 | 764 | END beh; |
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@@ -1,493 +1,544 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | LIBRARY ieee; | |
|
24 | USE ieee.std_logic_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | LIBRARY grlib; | |
|
27 | USE grlib.amba.ALL; | |
|
28 | USE grlib.stdlib.ALL; | |
|
29 | USE grlib.devices.ALL; | |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_amba.ALL; | |
|
32 | USE lpp.apb_devices_list.ALL; | |
|
33 | USE lpp.lpp_memory.ALL; | |
|
34 | LIBRARY techmap; | |
|
35 | USE techmap.gencomp.ALL; | |
|
36 | ||
|
37 | ENTITY lpp_lfr_apbreg IS | |
|
38 | GENERIC ( | |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
|
42 | delta_vector_size : INTEGER := 20; | |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | ||
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
|
51 | PORT ( | |
|
52 | -- AMBA AHB system signals | |
|
53 | HCLK : IN STD_ULOGIC; | |
|
54 | HRESETn : IN STD_ULOGIC; | |
|
55 | ||
|
56 | -- AMBA APB Slave Interface | |
|
57 | apbi : IN apb_slv_in_type; | |
|
58 | apbo : OUT apb_slv_out_type; | |
|
59 | ||
|
60 | --------------------------------------------------------------------------- | |
|
61 | -- Spectral Matrix Reg | |
|
62 | -- IN | |
|
63 | ready_matrix_f0_0 : IN STD_LOGIC; | |
|
64 |
ready_matrix_f0_ |
|
|
65 | ready_matrix_f1 : IN STD_LOGIC; | |
|
66 |
ready_matrix_f |
|
|
67 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
68 |
error_ |
|
|
69 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
70 | ||
|
71 | -- OUT | |
|
72 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
73 |
status_ready_matrix_f0_ |
|
|
74 |
status_ready_matrix_f1 |
|
|
75 |
status_ready_matrix_f |
|
|
76 |
status_ |
|
|
77 |
status_error_ |
|
|
78 | ||
|
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
|
80 |
config_active_interruption_on |
|
|
81 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
82 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 |
|
|
|
84 |
addr_matrix_f |
|
|
85 | --------------------------------------------------------------------------- | |
|
86 | --------------------------------------------------------------------------- | |
|
87 | -- WaveForm picker Reg | |
|
88 |
|
|
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
|
92 | ||
|
93 | -- OUT | |
|
94 | data_shaping_BW : OUT STD_LOGIC; | |
|
95 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
96 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
97 | data_shaping_R0 : OUT STD_LOGIC; | |
|
98 | data_shaping_R1 : OUT STD_LOGIC; | |
|
99 | ||
|
100 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
101 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
102 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
103 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
104 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
105 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
106 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
107 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
108 | ||
|
109 | enable_f0 : OUT STD_LOGIC; | |
|
110 | enable_f1 : OUT STD_LOGIC; | |
|
111 | enable_f2 : OUT STD_LOGIC; | |
|
112 | enable_f3 : OUT STD_LOGIC; | |
|
113 | ||
|
114 | burst_f0 : OUT STD_LOGIC; | |
|
115 | burst_f1 : OUT STD_LOGIC; | |
|
116 | burst_f2 : OUT STD_LOGIC; | |
|
117 | ||
|
118 |
|
|
|
119 | ||
|
120 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
121 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
122 |
|
|
|
123 |
|
|
|
124 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
125 | --------------------------------------------------------------------------- | |
|
126 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
127 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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128 |
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129 |
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130 |
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131 |
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132 |
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133 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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134 | ||
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135 | --------------------------------------------------------------------------- | |
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136 | ); | |
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137 | ||
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138 | END lpp_lfr_apbreg; | |
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139 | ||
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140 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
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141 | ||
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142 | CONSTANT REVISION : INTEGER := 1; | |
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143 | ||
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144 | CONSTANT pconfig : apb_config_type := ( | |
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145 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
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146 | 1 => apb_iobar(paddr, pmask)); | |
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147 | ||
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148 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
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149 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
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150 | config_active_interruption_onError : STD_LOGIC; | |
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151 | status_ready_matrix_f0_0 : STD_LOGIC; | |
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152 | status_ready_matrix_f0_1 : STD_LOGIC; | |
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153 | status_ready_matrix_f1 : STD_LOGIC; | |
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154 | status_ready_matrix_f2 : STD_LOGIC; | |
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155 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
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156 | status_error_bad_component_error : STD_LOGIC; | |
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157 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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158 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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159 |
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160 |
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161 | END RECORD; | |
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162 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
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163 | ||
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164 | TYPE lpp_WaveformPicker_regs IS RECORD | |
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165 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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166 |
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167 |
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168 | data_shaping_BW : STD_LOGIC; | |
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169 | data_shaping_SP0 : STD_LOGIC; | |
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170 | data_shaping_SP1 : STD_LOGIC; | |
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171 | data_shaping_R0 : STD_LOGIC; | |
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172 | data_shaping_R1 : STD_LOGIC; | |
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173 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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174 |
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175 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
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176 |
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177 |
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178 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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179 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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180 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
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181 | enable_f0 : STD_LOGIC; | |
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182 | enable_f1 : STD_LOGIC; | |
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183 | enable_f2 : STD_LOGIC; | |
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184 |
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185 | burst_f0 : STD_LOGIC; | |
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186 | burst_f1 : STD_LOGIC; | |
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187 |
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188 | run : STD_LOGIC; | |
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189 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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190 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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191 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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192 |
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193 |
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194 | END RECORD; | |
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195 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
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196 | ||
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197 |
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198 | ||
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199 | ----------------------------------------------------------------------------- | |
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200 | -- IRQ | |
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201 | ----------------------------------------------------------------------------- | |
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202 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
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203 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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204 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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205 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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206 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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207 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
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208 | ||
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209 | BEGIN -- beh | |
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210 | ||
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211 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
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212 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
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213 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
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214 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
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215 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
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216 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
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217 | ||
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218 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
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219 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
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220 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
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221 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
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222 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
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223 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
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224 | ||
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225 | ||
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226 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
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227 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
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228 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
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229 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
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230 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
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231 | ||
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232 | delta_snapshot <= reg_wp.delta_snapshot; | |
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233 | delta_f0 <= reg_wp.delta_f0; | |
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234 | delta_f0_2 <= reg_wp.delta_f0_2; | |
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235 | delta_f1 <= reg_wp.delta_f1; | |
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236 | delta_f2 <= reg_wp.delta_f2; | |
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237 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
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238 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
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239 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
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240 | ||
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241 | enable_f0 <= reg_wp.enable_f0; | |
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242 | enable_f1 <= reg_wp.enable_f1; | |
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243 | enable_f2 <= reg_wp.enable_f2; | |
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244 | enable_f3 <= reg_wp.enable_f3; | |
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245 | ||
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246 | burst_f0 <= reg_wp.burst_f0; | |
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247 | burst_f1 <= reg_wp.burst_f1; | |
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248 | burst_f2 <= reg_wp.burst_f2; | |
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249 | ||
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250 | run <= reg_wp.run; | |
|
251 | ||
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252 |
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253 |
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254 |
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255 |
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256 | ||
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257 | start_date <= reg_wp.start_date; | |
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258 | ||
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259 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
|
260 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
|
261 | BEGIN -- PROCESS lpp_dma_top | |
|
262 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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263 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
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264 | reg_sp.config_active_interruption_onError <= '0'; | |
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265 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
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266 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
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267 | reg_sp.status_ready_matrix_f1 <= '0'; | |
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268 | reg_sp.status_ready_matrix_f2 <= '0'; | |
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269 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
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270 | reg_sp.status_error_bad_component_error <= '0'; | |
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271 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
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272 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
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273 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
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274 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
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275 | prdata <= (OTHERS => '0'); | |
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276 | ||
|
277 | apbo.pirq <= (OTHERS => '0'); | |
|
278 | ||
|
279 | status_full_ack <= (OTHERS => '0'); | |
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280 | ||
|
281 | reg_wp.data_shaping_BW <= '0'; | |
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282 | reg_wp.data_shaping_SP0 <= '0'; | |
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283 | reg_wp.data_shaping_SP1 <= '0'; | |
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284 | reg_wp.data_shaping_R0 <= '0'; | |
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285 |
reg_ |
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286 |
reg_ |
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287 |
reg_ |
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288 |
reg_ |
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289 | reg_wp.enable_f3 <= '0'; | |
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290 | reg_wp.burst_f0 <= '0'; | |
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291 |
reg_ |
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292 |
reg_ |
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293 |
reg_ |
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294 |
reg_ |
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295 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
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296 |
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297 |
reg_ |
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298 |
reg_ |
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299 |
reg_ |
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300 |
reg_ |
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301 |
reg_ |
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302 |
reg_ |
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303 |
reg_ |
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304 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
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305 |
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306 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
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307 |
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308 | reg_wp.start_date <= (OTHERS => '0'); | |
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309 | ||
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310 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
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311 | status_full_ack <= (OTHERS => '0'); | |
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312 | ||
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313 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
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314 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
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315 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
316 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
317 | ||
|
318 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
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319 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
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320 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
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321 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
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322 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
323 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
324 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
325 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
326 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
327 | END LOOP all_status; | |
|
328 | ||
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329 | paddr := "000000"; | |
|
330 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
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331 |
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|
|
332 | IF apbi.psel(pindex) = '1' THEN | |
|
333 | -- APB DMA READ -- | |
|
334 | CASE paddr(7 DOWNTO 2) IS | |
|
335 | -- | |
|
336 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
337 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
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338 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
339 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
340 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
341 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
342 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
343 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
344 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
345 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
346 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
347 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
348 | WHEN "000110" => prdata <= debug_reg; | |
|
349 | -- | |
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350 | WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
351 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
352 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
353 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
354 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
355 | WHEN "001001" => prdata(0) <= reg_wp.enable_f0; | |
|
356 | prdata(1) <= reg_wp.enable_f1; | |
|
357 | prdata(2) <= reg_wp.enable_f2; | |
|
358 | prdata(3) <= reg_wp.enable_f3; | |
|
359 | prdata(4) <= reg_wp.burst_f0; | |
|
360 | prdata(5) <= reg_wp.burst_f1; | |
|
361 | prdata(6) <= reg_wp.burst_f2; | |
|
362 | prdata(7) <= reg_wp.run; | |
|
363 | WHEN "001010" => prdata <= reg_wp.addr_data_f0; | |
|
364 | WHEN "001011" => prdata <= reg_wp.addr_data_f1; | |
|
365 | WHEN "001100" => prdata <= reg_wp.addr_data_f2; | |
|
366 | WHEN "001101" => prdata <= reg_wp.addr_data_f3; | |
|
367 | WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
368 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
369 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
370 | WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
371 | WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
372 | WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
373 | WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
374 | WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
375 | WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
376 | WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
377 | WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
378 | WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
379 | ---------------------------------------------------- | |
|
380 |
WHEN " |
|
|
381 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
382 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
383 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
384 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
385 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
386 |
WHEN " |
|
|
387 |
WHEN " |
|
|
388 | ---------------------------------------------------- | |
|
389 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
390 | WHEN OTHERS => NULL; | |
|
391 | END CASE; | |
|
392 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
393 | -- APB DMA WRITE -- | |
|
394 | CASE paddr(7 DOWNTO 2) IS | |
|
395 | -- | |
|
396 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
397 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
398 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
399 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
400 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
401 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
402 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
403 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
404 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
405 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
406 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
407 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
408 |
|
|
|
409 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
|
414 | WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
415 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
416 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
417 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
418 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
419 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
420 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
421 | reg_wp.run <= apbi.pwdata(7); | |
|
422 | WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
423 | WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
424 | WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
425 | WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
426 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
427 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
428 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
429 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
430 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
431 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
432 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
433 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
434 | WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
435 | WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
436 | WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
437 | WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
438 | WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
439 | WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
440 | WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
441 | WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
442 | -- | |
|
443 | WHEN OTHERS => NULL; | |
|
444 |
|
|
|
445 | END IF; | |
|
446 | END IF; | |
|
447 | ||
|
448 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
449 | ready_matrix_f0_1 OR | |
|
450 | ready_matrix_f1 OR | |
|
451 | ready_matrix_f2) | |
|
452 | ) | |
|
453 | OR | |
|
454 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
455 | error_bad_component_error) | |
|
456 | )); | |
|
457 | ||
|
458 | --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR | |
|
459 | -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR | |
|
460 | -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR | |
|
461 | -- status_full(3) OR status_full_err(3) OR status_new_err(3) | |
|
462 |
|
|
|
463 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
464 | ||
|
465 | END IF; | |
|
466 | END PROCESS lpp_lfr_apbreg; | |
|
467 | ||
|
468 | apbo.pindex <= pindex; | |
|
469 | apbo.pconfig <= pconfig; | |
|
470 | apbo.prdata <= prdata; | |
|
471 | ||
|
472 | ----------------------------------------------------------------------------- | |
|
473 | -- IRQ | |
|
474 | ----------------------------------------------------------------------------- | |
|
475 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
476 | ||
|
477 | PROCESS (HCLK, HRESETn) | |
|
478 | BEGIN -- PROCESS | |
|
479 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
480 | irq_wfp_reg <= (OTHERS => '0'); | |
|
481 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
482 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
483 | END IF; | |
|
484 | END PROCESS; | |
|
485 | ||
|
486 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
487 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
488 | END GENERATE all_irq_wfp; | |
|
489 | ||
|
490 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
491 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
492 | ||
|
493 | END beh; | |
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | LIBRARY ieee; | |
|
24 | USE ieee.std_logic_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | LIBRARY grlib; | |
|
27 | USE grlib.amba.ALL; | |
|
28 | USE grlib.stdlib.ALL; | |
|
29 | USE grlib.devices.ALL; | |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_amba.ALL; | |
|
32 | USE lpp.apb_devices_list.ALL; | |
|
33 | USE lpp.lpp_memory.ALL; | |
|
34 | LIBRARY techmap; | |
|
35 | USE techmap.gencomp.ALL; | |
|
36 | ||
|
37 | ENTITY lpp_lfr_apbreg IS | |
|
38 | GENERIC ( | |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
|
42 | delta_vector_size : INTEGER := 20; | |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | ||
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
|
51 | PORT ( | |
|
52 | -- AMBA AHB system signals | |
|
53 | HCLK : IN STD_ULOGIC; | |
|
54 | HRESETn : IN STD_ULOGIC; | |
|
55 | ||
|
56 | -- AMBA APB Slave Interface | |
|
57 | apbi : IN apb_slv_in_type; | |
|
58 | apbo : OUT apb_slv_out_type; | |
|
59 | ||
|
60 | --------------------------------------------------------------------------- | |
|
61 | -- Spectral Matrix Reg | |
|
62 | run_ms : OUT STD_LOGIC; | |
|
63 | -- IN | |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- OUT | |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
|
82 | ||
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
92 | ||
|
93 | --------------------------------------------------------------------------- | |
|
94 | --------------------------------------------------------------------------- | |
|
95 | -- WaveForm picker Reg | |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | ||
|
101 | -- OUT | |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
|
107 | ||
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
116 | ||
|
117 | enable_f0 : OUT STD_LOGIC; | |
|
118 | enable_f1 : OUT STD_LOGIC; | |
|
119 | enable_f2 : OUT STD_LOGIC; | |
|
120 | enable_f3 : OUT STD_LOGIC; | |
|
121 | ||
|
122 | burst_f0 : OUT STD_LOGIC; | |
|
123 | burst_f1 : OUT STD_LOGIC; | |
|
124 | burst_f2 : OUT STD_LOGIC; | |
|
125 | ||
|
126 | run : OUT STD_LOGIC; | |
|
127 | ||
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
133 | --------------------------------------------------------------------------- | |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
142 | ||
|
143 | --------------------------------------------------------------------------- | |
|
144 | ); | |
|
145 | ||
|
146 | END lpp_lfr_apbreg; | |
|
147 | ||
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
|
149 | ||
|
150 | CONSTANT REVISION : INTEGER := 1; | |
|
151 | ||
|
152 | CONSTANT pconfig : apb_config_type := ( | |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
|
155 | ||
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
|
159 | config_ms_run : STD_LOGIC; | |
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
170 | ||
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | ||
|
176 | fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
177 | fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
178 | fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | END RECORD; | |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
|
182 | ||
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
187 | data_shaping_BW : STD_LOGIC; | |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
|
190 | data_shaping_R0 : STD_LOGIC; | |
|
191 | data_shaping_R1 : STD_LOGIC; | |
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
200 | enable_f0 : STD_LOGIC; | |
|
201 | enable_f1 : STD_LOGIC; | |
|
202 | enable_f2 : STD_LOGIC; | |
|
203 | enable_f3 : STD_LOGIC; | |
|
204 | burst_f0 : STD_LOGIC; | |
|
205 | burst_f1 : STD_LOGIC; | |
|
206 | burst_f2 : STD_LOGIC; | |
|
207 | run : STD_LOGIC; | |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
213 | END RECORD; | |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
|
215 | ||
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | ||
|
218 | ----------------------------------------------------------------------------- | |
|
219 | -- IRQ | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
227 | ||
|
228 | BEGIN -- beh | |
|
229 | ||
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
236 | ||
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
243 | ||
|
244 | ||
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
|
250 | ||
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
252 | delta_f0 <= reg_wp.delta_f0; | |
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
254 | delta_f1 <= reg_wp.delta_f1; | |
|
255 | delta_f2 <= reg_wp.delta_f2; | |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
259 | ||
|
260 | enable_f0 <= reg_wp.enable_f0; | |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
|
264 | ||
|
265 | burst_f0 <= reg_wp.burst_f0; | |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
|
268 | ||
|
269 | run <= reg_wp.run; | |
|
270 | ||
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
|
275 | ||
|
276 | start_date <= reg_wp.start_date; | |
|
277 | ||
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
|
280 | BEGIN -- PROCESS lpp_dma_top | |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
|
284 | reg_sp.config_ms_run <= '1'; | |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
295 | ||
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
300 | reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
|
301 | reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
|
302 | reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
|
303 | reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
304 | ||
|
305 | prdata <= (OTHERS => '0'); | |
|
306 | ||
|
307 | apbo.pirq <= (OTHERS => '0'); | |
|
308 | ||
|
309 | status_full_ack <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_wp.data_shaping_BW <= '0'; | |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
|
316 | reg_wp.enable_f0 <= '0'; | |
|
317 | reg_wp.enable_f1 <= '0'; | |
|
318 | reg_wp.enable_f2 <= '0'; | |
|
319 | reg_wp.enable_f3 <= '0'; | |
|
320 | reg_wp.burst_f0 <= '0'; | |
|
321 | reg_wp.burst_f1 <= '0'; | |
|
322 | reg_wp.burst_f2 <= '0'; | |
|
323 | reg_wp.run <= '0'; | |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
|
339 | ||
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
346 | ||
|
347 | reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
348 | reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
349 | reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
350 | reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
351 | ||
|
352 | status_full_ack <= (OTHERS => '0'); | |
|
353 | ||
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
358 | ||
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
368 | END LOOP all_status; | |
|
369 | ||
|
370 | paddr := "000000"; | |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
|
372 | prdata <= (OTHERS => '0'); | |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
|
374 | -- APB DMA READ -- | |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
|
376 | -- | |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
390 | ||
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
|
395 | WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0; | |
|
396 | WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1; | |
|
397 | WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1; | |
|
398 | WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2; | |
|
399 | ||
|
400 | WHEN "001111" => prdata <= debug_reg; | |
|
401 | --------------------------------------------------------------------- | |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
|
414 | prdata(7) <= reg_wp.run; | |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
431 | ---------------------------------------------------- | |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
|
440 | ---------------------------------------------------- | |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||
|
444 | END CASE; | |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
446 | -- APB DMA WRITE -- | |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
|
448 | -- | |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
462 | -- | |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
496 | -- | |
|
497 | WHEN OTHERS => NULL; | |
|
498 | END CASE; | |
|
499 | END IF; | |
|
500 | END IF; | |
|
501 | ||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
503 | ready_matrix_f0_1 OR | |
|
504 | ready_matrix_f1 OR | |
|
505 | ready_matrix_f2) | |
|
506 | ) | |
|
507 | OR | |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
509 | error_bad_component_error) | |
|
510 | )); | |
|
511 | ||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
513 | ||
|
514 | END IF; | |
|
515 | END PROCESS lpp_lfr_apbreg; | |
|
516 | ||
|
517 | apbo.pindex <= pindex; | |
|
518 | apbo.pconfig <= pconfig; | |
|
519 | apbo.prdata <= prdata; | |
|
520 | ||
|
521 | ----------------------------------------------------------------------------- | |
|
522 | -- IRQ | |
|
523 | ----------------------------------------------------------------------------- | |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
525 | ||
|
526 | PROCESS (HCLK, HRESETn) | |
|
527 | BEGIN -- PROCESS | |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
532 | END IF; | |
|
533 | END PROCESS; | |
|
534 | ||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
537 | END GENERATE all_irq_wfp; | |
|
538 | ||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
541 | ||
|
542 | run_ms <= reg_sp.config_ms_run; | |
|
543 | ||
|
544 | END beh; |
@@ -1,402 +1,414 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY lpp; |
|
5 | 5 | USE lpp.lpp_amba.ALL; |
|
6 | 6 | USE lpp.lpp_memory.ALL; |
|
7 | 7 | --USE lpp.lpp_uart.ALL; |
|
8 | 8 | USE lpp.lpp_matrix.ALL; |
|
9 | 9 | --USE lpp.lpp_delay.ALL; |
|
10 | 10 | USE lpp.lpp_fft.ALL; |
|
11 | 11 | USE lpp.fft_components.ALL; |
|
12 | 12 | USE lpp.lpp_ad_conv.ALL; |
|
13 | 13 | USE lpp.iir_filter.ALL; |
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | USE lpp.Filtercfg.ALL; |
|
16 | 16 | USE lpp.lpp_demux.ALL; |
|
17 | 17 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
18 | 18 | USE lpp.lpp_dma_pkg.ALL; |
|
19 | 19 | USE lpp.lpp_Header.ALL; |
|
20 | 20 | USE lpp.lpp_lfr_pkg.ALL; |
|
21 | 21 | |
|
22 | 22 | LIBRARY grlib; |
|
23 | 23 | USE grlib.amba.ALL; |
|
24 | 24 | USE grlib.stdlib.ALL; |
|
25 | 25 | USE grlib.devices.ALL; |
|
26 | 26 | USE GRLIB.DMA2AHB_Package.ALL; |
|
27 | 27 | |
|
28 | 28 | |
|
29 | 29 | ENTITY lpp_lfr_ms IS |
|
30 | 30 | GENERIC ( |
|
31 | 31 | Mem_use : INTEGER |
|
32 | 32 | ); |
|
33 | 33 | PORT ( |
|
34 | 34 | clk : IN STD_LOGIC; |
|
35 | 35 | rstn : IN STD_LOGIC; |
|
36 | 36 | |
|
37 | 37 | --------------------------------------------------------------------------- |
|
38 | 38 | -- DATA INPUT |
|
39 | 39 | --------------------------------------------------------------------------- |
|
40 | 40 | -- TIME |
|
41 | 41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
42 | 42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
43 | 43 | -- |
|
44 | 44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
45 | 45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
46 | 46 | -- |
|
47 | 47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 49 | -- |
|
50 | 50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
51 | 51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
52 | 52 | |
|
53 | 53 | --------------------------------------------------------------------------- |
|
54 | 54 | -- DMA |
|
55 | 55 | --------------------------------------------------------------------------- |
|
56 | 56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | 57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | 58 | dma_valid : OUT STD_LOGIC; |
|
59 | 59 | dma_valid_burst : OUT STD_LOGIC; |
|
60 | 60 | dma_ren : IN STD_LOGIC; |
|
61 | 61 | dma_done : IN STD_LOGIC; |
|
62 | 62 | |
|
63 | 63 | -- Reg out |
|
64 | 64 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
65 | 65 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
66 | 66 | ready_matrix_f1 : OUT STD_LOGIC; |
|
67 | 67 | ready_matrix_f2 : OUT STD_LOGIC; |
|
68 | 68 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
69 | 69 | error_bad_component_error : OUT STD_LOGIC; |
|
70 | 70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | 71 | |
|
72 | 72 | -- Reg In |
|
73 | 73 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
74 | 74 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
75 | 75 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
76 | 76 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
77 | 77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
78 | 78 | status_error_bad_component_error :IN STD_LOGIC; |
|
79 | 79 | |
|
80 | 80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
81 | 81 | config_active_interruption_onError : IN STD_LOGIC; |
|
82 | 82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | 83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
91 | ||
|
86 | 92 | ); |
|
87 | 93 | END; |
|
88 | 94 | |
|
89 | 95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
90 | 96 | ----------------------------------------------------------------------------- |
|
91 | 97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | 98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
93 | 99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | 100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
95 | 101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
96 | 102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
97 | 103 | |
|
98 | 104 | ----------------------------------------------------------------------------- |
|
99 | 105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); |
|
100 | 106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
101 | 107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
102 | 108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
103 | 109 | |
|
104 | 110 | ----------------------------------------------------------------------------- |
|
105 | 111 | SIGNAL FFT_Load : STD_LOGIC; |
|
106 | 112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
107 | 113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
108 | 114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | 115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
110 | 116 | |
|
111 | 117 | ----------------------------------------------------------------------------- |
|
112 | 118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
113 | 119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
114 | 120 | |
|
115 | 121 | ----------------------------------------------------------------------------- |
|
116 | 122 | SIGNAL SM_FlagError : STD_LOGIC; |
|
117 | 123 | -- SIGNAL SM_Pong : STD_LOGIC; |
|
118 | 124 | SIGNAL SM_Wen : STD_LOGIC; |
|
119 | 125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
120 | 126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
121 | 127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
122 | 128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
123 | 129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
124 | 130 | |
|
125 | 131 | ----------------------------------------------------------------------------- |
|
126 | 132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
127 | 133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
128 | 134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
129 | 135 | |
|
130 | 136 | ----------------------------------------------------------------------------- |
|
131 | 137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
132 | 138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 139 | SIGNAL Head_Empty : STD_LOGIC; |
|
134 | 140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
135 | 141 | SIGNAL Head_Valid : STD_LOGIC; |
|
136 | 142 | SIGNAL Head_Val : STD_LOGIC; |
|
137 | 143 | |
|
138 | 144 | ----------------------------------------------------------------------------- |
|
139 | 145 | SIGNAL DMA_Read : STD_LOGIC; |
|
140 | 146 | SIGNAL DMA_ack : STD_LOGIC; |
|
141 | 147 | |
|
142 | 148 | ----------------------------------------------------------------------------- |
|
143 | 149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
144 | 150 | |
|
145 | 151 | BEGIN |
|
146 | 152 | |
|
147 | 153 | ----------------------------------------------------------------------------- |
|
148 | 154 | Memf0: lppFIFOxN |
|
149 | 155 | GENERIC MAP ( |
|
150 | 156 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
151 | 157 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
|
152 | 158 | PORT MAP ( |
|
153 | 159 | rstn => rstn, wclk => clk, rclk => clk, |
|
154 | 160 | ReUse => (OTHERS => '0'), |
|
155 | 161 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), |
|
156 | 162 | wdata => sample_f0_wdata, rdata => FifoF0_Data, |
|
157 | 163 | full => OPEN, empty => FifoF0_Empty); |
|
158 | 164 | |
|
159 | 165 | Memf1: lppFIFOxN |
|
160 | 166 | GENERIC MAP ( |
|
161 | 167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
162 | 168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
163 | 169 | PORT MAP ( |
|
164 | 170 | rstn => rstn, wclk => clk, rclk => clk, |
|
165 | 171 | ReUse => (OTHERS => '0'), |
|
166 | 172 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), |
|
167 | 173 | wdata => sample_f1_wdata, rdata => FifoF1_Data, |
|
168 | 174 | full => OPEN, empty => FifoF1_Empty); |
|
169 | 175 | |
|
170 | 176 | |
|
171 | 177 | Memf2: lppFIFOxN |
|
172 | 178 | GENERIC MAP ( |
|
173 | 179 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
|
174 | 180 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
175 | 181 | PORT MAP ( |
|
176 | 182 | rstn => rstn, wclk => clk, rclk => clk, |
|
177 | 183 | ReUse => (OTHERS => '0'), |
|
178 | 184 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), |
|
179 | 185 | wdata => sample_f3_wdata, rdata => FifoF3_Data, |
|
180 | 186 | full => OPEN, empty => FifoF3_Empty); |
|
181 | 187 | ----------------------------------------------------------------------------- |
|
182 | 188 | |
|
183 | 189 | |
|
184 | 190 | ----------------------------------------------------------------------------- |
|
185 | 191 | DMUX0 : DEMUX |
|
186 | 192 | GENERIC MAP ( |
|
187 | 193 | Data_sz => 16) |
|
188 | 194 | PORT MAP ( |
|
189 | 195 | clk => clk, |
|
190 | 196 | rstn => rstn, |
|
191 | 197 | Read => FFT_Read, |
|
192 | 198 | Load => FFT_Load, |
|
193 | 199 | EmptyF0 => FifoF0_Empty, |
|
194 | 200 | EmptyF1 => FifoF1_Empty, |
|
195 | 201 | EmptyF2 => FifoF3_Empty, |
|
196 | 202 | DataF0 => FifoF0_Data, |
|
197 | 203 | DataF1 => FifoF1_Data, |
|
198 | 204 | DataF2 => FifoF3_Data, |
|
199 | 205 | WorkFreq => DMUX_WorkFreq, |
|
200 | 206 | Read_DEMUX => DMUX_Read, |
|
201 | 207 | Empty => DMUX_Empty, |
|
202 | 208 | Data => DMUX_Data); |
|
203 | 209 | ----------------------------------------------------------------------------- |
|
204 | 210 | |
|
205 | 211 | |
|
206 | 212 | ----------------------------------------------------------------------------- |
|
207 | 213 | FFT0: FFT |
|
208 | 214 | GENERIC MAP ( |
|
209 | 215 | Data_sz => 16, |
|
210 | 216 | NbData => 256) |
|
211 | 217 | PORT MAP ( |
|
212 | 218 | clkm => clk, |
|
213 | 219 | rstn => rstn, |
|
214 | 220 | FifoIN_Empty => DMUX_Empty, |
|
215 | 221 | FifoIN_Data => DMUX_Data, |
|
216 | 222 | FifoOUT_Full => FifoINT_Full, |
|
217 | 223 | Load => FFT_Load, |
|
218 | 224 | Read => FFT_Read, |
|
219 | 225 | Write => FFT_Write, |
|
220 | 226 | ReUse => FFT_ReUse, |
|
221 | 227 | Data => FFT_Data); |
|
222 | 228 | ----------------------------------------------------------------------------- |
|
223 | 229 | |
|
224 | 230 | |
|
225 | 231 | ----------------------------------------------------------------------------- |
|
226 | 232 | MemInt : lppFIFOxN |
|
227 | 233 | GENERIC MAP ( |
|
228 | 234 | tech => 0, |
|
229 | 235 | Mem_use => Mem_use, |
|
230 | 236 | Data_sz => 16, |
|
231 | 237 | Addr_sz => 8, |
|
232 | 238 | FifoCnt => 5, |
|
233 | 239 | Enable_ReUse => '1') |
|
234 | 240 | PORT MAP ( |
|
235 | 241 | rstn => rstn, |
|
236 | 242 | wclk => clk, |
|
237 | 243 | rclk => clk, |
|
238 | 244 | ReUse => SM_ReUse, |
|
239 | 245 | wen => FFT_Write, |
|
240 | 246 | ren => SM_Read, |
|
241 | 247 | wdata => FFT_Data, |
|
242 | 248 | rdata => FifoINT_Data, |
|
243 | 249 | full => FifoINT_Full, |
|
244 | 250 | empty => OPEN); |
|
245 | 251 | ----------------------------------------------------------------------------- |
|
246 | 252 | |
|
247 | 253 | ----------------------------------------------------------------------------- |
|
248 | 254 | SM0 : MatriceSpectrale |
|
249 | 255 | GENERIC MAP ( |
|
250 | 256 | Input_SZ => 16, |
|
251 | 257 | Result_SZ => 32) |
|
252 | 258 | PORT MAP ( |
|
253 | 259 | clkm => clk, |
|
254 | 260 | rstn => rstn, |
|
255 | 261 | FifoIN_Full => FifoINT_Full, |
|
256 | 262 | SetReUse => FFT_ReUse, |
|
257 | 263 | Valid => Head_Valid, |
|
258 | 264 | Data_IN => FifoINT_Data, |
|
259 | 265 | ACK => DMA_ack, |
|
260 | 266 | SM_Write => SM_Wen, |
|
261 | 267 | FlagError => SM_FlagError, |
|
262 | 268 | -- Pong => SM_Pong, |
|
263 | 269 | Statu => SM_Param, |
|
264 | 270 | Write => SM_Write, |
|
265 | 271 | Read => SM_Read, |
|
266 | 272 | ReUse => SM_ReUse, |
|
267 | 273 | Data_OUT => SM_Data); |
|
268 | 274 | ----------------------------------------------------------------------------- |
|
269 | 275 | |
|
270 | 276 | ----------------------------------------------------------------------------- |
|
271 | 277 | MemOut : lppFIFOxN |
|
272 | 278 | GENERIC MAP ( |
|
273 | 279 | tech => 0, |
|
274 | 280 | Mem_use => Mem_use, |
|
275 | 281 | Data_sz => 32, |
|
276 | 282 | Addr_sz => 8, |
|
277 | 283 | FifoCnt => 2, |
|
278 | 284 | Enable_ReUse => '0') |
|
279 | 285 | PORT MAP ( |
|
280 | 286 | rstn => rstn, |
|
281 | 287 | wclk => clk, |
|
282 | 288 | rclk => clk, |
|
283 | 289 | ReUse => (OTHERS => '0'), |
|
284 | 290 | wen => SM_Write, |
|
285 | 291 | ren => Head_Read, |
|
286 | 292 | wdata => SM_Data, |
|
287 | 293 | rdata => FifoOUT_Data, |
|
288 | 294 | full => FifoOUT_Full, |
|
289 | 295 | empty => FifoOUT_Empty); |
|
290 | 296 | ----------------------------------------------------------------------------- |
|
291 | 297 | |
|
292 | 298 | ----------------------------------------------------------------------------- |
|
293 | 299 | Head0 : HeaderBuilder |
|
294 | 300 | GENERIC MAP ( |
|
295 | 301 | Data_sz => 32) |
|
296 | 302 | PORT MAP ( |
|
297 | 303 | clkm => clk, |
|
298 | 304 | rstn => rstn, |
|
299 | 305 | -- pong => SM_Pong, |
|
300 | 306 | Statu => SM_Param, |
|
301 | 307 | Matrix_Type => DMUX_WorkFreq, |
|
302 | 308 | Matrix_Write => SM_Wen, |
|
303 | 309 | Valid => Head_Valid, |
|
304 | 310 | dataIN => FifoOUT_Data, |
|
305 | 311 | emptyIN => FifoOUT_Empty, |
|
306 | 312 | RenOUT => Head_Read, |
|
307 | 313 | dataOUT => Head_Data, |
|
308 | 314 | emptyOUT => Head_Empty, |
|
309 | 315 | RenIN => DMA_Read, |
|
310 | 316 | header => Head_Header, |
|
311 | 317 | header_val => Head_Val, |
|
312 | 318 | header_ack => DMA_ack ); |
|
313 | 319 | ----------------------------------------------------------------------------- |
|
314 | 320 | data_time(31 DOWNTO 0) <= coarse_time; |
|
315 | 321 | data_time(47 DOWNTO 32) <= fine_time; |
|
316 | 322 | |
|
317 | 323 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
318 | 324 | PORT MAP ( |
|
319 | 325 | HCLK => clk, |
|
320 | 326 | HRESETn => rstn, |
|
321 | 327 | |
|
322 | 328 | data_time => data_time, |
|
323 | 329 | |
|
324 | 330 | fifo_data => Head_Data, |
|
325 | 331 | fifo_empty => Head_Empty, |
|
326 | 332 | fifo_ren => DMA_Read, |
|
327 | 333 | |
|
328 | 334 | header => Head_Header, |
|
329 | 335 | header_val => Head_Val, |
|
330 | 336 | header_ack => DMA_ack, |
|
331 | 337 | |
|
332 | 338 | dma_addr => dma_addr, |
|
333 | 339 | dma_data => dma_data, |
|
334 | 340 | dma_valid => dma_valid, |
|
335 | 341 | dma_valid_burst => dma_valid_burst, |
|
336 | 342 | dma_ren => dma_ren, |
|
337 | 343 | dma_done => dma_done, |
|
338 | 344 | |
|
339 | 345 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
340 | 346 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
341 | 347 | ready_matrix_f1 => ready_matrix_f1, |
|
342 | 348 | ready_matrix_f2 => ready_matrix_f2, |
|
343 | 349 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
344 | 350 | error_bad_component_error => error_bad_component_error, |
|
345 | 351 | debug_reg => debug_reg, |
|
346 | 352 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
347 | 353 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
348 | 354 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
349 | 355 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
350 | 356 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
351 | 357 | status_error_bad_component_error => status_error_bad_component_error, |
|
352 | 358 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
353 | 359 | config_active_interruption_onError => config_active_interruption_onError, |
|
354 | 360 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
355 | 361 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
356 | 362 | addr_matrix_f1 => addr_matrix_f1, |
|
357 |
addr_matrix_f2 => addr_matrix_f2 |
|
|
363 | addr_matrix_f2 => addr_matrix_f2, | |
|
364 | ||
|
365 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
366 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
367 | matrix_time_f1 => matrix_time_f1, | |
|
368 | matrix_time_f2 => matrix_time_f2 | |
|
369 | ); | |
|
358 | 370 | |
|
359 | 371 | |
|
360 | 372 | |
|
361 | 373 | |
|
362 | 374 | ----------------------------------------------------------------------------- |
|
363 | 375 | --lpp_dma_ip_1: lpp_dma_ip |
|
364 | 376 | -- GENERIC MAP ( |
|
365 | 377 | -- tech => 0, |
|
366 | 378 | -- hindex => hindex) |
|
367 | 379 | -- PORT MAP ( |
|
368 | 380 | -- HCLK => clk, |
|
369 | 381 | -- HRESETn => rstn, |
|
370 | 382 | -- AHB_Master_In => AHB_Master_In, |
|
371 | 383 | -- AHB_Master_Out => AHB_Master_Out, |
|
372 | 384 | |
|
373 | 385 | -- fifo_data => Head_Data, |
|
374 | 386 | -- fifo_empty => Head_Empty, |
|
375 | 387 | -- fifo_ren => DMA_Read, |
|
376 | 388 | |
|
377 | 389 | -- header => Head_Header, |
|
378 | 390 | -- header_val => Head_Val, |
|
379 | 391 | -- header_ack => DMA_ack, |
|
380 | 392 | |
|
381 | 393 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
|
382 | 394 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
383 | 395 | -- ready_matrix_f1 => ready_matrix_f1, |
|
384 | 396 | -- ready_matrix_f2 => ready_matrix_f2, |
|
385 | 397 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
386 | 398 | -- error_bad_component_error => error_bad_component_error, |
|
387 | 399 | -- debug_reg => debug_reg, |
|
388 | 400 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
389 | 401 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
390 | 402 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
|
391 | 403 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
|
392 | 404 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
393 | 405 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
394 | 406 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
395 | 407 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
396 | 408 | -- addr_matrix_f0_0 => addr_matrix_f0_0, |
|
397 | 409 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
398 | 410 | -- addr_matrix_f1 => addr_matrix_f1, |
|
399 | 411 | -- addr_matrix_f2 => addr_matrix_f2); |
|
400 | 412 | ------------------------------------------------------------------------------- |
|
401 | 413 | |
|
402 | 414 | END Behavioral; |
@@ -1,365 +1,383 | |||
|
1 | 1 | |
|
2 | 2 | ------------------------------------------------------------------------------ |
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
5 | 5 | -- |
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
9 | 9 | -- (at your option) any later version. |
|
10 | 10 | -- |
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 | 14 | -- GNU General Public License for more details. |
|
15 | 15 | -- |
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 | 19 | ------------------------------------------------------------------------------- |
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
23 | 23 | ------------------------------------------------------------------------------- |
|
24 | 24 | -- 1.0 - initial version |
|
25 | 25 | ------------------------------------------------------------------------------- |
|
26 | 26 | LIBRARY ieee; |
|
27 | 27 | USE ieee.std_logic_1164.ALL; |
|
28 | 28 | USE ieee.numeric_std.ALL; |
|
29 | 29 | LIBRARY grlib; |
|
30 | 30 | USE grlib.amba.ALL; |
|
31 | 31 | USE grlib.stdlib.ALL; |
|
32 | 32 | USE grlib.devices.ALL; |
|
33 | 33 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | 34 | LIBRARY lpp; |
|
35 | 35 | USE lpp.lpp_amba.ALL; |
|
36 | 36 | USE lpp.apb_devices_list.ALL; |
|
37 | 37 | USE lpp.lpp_memory.ALL; |
|
38 | 38 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | 39 | LIBRARY techmap; |
|
40 | 40 | USE techmap.gencomp.ALL; |
|
41 | 41 | |
|
42 | 42 | |
|
43 | 43 | ENTITY lpp_lfr_ms_fsmdma IS |
|
44 | 44 | PORT ( |
|
45 | 45 | -- AMBA AHB system signals |
|
46 | 46 | HCLK : IN STD_ULOGIC; |
|
47 | 47 | HRESETn : IN STD_ULOGIC; |
|
48 | 48 | |
|
49 | 49 | --TIME |
|
50 | 50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- fifo interface |
|
53 | 53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
54 | 54 | fifo_empty : IN STD_LOGIC; |
|
55 | 55 | fifo_ren : OUT STD_LOGIC; |
|
56 | 56 | |
|
57 | 57 | -- header |
|
58 | 58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | 59 | header_val : IN STD_LOGIC; |
|
60 | 60 | header_ack : OUT STD_LOGIC; |
|
61 | 61 | |
|
62 | 62 | -- DMA |
|
63 | 63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | 65 | dma_valid : OUT STD_LOGIC; |
|
66 | 66 | dma_valid_burst : OUT STD_LOGIC; |
|
67 | 67 | dma_ren : IN STD_LOGIC; |
|
68 | 68 | dma_done : IN STD_LOGIC; |
|
69 | 69 | |
|
70 | 70 | -- Reg out |
|
71 | 71 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
72 | 72 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
73 | 73 | ready_matrix_f1 : OUT STD_LOGIC; |
|
74 | 74 | ready_matrix_f2 : OUT STD_LOGIC; |
|
75 | 75 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
76 | 76 | error_bad_component_error : OUT STD_LOGIC; |
|
77 | 77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 78 | |
|
79 | 79 | -- Reg In |
|
80 | 80 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
81 | 81 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
82 | 82 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
83 | 83 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
84 | 84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
85 | 85 | status_error_bad_component_error : IN STD_LOGIC; |
|
86 | 86 | |
|
87 | 87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
88 | 88 | config_active_interruption_onError : IN STD_LOGIC; |
|
89 | 89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
93 | ||
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
93 | 98 | |
|
94 | 99 | ); |
|
95 | 100 | END; |
|
96 | 101 | |
|
97 | 102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
98 | 103 | ----------------------------------------------------------------------------- |
|
99 | 104 | -- SIGNAL DMAIn : DMA_In_Type; |
|
100 | 105 | -- SIGNAL header_dmai : DMA_In_Type; |
|
101 | 106 | -- SIGNAL component_dmai : DMA_In_Type; |
|
102 | 107 | -- SIGNAL DMAOut : DMA_OUt_Type; |
|
103 | 108 | ----------------------------------------------------------------------------- |
|
104 | 109 | |
|
105 | 110 | ----------------------------------------------------------------------------- |
|
106 | 111 | ----------------------------------------------------------------------------- |
|
107 | 112 | TYPE state_DMAWriteBurst IS (IDLE, |
|
108 | 113 | CHECK_COMPONENT_TYPE, |
|
109 | 114 | WRITE_COARSE_TIME, |
|
110 | 115 | WRITE_FINE_TIME, |
|
111 | 116 | TRASH_FIFO, |
|
112 | 117 | SEND_DATA, |
|
113 | 118 | WAIT_DATA_ACK, |
|
114 | 119 | CHECK_LENGTH |
|
115 | 120 | ); |
|
116 | 121 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
|
117 | 122 | |
|
118 | 123 | -- SIGNAL nbSend : INTEGER; |
|
119 | 124 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
120 | 125 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
121 | 126 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
122 | 127 | SIGNAL header_check_ok : STD_LOGIC; |
|
123 | 128 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
124 | 129 | SIGNAL send_matrix : STD_LOGIC; |
|
125 | 130 | -- SIGNAL request : STD_LOGIC; |
|
126 | 131 | -- SIGNAL remaining_data_request : INTEGER; |
|
127 | 132 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | 133 | ----------------------------------------------------------------------------- |
|
129 | 134 | ----------------------------------------------------------------------------- |
|
130 | 135 | SIGNAL header_select : STD_LOGIC; |
|
131 | 136 | |
|
132 | 137 | SIGNAL header_send : STD_LOGIC; |
|
133 | 138 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | 139 | SIGNAL header_send_ok : STD_LOGIC; |
|
135 | 140 | SIGNAL header_send_ko : STD_LOGIC; |
|
136 | 141 | |
|
137 | 142 | SIGNAL component_send : STD_LOGIC; |
|
138 | 143 | SIGNAL component_send_ok : STD_LOGIC; |
|
139 | 144 | SIGNAL component_send_ko : STD_LOGIC; |
|
140 | 145 | ----------------------------------------------------------------------------- |
|
141 | 146 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
142 | 147 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
143 | 148 | |
|
144 | 149 | ----------------------------------------------------------------------------- |
|
145 | 150 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | 151 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
147 | 152 | |
|
148 | 153 | BEGIN |
|
149 | 154 | |
|
150 | 155 | debug_reg <= debug_reg_s; |
|
151 | 156 | |
|
152 | 157 | |
|
153 | 158 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
154 | 159 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
155 | 160 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
156 | 161 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
157 | 162 | '0'; |
|
158 | 163 | |
|
159 | 164 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
160 | 165 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE |
|
161 | 166 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
162 | 167 | '0'; |
|
163 | 168 | |
|
164 | 169 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
165 | 170 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
166 | 171 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
167 | 172 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
168 | 173 | (OTHERS => '0'); |
|
169 | 174 | |
|
170 | 175 | ----------------------------------------------------------------------------- |
|
171 | 176 | -- DMA control |
|
172 | 177 | ----------------------------------------------------------------------------- |
|
173 | 178 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
174 | 179 | BEGIN -- PROCESS DMAWriteBurst_p |
|
175 | 180 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
176 | 181 | matrix_type <= (OTHERS => '0'); |
|
177 | 182 | component_type <= (OTHERS => '0'); |
|
178 | 183 | state <= IDLE; |
|
179 | 184 | header_ack <= '0'; |
|
180 | 185 | ready_matrix_f0_0 <= '0'; |
|
181 | 186 | ready_matrix_f0_1 <= '0'; |
|
182 | 187 | ready_matrix_f1 <= '0'; |
|
183 | 188 | ready_matrix_f2 <= '0'; |
|
184 | 189 | error_anticipating_empty_fifo <= '0'; |
|
185 | 190 | error_bad_component_error <= '0'; |
|
186 | 191 | component_type_pre <= "0000"; |
|
187 | 192 | fifo_ren_trash <= '1'; |
|
188 | 193 | component_send <= '0'; |
|
189 | 194 | address <= (OTHERS => '0'); |
|
190 | 195 | header_select <= '0'; |
|
191 | 196 | header_send <= '0'; |
|
192 | 197 | header_data <= (OTHERS => '0'); |
|
193 | 198 | fine_time_reg <= (OTHERS => '0'); |
|
194 | 199 | |
|
195 | 200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
|
196 | 201 | |
|
197 | 202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
198 | 203 | |
|
199 | 204 | CASE state IS |
|
200 | 205 | WHEN IDLE => |
|
201 | 206 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
202 | 207 | |
|
203 | 208 | matrix_type <= header(1 DOWNTO 0); |
|
204 | 209 | --component_type <= header(5 DOWNTO 2); |
|
205 | 210 | |
|
206 | 211 | ready_matrix_f0_0 <= '0'; |
|
207 | 212 | ready_matrix_f0_1 <= '0'; |
|
208 | 213 | ready_matrix_f1 <= '0'; |
|
209 | 214 | ready_matrix_f2 <= '0'; |
|
210 | 215 | error_bad_component_error <= '0'; |
|
211 | 216 | header_select <= '1'; |
|
212 | 217 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
213 | 218 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
|
214 | 219 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
|
215 | 220 | |
|
216 | 221 | matrix_type <= header(1 DOWNTO 0); |
|
217 | 222 | component_type <= header(5 DOWNTO 2); |
|
218 | 223 | component_type_pre <= component_type; |
|
219 | 224 | state <= CHECK_COMPONENT_TYPE; |
|
220 | 225 | END IF; |
|
221 | 226 | |
|
222 | 227 | WHEN CHECK_COMPONENT_TYPE => |
|
223 | 228 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
224 | 229 | |
|
225 | 230 | IF header_check_ok = '1' THEN |
|
226 | 231 | header_ack <= '1'; |
|
227 | 232 | header_send <= '0'; |
|
228 | 233 | -- |
|
229 | 234 | IF component_type = "0000" THEN |
|
230 | 235 | address <= address_matrix; |
|
231 | state <= WRITE_COARSE_TIME; | |
|
236 | CASE matrix_type IS | |
|
237 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
|
238 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
|
239 | WHEN "10" => matrix_time_f1 <= data_time; | |
|
240 | WHEN "11" => matrix_time_f2 <= data_time ; | |
|
241 | WHEN OTHERS => NULL; | |
|
242 | END CASE; | |
|
243 | ||
|
232 | 244 |
|
|
233 | 245 | fine_time_reg <= data_time(47 DOWNTO 32); |
|
234 | header_send <= '1'; | |
|
246 | --state <= WRITE_COARSE_TIME; | |
|
247 | --header_send <= '1'; | |
|
248 | state <= SEND_DATA; | |
|
249 | header_send <= '0'; | |
|
250 | component_send <= '1'; | |
|
251 | header_select <= '0'; | |
|
235 | 252 | ELSE |
|
236 | 253 | state <= SEND_DATA; |
|
237 | 254 | END IF; |
|
238 | 255 | -- |
|
239 | 256 | ELSE |
|
240 | 257 | error_bad_component_error <= '1'; |
|
241 | 258 | component_type_pre <= "0000"; |
|
242 | 259 | header_ack <= '1'; |
|
243 | 260 | state <= TRASH_FIFO; |
|
244 | 261 | END IF; |
|
245 | 262 | |
|
246 | 263 | WHEN WRITE_COARSE_TIME => |
|
247 | 264 | debug_reg_s(2 DOWNTO 0) <= "010"; |
|
248 | 265 | |
|
249 | 266 | header_ack <= '0'; |
|
250 | 267 | |
|
251 | 268 | IF dma_ren = '0' THEN |
|
252 | 269 | header_send <= '0'; |
|
253 | 270 | ELSE |
|
254 | 271 | header_send <= header_send; |
|
255 | 272 | END IF; |
|
256 | 273 | |
|
257 | 274 | |
|
258 | 275 | IF header_send_ko = '1' THEN |
|
259 | 276 | header_send <= '0'; |
|
260 | 277 | state <= TRASH_FIFO; |
|
261 | 278 | error_anticipating_empty_fifo <= '1'; |
|
262 | 279 | -- TODO : error sending header |
|
263 | 280 | ELSIF header_send_ok = '1' THEN |
|
264 | 281 | header_send <= '1'; |
|
265 | 282 | header_select <= '1'; |
|
266 | 283 | header_data(15 DOWNTO 0) <= fine_time_reg; |
|
267 | 284 | header_data(31 DOWNTO 16) <= (OTHERS => '0'); |
|
268 | 285 | state <= WRITE_FINE_TIME; |
|
269 | 286 | address <= address + 4; |
|
270 | 287 | END IF; |
|
271 | 288 | |
|
272 | 289 | |
|
273 | 290 | WHEN WRITE_FINE_TIME => |
|
274 | 291 | debug_reg_s(2 DOWNTO 0) <= "011"; |
|
275 | 292 | |
|
276 | 293 | header_ack <= '0'; |
|
277 | header_ack <= '0'; | |
|
278 | 294 | |
|
279 | 295 | IF dma_ren = '0' THEN |
|
280 | 296 | header_send <= '0'; |
|
281 | 297 | ELSE |
|
282 | 298 | header_send <= header_send; |
|
283 | 299 | END IF; |
|
284 | 300 | |
|
285 | 301 | IF header_send_ko = '1' THEN |
|
286 | 302 | header_send <= '0'; |
|
287 | 303 | state <= TRASH_FIFO; |
|
288 | 304 | error_anticipating_empty_fifo <= '1'; |
|
289 | 305 | -- TODO : error sending header |
|
290 | 306 | ELSIF header_send_ok = '1' THEN |
|
291 | 307 | header_send <= '0'; |
|
292 | 308 | header_select <= '0'; |
|
293 | 309 | state <= SEND_DATA; |
|
294 | 310 | address <= address + 4; |
|
295 | 311 | END IF; |
|
296 | 312 | |
|
297 | 313 | WHEN TRASH_FIFO => |
|
298 | 314 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
299 | 315 | |
|
300 | 316 | header_ack <= '0'; |
|
301 | 317 | error_bad_component_error <= '0'; |
|
302 | 318 | error_anticipating_empty_fifo <= '0'; |
|
303 | 319 | IF fifo_empty = '1' THEN |
|
304 | 320 | state <= IDLE; |
|
305 | 321 | fifo_ren_trash <= '1'; |
|
306 | 322 | ELSE |
|
307 | 323 | fifo_ren_trash <= '0'; |
|
308 | 324 | END IF; |
|
309 | 325 | |
|
310 | 326 | WHEN SEND_DATA => |
|
327 | header_ack <= '0'; | |
|
311 | 328 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
312 | 329 | |
|
313 | 330 | IF fifo_empty = '1' THEN |
|
314 | 331 | state <= IDLE; |
|
315 | 332 | IF component_type = "1110" THEN --"1110" -- JC |
|
316 | 333 | CASE matrix_type IS |
|
317 | 334 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
318 | 335 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
319 | 336 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
320 | 337 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
321 | 338 | WHEN OTHERS => NULL; |
|
322 | 339 | END CASE; |
|
323 | 340 | |
|
324 | 341 | END IF; |
|
325 | 342 | ELSE |
|
326 | 343 | component_send <= '1'; |
|
327 | 344 | address <= address; |
|
328 | 345 | state <= WAIT_DATA_ACK; |
|
329 | 346 | END IF; |
|
330 | 347 | |
|
331 | 348 | WHEN WAIT_DATA_ACK => |
|
332 | 349 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
333 | 350 | |
|
334 | 351 | component_send <= '0'; |
|
335 | 352 | IF component_send_ok = '1' THEN |
|
336 | 353 | address <= address + 64; |
|
337 | 354 | state <= SEND_DATA; |
|
338 | 355 | ELSIF component_send_ko = '1' THEN |
|
339 | 356 | error_anticipating_empty_fifo <= '0'; |
|
340 | 357 | state <= TRASH_FIFO; |
|
341 | 358 | END IF; |
|
342 | 359 | |
|
343 | 360 | WHEN CHECK_LENGTH => |
|
361 | component_send <= '0'; | |
|
344 | 362 | debug_reg_s(2 DOWNTO 0) <= "111"; |
|
345 | 363 | state <= IDLE; |
|
346 | 364 | |
|
347 | 365 | WHEN OTHERS => NULL; |
|
348 | 366 | END CASE; |
|
349 | 367 | |
|
350 | 368 | END IF; |
|
351 | 369 | END PROCESS DMAWriteFSM_p; |
|
352 | 370 | |
|
353 | 371 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; |
|
354 | 372 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; |
|
355 | 373 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; |
|
356 | 374 | dma_addr <= address; |
|
357 | 375 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; |
|
358 | 376 | |
|
359 | 377 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; |
|
360 | 378 | component_send_ko <= '0'; |
|
361 | 379 | |
|
362 | 380 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; |
|
363 | 381 | header_send_ko <= '0'; |
|
364 | 382 | |
|
365 | 383 | END Behavioral; |
@@ -1,263 +1,287 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | 16 | |
|
17 | 17 | COMPONENT lpp_lfr_ms |
|
18 | 18 | GENERIC ( |
|
19 | 19 | Mem_use : INTEGER |
|
20 | 20 | ); |
|
21 | 21 | PORT ( |
|
22 | 22 | clk : IN STD_LOGIC; |
|
23 | 23 | rstn : IN STD_LOGIC; |
|
24 | 24 | |
|
25 | 25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
26 | 26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
27 | 27 | |
|
28 | 28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
29 | 29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
30 | 30 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 31 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 32 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | 33 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | 34 | |
|
35 | 35 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
36 | 36 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
37 | 37 | dma_valid : OUT STD_LOGIC; |
|
38 | 38 | dma_valid_burst : OUT STD_LOGIC; |
|
39 | 39 | dma_ren : IN STD_LOGIC; |
|
40 | 40 | dma_done : IN STD_LOGIC; |
|
41 | 41 | |
|
42 | 42 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
43 | 43 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
44 | 44 | ready_matrix_f1 : OUT STD_LOGIC; |
|
45 | 45 | ready_matrix_f2 : OUT STD_LOGIC; |
|
46 | 46 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
47 | 47 | error_bad_component_error : OUT STD_LOGIC; |
|
48 | 48 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
49 | 49 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
50 | 50 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
51 | 51 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
52 | 52 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
53 | 53 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
54 | 54 | status_error_bad_component_error : IN STD_LOGIC; |
|
55 | 55 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
56 | 56 | config_active_interruption_onError : IN STD_LOGIC; |
|
57 | 57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | 58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | 59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
61 | ||
|
62 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
64 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
65 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
|
61 | 66 | END COMPONENT; |
|
62 | 67 | |
|
63 | 68 | COMPONENT lpp_lfr_ms_fsmdma |
|
64 | 69 | PORT ( |
|
65 | 70 | HCLK : IN STD_ULOGIC; |
|
66 | 71 | HRESETn : IN STD_ULOGIC; |
|
67 | 72 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
68 | 73 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | 74 | fifo_empty : IN STD_LOGIC; |
|
70 | 75 | fifo_ren : OUT STD_LOGIC; |
|
71 | 76 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | 77 | header_val : IN STD_LOGIC; |
|
73 | 78 | header_ack : OUT STD_LOGIC; |
|
74 | 79 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | 80 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | 81 | dma_valid : OUT STD_LOGIC; |
|
77 | 82 | dma_valid_burst : OUT STD_LOGIC; |
|
78 | 83 | dma_ren : IN STD_LOGIC; |
|
79 | 84 | dma_done : IN STD_LOGIC; |
|
80 | 85 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
81 | 86 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
82 | 87 | ready_matrix_f1 : OUT STD_LOGIC; |
|
83 | 88 | ready_matrix_f2 : OUT STD_LOGIC; |
|
84 | 89 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
85 | 90 | error_bad_component_error : OUT STD_LOGIC; |
|
86 | 91 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | 92 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
88 | 93 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
89 | 94 | status_ready_matrix_f1 : IN STD_LOGIC; |
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90 | 95 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
91 | 96 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
92 | 97 | status_error_bad_component_error : IN STD_LOGIC; |
|
93 | 98 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
94 | 99 | config_active_interruption_onError : IN STD_LOGIC; |
|
95 | 100 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
96 | 101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | 102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 |
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
104 | ||
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105 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
107 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
108 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
109 | ); | |
|
99 | 110 | END COMPONENT; |
|
100 | 111 | |
|
101 | 112 | |
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102 | 113 | COMPONENT lpp_lfr_filter |
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103 | 114 | GENERIC ( |
|
104 | 115 | Mem_use : INTEGER); |
|
105 | 116 | PORT ( |
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106 | 117 | sample : IN Samples(7 DOWNTO 0); |
|
107 | 118 | sample_val : IN STD_LOGIC; |
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108 | 119 | clk : IN STD_LOGIC; |
|
109 | 120 | rstn : IN STD_LOGIC; |
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110 | 121 | data_shaping_SP0 : IN STD_LOGIC; |
|
111 | 122 | data_shaping_SP1 : IN STD_LOGIC; |
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112 | 123 | data_shaping_R0 : IN STD_LOGIC; |
|
113 | 124 | data_shaping_R1 : IN STD_LOGIC; |
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114 | 125 | sample_f0_val : OUT STD_LOGIC; |
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115 | 126 | sample_f1_val : OUT STD_LOGIC; |
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116 | 127 | sample_f2_val : OUT STD_LOGIC; |
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117 | 128 | sample_f3_val : OUT STD_LOGIC; |
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118 | 129 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
119 | 130 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
120 | 131 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
121 | 132 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
122 | 133 | END COMPONENT; |
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123 | 134 | |
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124 | 135 | COMPONENT lpp_lfr |
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125 | 136 | GENERIC ( |
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126 | 137 | Mem_use : INTEGER; |
|
127 | 138 | nb_data_by_buffer_size : INTEGER; |
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128 | 139 | nb_word_by_buffer_size : INTEGER; |
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129 | 140 | nb_snapshot_param_size : INTEGER; |
|
130 | 141 | delta_vector_size : INTEGER; |
|
131 | 142 | delta_vector_size_f0_2 : INTEGER; |
|
132 | 143 | pindex : INTEGER; |
|
133 | 144 | paddr : INTEGER; |
|
134 | 145 | pmask : INTEGER; |
|
135 | 146 | pirq_ms : INTEGER; |
|
136 | 147 | pirq_wfp : INTEGER; |
|
137 | 148 | hindex : INTEGER; |
|
138 | 149 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
139 | 150 | ); |
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140 | 151 | PORT ( |
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141 | 152 | clk : IN STD_LOGIC; |
|
142 | 153 | rstn : IN STD_LOGIC; |
|
143 | 154 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
144 | 155 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
145 | 156 | sample_val : IN STD_LOGIC; |
|
146 | 157 | apbi : IN apb_slv_in_type; |
|
147 | 158 | apbo : OUT apb_slv_out_type; |
|
148 | 159 | ahbi : IN AHB_Mst_In_Type; |
|
149 | 160 | ahbo : OUT AHB_Mst_Out_Type; |
|
150 | 161 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | 162 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
152 | 163 | data_shaping_BW : OUT STD_LOGIC; |
|
153 | 164 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
154 | 165 | ); |
|
155 | 166 | END COMPONENT; |
|
156 | 167 | |
|
157 | 168 | COMPONENT lpp_lfr_apbreg |
|
158 | 169 | GENERIC ( |
|
159 | 170 | nb_data_by_buffer_size : INTEGER; |
|
160 | 171 | nb_word_by_buffer_size : INTEGER; |
|
161 | 172 | nb_snapshot_param_size : INTEGER; |
|
162 | 173 | delta_vector_size : INTEGER; |
|
163 | 174 | delta_vector_size_f0_2 : INTEGER; |
|
164 | 175 | pindex : INTEGER; |
|
165 | 176 | paddr : INTEGER; |
|
166 | 177 | pmask : INTEGER; |
|
167 | 178 | pirq_ms : INTEGER; |
|
168 | 179 | pirq_wfp : INTEGER; |
|
169 | 180 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
170 | 181 | PORT ( |
|
171 | 182 | HCLK : IN STD_ULOGIC; |
|
172 | 183 | HRESETn : IN STD_ULOGIC; |
|
173 | 184 | apbi : IN apb_slv_in_type; |
|
174 | 185 | apbo : OUT apb_slv_out_type; |
|
186 | run_ms : OUT STD_LOGIC; | |
|
175 | 187 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
176 | 188 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
177 | 189 | ready_matrix_f1 : IN STD_LOGIC; |
|
178 | 190 | ready_matrix_f2 : IN STD_LOGIC; |
|
179 | 191 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
180 | 192 | error_bad_component_error : IN STD_LOGIC; |
|
181 | 193 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
182 | 194 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
183 | 195 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
184 | 196 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
185 | 197 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
186 | 198 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
187 | 199 | status_error_bad_component_error : OUT STD_LOGIC; |
|
188 | 200 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
189 | 201 | config_active_interruption_onError : OUT STD_LOGIC; |
|
190 | 202 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | 203 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | 204 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | 205 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
206 | ||
|
207 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
208 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
209 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
210 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
211 | ||
|
194 | 212 |
|
|
195 | 213 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
196 | 214 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
197 | 215 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
198 | 216 | data_shaping_BW : OUT STD_LOGIC; |
|
199 | 217 | data_shaping_SP0 : OUT STD_LOGIC; |
|
200 | 218 | data_shaping_SP1 : OUT STD_LOGIC; |
|
201 | 219 | data_shaping_R0 : OUT STD_LOGIC; |
|
202 | 220 | data_shaping_R1 : OUT STD_LOGIC; |
|
203 | 221 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
204 | 222 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
205 | 223 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
206 | 224 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
207 | 225 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
208 | 226 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
209 | 227 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
210 | 228 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
211 | 229 | enable_f0 : OUT STD_LOGIC; |
|
212 | 230 | enable_f1 : OUT STD_LOGIC; |
|
213 | 231 | enable_f2 : OUT STD_LOGIC; |
|
214 | 232 | enable_f3 : OUT STD_LOGIC; |
|
215 | 233 | burst_f0 : OUT STD_LOGIC; |
|
216 | 234 | burst_f1 : OUT STD_LOGIC; |
|
217 | 235 | burst_f2 : OUT STD_LOGIC; |
|
218 | 236 | run : OUT STD_LOGIC; |
|
219 | 237 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | 238 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | 239 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | 240 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
223 | 241 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
224 | 242 | --------------------------------------------------------------------------- |
|
225 | 243 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
226 | 244 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
227 | 245 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
228 | 246 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
229 | 247 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
230 | 248 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
231 | 249 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
232 | 250 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
233 | 251 | END COMPONENT; |
|
234 | 252 | |
|
235 | 253 | COMPONENT lpp_top_ms |
|
236 | 254 | GENERIC ( |
|
237 | 255 | Mem_use : INTEGER; |
|
238 | 256 | nb_burst_available_size : INTEGER; |
|
239 | 257 | nb_snapshot_param_size : INTEGER; |
|
240 | 258 | delta_snapshot_size : INTEGER; |
|
241 | 259 | delta_f2_f0_size : INTEGER; |
|
242 | 260 | delta_f2_f1_size : INTEGER; |
|
243 | 261 | pindex : INTEGER; |
|
244 | 262 | paddr : INTEGER; |
|
245 | 263 | pmask : INTEGER; |
|
246 | 264 | pirq_ms : INTEGER; |
|
247 | 265 | pirq_wfp : INTEGER; |
|
248 | 266 | hindex_wfp : INTEGER; |
|
249 | 267 | hindex_ms : INTEGER); |
|
250 | 268 | PORT ( |
|
251 | 269 | clk : IN STD_LOGIC; |
|
252 | 270 | rstn : IN STD_LOGIC; |
|
253 | 271 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
254 | 272 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
255 | 273 | sample_val : IN STD_LOGIC; |
|
256 | 274 | apbi : IN apb_slv_in_type; |
|
257 | 275 | apbo : OUT apb_slv_out_type; |
|
258 | 276 | ahbi_ms : IN AHB_Mst_In_Type; |
|
259 | 277 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
260 |
data_shaping_BW : OUT STD_LOGIC |
|
|
278 | data_shaping_BW : OUT STD_LOGIC; | |
|
279 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
280 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
281 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
282 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
283 | ||
|
284 | ); | |
|
261 | 285 | END COMPONENT; |
|
262 | 286 | |
|
263 | 287 | END lpp_lfr_pkg; |
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