@@ -26,7 +26,7 ENTITY lpp_lfr IS | |||
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26 | 26 | GENERIC ( |
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27 | 27 | Mem_use : INTEGER := use_RAM; |
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28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
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29 | nb_word_by_buffer_size : INTEGER := 11; | |
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29 | -- nb_word_by_buffer_size : INTEGER := 11; -- TODO | |
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30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
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31 | 31 | delta_vector_size : INTEGER := 20; |
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32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
@@ -161,9 +161,9 ARCHITECTURE beh OF lpp_lfr IS | |||
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161 | 161 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
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162 | 162 | |
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163 | 163 | -- WFP |
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164 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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165 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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166 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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164 | --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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165 | --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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166 | --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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167 | 167 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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168 | 168 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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169 | 169 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
@@ -172,7 +172,6 ARCHITECTURE beh OF lpp_lfr IS | |||
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172 | 172 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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173 | 173 | |
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174 | 174 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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175 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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176 | 175 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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177 | 176 | SIGNAL enable_f0 : STD_LOGIC; |
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178 | 177 | SIGNAL enable_f1 : STD_LOGIC; |
@@ -181,38 +180,10 ARCHITECTURE beh OF lpp_lfr IS | |||
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181 | 180 | SIGNAL burst_f0 : STD_LOGIC; |
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182 | 181 | SIGNAL burst_f1 : STD_LOGIC; |
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183 | 182 | SIGNAL burst_f2 : STD_LOGIC; |
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184 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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185 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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186 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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187 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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188 | 183 | |
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189 | 184 | SIGNAL run : STD_LOGIC; |
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190 | 185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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191 | 186 | |
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192 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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194 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
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195 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
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196 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
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197 | --f1 | |
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198 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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199 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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200 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
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201 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
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202 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
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203 | --f2 | |
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204 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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205 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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206 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
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207 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
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208 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
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209 | --f3 | |
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210 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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211 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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212 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
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213 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
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214 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
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215 | ||
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216 | 187 | ----------------------------------------------------------------------------- |
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217 | 188 | -- |
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218 | 189 | ----------------------------------------------------------------------------- |
@@ -232,6 +203,12 ARCHITECTURE beh OF lpp_lfr IS | |||
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232 | 203 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
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233 | 204 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
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234 | 205 | |
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206 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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207 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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208 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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209 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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210 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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211 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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235 | 212 | ----------------------------------------------------------------------------- |
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236 | 213 | -- DMA RR |
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237 | 214 | ----------------------------------------------------------------------------- |
@@ -340,7 +317,7 BEGIN | |||
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340 | 317 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
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341 | 318 | GENERIC MAP ( |
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342 | 319 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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343 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
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320 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO | |
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344 | 321 | nb_snapshot_param_size => nb_snapshot_param_size, |
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345 | 322 | delta_vector_size => delta_vector_size, |
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346 | 323 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
@@ -379,9 +356,9 BEGIN | |||
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379 | 356 | length_matrix_f1 => length_matrix_f1, |
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380 | 357 | length_matrix_f2 => length_matrix_f2, |
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381 | 358 | ------------------------------------------------------------------------- |
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382 | status_full => status_full, | |
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383 | status_full_ack => status_full_ack, | |
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384 | status_full_err => status_full_err, | |
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359 | --status_full => status_full, -- TODo | |
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360 | --status_full_ack => status_full_ack, -- TODo | |
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361 | --status_full_err => status_full_err, -- TODo | |
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385 | 362 | status_new_err => status_new_err, |
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386 | 363 | data_shaping_BW => data_shaping_BW, |
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387 | 364 | data_shaping_SP0 => data_shaping_SP0, |
@@ -395,7 +372,7 BEGIN | |||
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395 | 372 | delta_f1 => delta_f1, |
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396 | 373 | delta_f2 => delta_f2, |
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397 | 374 | nb_data_by_buffer => nb_data_by_buffer, |
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398 | nb_word_by_buffer => nb_word_by_buffer, | |
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375 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO | |
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399 | 376 | nb_snapshot_param => nb_snapshot_param, |
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400 | 377 | enable_f0 => enable_f0, |
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401 | 378 | enable_f1 => enable_f1, |
@@ -405,12 +382,16 BEGIN | |||
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405 | 382 | burst_f1 => burst_f1, |
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406 | 383 | burst_f2 => burst_f2, |
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407 | 384 | run => run, |
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408 | addr_data_f0 => addr_data_f0, | |
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409 | addr_data_f1 => addr_data_f1, | |
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410 | addr_data_f2 => addr_data_f2, | |
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411 | addr_data_f3 => addr_data_f3, | |
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412 | 385 | start_date => start_date, |
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413 |
debug_signal => debug_signal |
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386 | -- debug_signal => debug_signal, | |
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387 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO | |
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388 | wfp_addr_buffer => wfp_addr_buffer,-- TODO | |
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389 | wfp_length_buffer => wfp_length_buffer,-- TODO | |
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390 | ||
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391 | wfp_ready_buffer => wfp_ready_buffer,-- TODO | |
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392 | wfp_buffer_time => wfp_buffer_time,-- TODO | |
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393 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO | |
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394 | ); | |
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414 | 395 | |
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415 | 396 | ----------------------------------------------------------------------------- |
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416 | 397 | ----------------------------------------------------------------------------- |
@@ -419,7 +400,6 BEGIN | |||
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419 | 400 | tech => inferred, |
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420 | 401 | data_size => 6*16, |
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421 | 402 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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422 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
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423 | 403 | nb_snapshot_param_size => nb_snapshot_param_size, |
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424 | 404 | delta_vector_size => delta_vector_size, |
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425 | 405 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
@@ -445,235 +425,44 BEGIN | |||
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445 | 425 | burst_f2 => burst_f2, |
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446 | 426 | |
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447 | 427 | nb_data_by_buffer => nb_data_by_buffer, |
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448 | nb_word_by_buffer => nb_word_by_buffer, | |
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449 | 428 | nb_snapshot_param => nb_snapshot_param, |
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450 | status_full => status_full, | |
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451 | status_full_ack => status_full_ack, | |
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452 | status_full_err => status_full_err, | |
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453 | 429 | status_new_err => status_new_err, |
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454 | 430 | |
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431 | status_buffer_ready => wfp_status_buffer_ready, | |
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432 | addr_buffer => wfp_addr_buffer, | |
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433 | length_buffer => wfp_length_buffer, | |
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434 | ready_buffer => wfp_ready_buffer, | |
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435 | buffer_time => wfp_buffer_time, | |
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436 | error_buffer_full => wfp_error_buffer_full, | |
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437 | ||
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455 | 438 | coarse_time => coarse_time, |
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456 | 439 | fine_time => fine_time, |
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457 | 440 | |
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458 | 441 | --f0 |
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459 | addr_data_f0 => addr_data_f0, | |
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460 | 442 | data_f0_in_valid => sample_f0_val, |
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461 | 443 | data_f0_in => sample_f0_data, |
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462 | 444 | --f1 |
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463 | addr_data_f1 => addr_data_f1, | |
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464 | 445 | data_f1_in_valid => sample_f1_val, |
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465 | 446 | data_f1_in => sample_f1_data, |
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466 | 447 | --f2 |
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467 | addr_data_f2 => addr_data_f2, | |
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468 | 448 | data_f2_in_valid => sample_f2_val, |
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469 | 449 | data_f2_in => sample_f2_data, |
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470 | 450 | --f3 |
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471 | addr_data_f3 => addr_data_f3, | |
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472 | 451 | data_f3_in_valid => sample_f3_val, |
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473 | 452 | data_f3_in => sample_f3_data, |
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474 | 453 | -- OUTPUT -- DMA interface |
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475 | --f0 | |
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476 | data_f0_addr_out => data_f0_addr_out_s, | |
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477 | data_f0_data_out => data_f0_data_out, | |
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478 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
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479 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
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480 | data_f0_data_out_ren => data_f0_data_out_ren, | |
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481 | --f1 | |
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482 | data_f1_addr_out => data_f1_addr_out_s, | |
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483 | data_f1_data_out => data_f1_data_out, | |
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484 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
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485 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
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486 | data_f1_data_out_ren => data_f1_data_out_ren, | |
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487 | --f2 | |
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488 | data_f2_addr_out => data_f2_addr_out_s, | |
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489 | data_f2_data_out => data_f2_data_out, | |
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490 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
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491 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
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492 | data_f2_data_out_ren => data_f2_data_out_ren, | |
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493 | --f3 | |
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494 | data_f3_addr_out => data_f3_addr_out_s, | |
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495 | data_f3_data_out => data_f3_data_out, | |
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496 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
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497 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
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498 | data_f3_data_out_ren => data_f3_data_out_ren , | |
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499 | 454 | |
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500 | ------------------------------------------------------------------------- | |
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501 | observation_reg => OPEN | |
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455 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), | |
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456 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), | |
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457 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), | |
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458 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), | |
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459 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), | |
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460 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), | |
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461 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), | |
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462 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) | |
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502 | 463 | |
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503 | 464 | ); |
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504 | 465 |
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505 | ||
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506 | ----------------------------------------------------------------------------- | |
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507 | -- TEMP | |
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508 | ----------------------------------------------------------------------------- | |
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509 | ||
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510 | PROCESS (clk, rstn) | |
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511 | BEGIN -- PROCESS | |
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512 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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513 | data_f0_data_out_valid <= '0'; | |
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514 | data_f0_data_out_valid_burst <= '0'; | |
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515 | data_f1_data_out_valid <= '0'; | |
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516 | data_f1_data_out_valid_burst <= '0'; | |
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517 | data_f2_data_out_valid <= '0'; | |
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518 | data_f2_data_out_valid_burst <= '0'; | |
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519 | data_f3_data_out_valid <= '0'; | |
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520 | data_f3_data_out_valid_burst <= '0'; | |
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521 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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522 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
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523 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
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524 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
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525 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
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526 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
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527 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
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528 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
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529 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
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530 | END IF; | |
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531 | END PROCESS; | |
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532 | ||
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533 | data_f0_addr_out <= data_f0_addr_out_s; | |
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534 | data_f1_addr_out <= data_f1_addr_out_s; | |
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535 | data_f2_addr_out <= data_f2_addr_out_s; | |
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536 | data_f3_addr_out <= data_f3_addr_out_s; | |
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537 | ||
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538 | ----------------------------------------------------------------------------- | |
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539 | -- RoundRobin Selection For DMA | |
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540 | ----------------------------------------------------------------------------- | |
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541 | ||
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542 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
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543 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
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544 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
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545 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
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546 | ||
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547 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
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548 | PORT MAP ( | |
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549 | clk => clk, | |
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550 | rstn => rstn, | |
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551 | in_valid => dma_rr_valid, | |
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552 | out_grant => dma_rr_grant_s); | |
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553 | ||
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554 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
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555 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
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556 | dma_rr_valid_ms(2) <= '0'; | |
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557 | dma_rr_valid_ms(3) <= '0'; | |
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558 | ||
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559 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
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560 | PORT MAP ( | |
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561 | clk => clk, | |
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562 | rstn => rstn, | |
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563 | in_valid => dma_rr_valid_ms, | |
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564 | out_grant => dma_rr_grant_ms); | |
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565 | ||
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566 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
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567 | ||
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568 | ||
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569 | ----------------------------------------------------------------------------- | |
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570 | -- in : dma_rr_grant | |
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571 | -- send | |
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572 | -- out : dma_sel | |
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573 | -- dma_valid_burst | |
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574 | -- dma_sel_valid | |
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575 | ----------------------------------------------------------------------------- | |
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576 | PROCESS (clk, rstn) | |
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577 | BEGIN -- PROCESS | |
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578 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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579 | dma_sel <= (OTHERS => '0'); | |
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580 | dma_send <= '0'; | |
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581 | dma_valid_burst <= '0'; | |
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582 | data_ms_done <= '0'; | |
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583 | dma_ms_ongoing <= '0'; | |
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584 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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585 | IF run = '1' THEN | |
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586 | data_ms_done <= '0'; | |
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587 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
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588 | dma_sel <= dma_rr_grant; | |
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589 | IF dma_rr_grant(0) = '1' THEN | |
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590 | dma_ms_ongoing <= '0'; | |
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591 | dma_send <= '1'; | |
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592 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
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593 | dma_sel_valid <= data_f0_data_out_valid; | |
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594 | ELSIF dma_rr_grant(1) = '1' THEN | |
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595 | dma_ms_ongoing <= '0'; | |
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596 | dma_send <= '1'; | |
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597 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
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598 | dma_sel_valid <= data_f1_data_out_valid; | |
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599 | ELSIF dma_rr_grant(2) = '1' THEN | |
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600 | dma_ms_ongoing <= '0'; | |
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601 | dma_send <= '1'; | |
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602 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
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603 | dma_sel_valid <= data_f2_data_out_valid; | |
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604 | ELSIF dma_rr_grant(3) = '1' THEN | |
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605 | dma_ms_ongoing <= '0'; | |
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606 | dma_send <= '1'; | |
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607 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
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608 | dma_sel_valid <= data_f3_data_out_valid; | |
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609 | ELSIF dma_rr_grant(4) = '1' THEN | |
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610 | dma_ms_ongoing <= '1'; | |
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611 | dma_send <= '1'; | |
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612 | dma_valid_burst <= data_ms_valid_burst; | |
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613 | dma_sel_valid <= data_ms_valid; | |
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614 | --ELSE | |
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615 | --dma_ms_ongoing <= '0'; | |
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616 | END IF; | |
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617 | ||
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618 | IF dma_ms_ongoing = '1' AND dma_done = '1' THEN | |
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619 | data_ms_done <= '1'; | |
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620 | END IF; | |
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621 | ELSE | |
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622 | dma_sel <= dma_sel; | |
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623 | dma_send <= '0'; | |
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624 | END IF; | |
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625 | ELSE | |
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626 | data_ms_done <= '0'; | |
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627 | dma_sel <= (OTHERS => '0'); | |
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628 | dma_send <= '0'; | |
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629 | dma_valid_burst <= '0'; | |
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630 | END IF; | |
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631 | END IF; | |
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632 | END PROCESS; | |
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633 | ||
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634 | ||
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635 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
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636 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
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637 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
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638 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
|
639 | data_ms_addr; | |
|
640 | ||
|
641 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
|
642 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
|
643 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
|
644 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
|
645 | data_ms_data; | |
|
646 | ||
|
647 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
|
648 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
|
649 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
|
650 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
|
651 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |
|
652 | ||
|
653 | dma_data_2 <= dma_data; | |
|
654 | ||
|
655 | ||
|
656 | ----------------------------------------------------------------------------- | |
|
657 | -- DMA | |
|
658 | ----------------------------------------------------------------------------- | |
|
659 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
|
660 | GENERIC MAP ( | |
|
661 | tech => inferred, | |
|
662 | hindex => hindex) | |
|
663 | PORT MAP ( | |
|
664 | HCLK => clk, | |
|
665 | HRESETn => rstn, | |
|
666 | run => run, | |
|
667 | AHB_Master_In => OPEN, | |
|
668 | AHB_Master_Out => OPEN, | |
|
669 | ||
|
670 | send => dma_send, | |
|
671 | valid_burst => dma_valid_burst, | |
|
672 | done => dma_done, | |
|
673 | ren => dma_ren, | |
|
674 | address => dma_address, | |
|
675 | data => dma_data_2); | |
|
676 | ||
|
677 | 466 | ----------------------------------------------------------------------------- |
|
678 | 467 | -- Matrix Spectral |
|
679 | 468 | ----------------------------------------------------------------------------- |
@@ -38,7 +38,7 USE techmap.gencomp.ALL; | |||
|
38 | 38 | ENTITY lpp_lfr_apbreg IS |
|
39 | 39 | GENERIC ( |
|
40 | 40 | nb_data_by_buffer_size : INTEGER := 11; |
|
41 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | -- nb_word_by_buffer_size : INTEGER := 11; | |
|
42 | 42 | nb_snapshot_param_size : INTEGER := 11; |
|
43 | 43 | delta_vector_size : INTEGER := 20; |
|
44 | 44 | delta_vector_size_f0_2 : INTEGER := 3; |
@@ -95,9 +95,9 ENTITY lpp_lfr_apbreg IS | |||
|
95 | 95 | --------------------------------------------------------------------------- |
|
96 | 96 | --------------------------------------------------------------------------- |
|
97 | 97 | -- WaveForm picker Reg |
|
98 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
101 | 101 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 |
|
@@ -114,7 +114,7 ENTITY lpp_lfr_apbreg IS | |||
|
114 | 114 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
115 | 115 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
116 | 116 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
117 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
117 | --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
118 | 118 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
119 | 119 | |
|
120 | 120 | enable_f0 : OUT STD_LOGIC; |
@@ -128,14 +128,15 ENTITY lpp_lfr_apbreg IS | |||
|
128 | 128 | |
|
129 | 129 | run : OUT STD_LOGIC; |
|
130 | 130 | |
|
131 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
133 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
134 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | 131 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
136 | --------------------------------------------------------------------------- | |
|
137 |
|
|
|
138 | --------------------------------------------------------------------------- | |
|
132 | ||
|
133 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
134 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
|
135 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
136 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
137 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
|
138 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
139 | ||
|
139 | 140 |
|
|
140 | 141 | |
|
141 | 142 | END lpp_lfr_apbreg; |
@@ -181,8 +182,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
181 | 182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
182 | 183 | |
|
183 | 184 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | 187 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | 188 | data_shaping_BW : STD_LOGIC; |
|
188 | 189 | data_shaping_SP0 : STD_LOGIC; |
@@ -196,7 +197,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
196 | 197 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
197 | 198 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
198 | 199 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
199 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
200 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
200 | 201 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
201 | 202 | enable_f0 : STD_LOGIC; |
|
202 | 203 | enable_f1 : STD_LOGIC; |
@@ -206,10 +207,11 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
206 | 207 | burst_f1 : STD_LOGIC; |
|
207 | 208 | burst_f2 : STD_LOGIC; |
|
208 | 209 | run : STD_LOGIC; |
|
209 |
|
|
|
210 |
|
|
|
211 |
|
|
|
212 |
|
|
|
210 | status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); | |
|
211 | addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); | |
|
212 | time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); | |
|
213 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
214 | error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
213 | 215 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
214 | 216 | END RECORD; |
|
215 | 217 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
@@ -254,6 +256,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
254 | 256 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
255 | 257 | SIGNAL apbo_irq_ms : STD_LOGIC; |
|
256 | 258 | SIGNAL apbo_irq_wfp : STD_LOGIC; |
|
259 | ----------------------------------------------------------------------------- | |
|
260 | SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); | |
|
257 | 261 | |
|
258 | 262 | BEGIN -- beh |
|
259 | 263 | |
@@ -283,7 +287,6 BEGIN -- beh | |||
|
283 | 287 | delta_f1 <= reg_wp.delta_f1; |
|
284 | 288 | delta_f2 <= reg_wp.delta_f2; |
|
285 | 289 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
286 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
287 | 290 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
288 | 291 | |
|
289 | 292 | enable_f0 <= reg_wp.enable_f0; |
@@ -297,16 +300,16 BEGIN -- beh | |||
|
297 | 300 | |
|
298 | 301 | run <= reg_wp.run; |
|
299 | 302 | |
|
300 | addr_data_f0 <= reg_wp.addr_data_f0; | |
|
301 | addr_data_f1 <= reg_wp.addr_data_f1; | |
|
302 | addr_data_f2 <= reg_wp.addr_data_f2; | |
|
303 | addr_data_f3 <= reg_wp.addr_data_f3; | |
|
303 | --addr_data_f0 <= reg_wp.addr_data_f0; | |
|
304 | --addr_data_f1 <= reg_wp.addr_data_f1; | |
|
305 | --addr_data_f2 <= reg_wp.addr_data_f2; | |
|
306 | --addr_data_f3 <= reg_wp.addr_data_f3; | |
|
304 | 307 | |
|
305 | 308 | start_date <= reg_wp.start_date; |
|
306 | 309 | |
|
307 | length_matrix_f0 <= reg_sp.length_matrix; | |
|
308 | length_matrix_f1 <= reg_sp.length_matrix; | |
|
309 | length_matrix_f2 <= reg_sp.length_matrix; | |
|
310 | --length_matrix_f0 <= reg_sp.length_matrix; | |
|
311 | --length_matrix_f1 <= reg_sp.length_matrix; | |
|
312 | --length_matrix_f2 <= reg_sp.length_matrix; | |
|
310 | 313 | |
|
311 | 314 | |
|
312 | 315 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
@@ -322,7 +325,6 BEGIN -- beh | |||
|
322 | 325 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
323 | 326 | reg_sp.status_ready_matrix_f1_1 <= '0'; |
|
324 | 327 | reg_sp.status_ready_matrix_f2_1 <= '0'; |
|
325 | -- reg_sp.status_error_bad_component_error <= '0'; | |
|
326 | 328 | reg_sp.status_error_buffer_full <= '0'; |
|
327 | 329 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
328 | 330 | |
@@ -351,7 +353,7 BEGIN -- beh | |||
|
351 | 353 | apbo_irq_wfp <= '0'; |
|
352 | 354 | |
|
353 | 355 | |
|
354 |
|
|
|
356 | -- status_full_ack <= (OTHERS => '0'); | |
|
355 | 357 | |
|
356 | 358 | reg_wp.data_shaping_BW <= '0'; |
|
357 | 359 | reg_wp.data_shaping_SP0 <= '0'; |
@@ -367,13 +369,10 BEGIN -- beh | |||
|
367 | 369 | reg_wp.burst_f1 <= '0'; |
|
368 | 370 | reg_wp.burst_f2 <= '0'; |
|
369 | 371 | reg_wp.run <= '0'; |
|
370 |
reg_wp. |
|
|
371 |
reg_wp. |
|
|
372 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
373 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
374 | reg_wp.status_full <= (OTHERS => '0'); | |
|
375 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
372 | -- reg_wp.status_full <= (OTHERS => '0'); | |
|
373 | -- reg_wp.status_full_err <= (OTHERS => '0'); | |
|
376 | 374 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
375 | reg_wp.error_buffer_full <= (OTHERS => '0'); | |
|
377 | 376 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
378 | 377 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
379 | 378 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
@@ -385,7 +384,7 BEGIN -- beh | |||
|
385 | 384 | |
|
386 | 385 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
387 | 386 | |
|
388 | status_full_ack <= (OTHERS => '0'); | |
|
387 | -- status_full_ack <= (OTHERS => '0'); | |
|
389 | 388 | |
|
390 | 389 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; |
|
391 | 390 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; |
@@ -395,7 +394,10 BEGIN -- beh | |||
|
395 | 394 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; |
|
396 | 395 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; |
|
397 | 396 | |
|
398 | -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
397 | all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP | |
|
398 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); | |
|
399 | END LOOP all_status_ready_buffer_bit; | |
|
400 | ||
|
399 | 401 | |
|
400 | 402 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
401 | 403 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); |
@@ -405,9 +407,8 BEGIN -- beh | |||
|
405 | 407 | |
|
406 | 408 | |
|
407 | 409 | all_status : FOR I IN 3 DOWNTO 0 LOOP |
|
408 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
409 |
reg_wp.status_ |
|
|
410 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; | |
|
410 | reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); | |
|
411 | reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); | |
|
411 | 412 | END LOOP all_status; |
|
412 | 413 | |
|
413 | 414 | paddr := "000000"; |
@@ -488,35 +489,58 BEGIN -- beh | |||
|
488 | 489 | prdata(6) <= reg_wp.burst_f2; |
|
489 | 490 | prdata(7) <= reg_wp.run; |
|
490 | 491 | --22 |
|
491 | WHEN "010111" => prdata <= reg_wp.addr_data_f0; | |
|
492 | --23 | |
|
493 |
WHEN "011000" => prdata <= reg_wp.addr_ |
|
|
494 | --24 | |
|
495 |
WHEN "0110 |
|
|
496 | --25 | |
|
497 |
WHEN "011 |
|
|
498 | --26 | |
|
499 |
WHEN "011 |
|
|
500 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
501 |
|
|
|
492 | --ON GOING \/ | |
|
493 | WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); | |
|
494 | WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); | |
|
495 | WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); | |
|
496 | WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); | |
|
497 | WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); | |
|
498 | WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); | |
|
499 | WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); | |
|
500 | WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); | |
|
501 | --ON GOING /\ | |
|
502 | WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; | |
|
503 | prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; | |
|
504 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; | |
|
505 | --prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
506 | -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
502 | 507 | --27 |
|
503 |
WHEN " |
|
|
508 | WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
504 | 509 | --28 |
|
505 |
WHEN " |
|
|
510 | WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
506 | 511 | --29 |
|
507 |
WHEN " |
|
|
512 | WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
508 | 513 | --30 |
|
509 |
WHEN " |
|
|
514 | WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
510 | 515 | --31 |
|
511 |
WHEN "100 |
|
|
516 | WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
512 | 517 | --32 |
|
513 |
WHEN "100 |
|
|
518 | WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
514 | 519 | --33 |
|
515 |
WHEN "100 |
|
|
520 | WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
516 | 521 | --34 |
|
517 |
WHEN "100 |
|
|
522 | WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
518 | 523 | --35 |
|
519 |
WHEN "10 |
|
|
524 | WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); | |
|
525 | WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); | |
|
526 | WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); | |
|
527 | WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); | |
|
528 | WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); | |
|
529 | WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); | |
|
530 | WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); | |
|
531 | WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); | |
|
532 | ||
|
533 | WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); | |
|
534 | WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); | |
|
535 | WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); | |
|
536 | WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); | |
|
537 | WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); | |
|
538 | WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); | |
|
539 | WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); | |
|
540 | WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); | |
|
541 | WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; | |
|
542 | ||
|
543 | -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
520 | 544 | ---------------------------------------------------- |
|
521 | 545 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
522 | 546 | WHEN OTHERS => NULL; |
@@ -567,27 +591,39 BEGIN -- beh | |||
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567 | 591 | reg_wp.burst_f2 <= apbi.pwdata(6); |
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568 | 592 | reg_wp.run <= apbi.pwdata(7); |
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569 | 593 | --22 |
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570 |
WHEN "010111" => reg_wp.addr_ |
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571 |
WHEN "011000" => reg_wp.addr_ |
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572 |
WHEN "011001" => reg_wp.addr_ |
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573 |
WHEN "011010" => reg_wp.addr_ |
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594 | WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata; | |
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595 | WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata; | |
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596 | WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata; | |
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597 | WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata; | |
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598 | WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata; | |
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599 | WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; | |
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600 | WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; | |
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601 | WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; | |
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574 | 602 | --26 |
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575 | WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
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576 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
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577 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
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578 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
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579 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
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580 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
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581 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
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582 | WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
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583 |
WHEN " |
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584 |
WHEN " |
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585 |
WHEN " |
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586 |
WHEN "1000 |
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587 |
WHEN "10000 |
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588 |
WHEN "100 |
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589 |
WHEN "100 |
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590 |
WHEN "1001 |
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603 | WHEN "011111" => | |
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604 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP | |
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605 | reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I); | |
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606 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); | |
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607 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); | |
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608 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); | |
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609 | END LOOP all_reg_wp_status_bit; | |
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610 | ||
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611 | WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
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612 | WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
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613 | WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
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614 | WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
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615 | WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
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616 | WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
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617 | WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
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618 | WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
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619 | ||
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620 | WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); | |
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621 | ||
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622 | ||
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623 | ||
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624 | ||
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625 | ||
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626 | -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
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591 | 627 | -- |
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592 | 628 | WHEN OTHERS => NULL; |
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593 | 629 | END CASE; |
@@ -622,7 +658,7 BEGIN -- beh | |||
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622 | 658 | ----------------------------------------------------------------------------- |
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623 | 659 | -- IRQ |
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624 | 660 | ----------------------------------------------------------------------------- |
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625 |
irq_wfp_reg_s <= status_ |
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661 | irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err; | |
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626 | 662 | |
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627 | 663 | PROCESS (HCLK, HRESETn) |
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628 | 664 | BEGIN -- PROCESS |
@@ -706,16 +742,29 BEGIN -- beh | |||
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706 | 742 | matrix_time => matrix_time_f2); |
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707 | 743 | |
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708 | 744 | ----------------------------------------------------------------------------- |
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709 | debug_signal(31 DOWNTO 12) <= (OTHERS => '0'); | |
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710 | debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11 | |
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711 | reg_sp.status_error_input_fifo_write(2) &--10 | |
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712 | reg_sp.status_error_input_fifo_write(1) &--9 | |
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713 | reg_sp.status_error_input_fifo_write(0) &--8 | |
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714 | reg_sp.status_error_buffer_full & | |
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715 | '0' & | |
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716 | -- reg_sp.status_error_bad_component_error & --7 6 | |
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717 | reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4 | |
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718 | reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2 | |
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719 | reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0 | |
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745 | all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE | |
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746 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer | |
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747 | PORT MAP ( | |
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748 | clk => HCLK, | |
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749 | rstn => HRESETn, | |
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750 | ||
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751 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
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752 | reg0_ready_matrix => reg_ready_buffer_f(2*I), | |
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753 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), | |
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754 | reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), | |
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720 | 755 | |
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721 | END beh; | |
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756 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), | |
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757 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), | |
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758 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), | |
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759 | reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), | |
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760 | ||
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761 | ready_matrix => wfp_ready_buffer(I), | |
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762 | status_ready_matrix => wfp_status_buffer_ready(I), | |
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763 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), | |
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764 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) | |
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765 | ); | |
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766 | ||
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767 | END GENERATE all_wfp_pointer; | |
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768 | ----------------------------------------------------------------------------- | |
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769 | ||
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770 | END beh; No newline at end of file |
@@ -258,7 +258,6 PACKAGE lpp_lfr_pkg IS | |||
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258 | 258 | COMPONENT lpp_lfr_apbreg |
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259 | 259 | GENERIC ( |
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260 | 260 | nb_data_by_buffer_size : INTEGER; |
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261 | nb_word_by_buffer_size : INTEGER; | |
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262 | 261 | nb_snapshot_param_size : INTEGER; |
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263 | 262 | delta_vector_size : INTEGER; |
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264 | 263 | delta_vector_size_f0_2 : INTEGER; |
@@ -291,9 +290,6 PACKAGE lpp_lfr_pkg IS | |||
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291 | 290 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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292 | 291 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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293 | 292 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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294 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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295 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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296 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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297 | 293 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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298 | 294 | data_shaping_BW : OUT STD_LOGIC; |
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299 | 295 | data_shaping_SP0 : OUT STD_LOGIC; |
@@ -307,7 +303,6 PACKAGE lpp_lfr_pkg IS | |||
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307 | 303 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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308 | 304 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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309 | 305 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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310 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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311 | 306 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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312 | 307 | enable_f0 : OUT STD_LOGIC; |
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313 | 308 | enable_f1 : OUT STD_LOGIC; |
@@ -317,12 +312,13 PACKAGE lpp_lfr_pkg IS | |||
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317 | 312 | burst_f1 : OUT STD_LOGIC; |
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318 | 313 | burst_f2 : OUT STD_LOGIC; |
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319 | 314 | run : OUT STD_LOGIC; |
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320 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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321 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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322 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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323 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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324 | 315 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
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325 |
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316 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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317 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
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326 | 322 | END COMPONENT; |
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327 | 323 | |
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328 | 324 | COMPONENT lpp_top_ms |
@@ -44,7 +44,7 ENTITY lpp_waveform IS | |||
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44 | 44 | tech : INTEGER := inferred; |
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45 | 45 | data_size : INTEGER := 96; --16*6 |
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46 | 46 | nb_data_by_buffer_size : INTEGER := 11; |
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47 | nb_word_by_buffer_size : INTEGER := 11; | |
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47 | -- nb_word_by_buffer_size : INTEGER := 11; | |
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48 | 48 | nb_snapshot_param_size : INTEGER := 11; |
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49 | 49 | delta_vector_size : INTEGER := 20; |
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50 | 50 | delta_vector_size_f0_2 : INTEGER := 3); |
@@ -76,31 +76,36 ENTITY lpp_waveform IS | |||
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76 | 76 | burst_f2 : IN STD_LOGIC; |
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77 | 77 | |
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78 | 78 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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79 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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79 | -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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80 | 80 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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81 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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82 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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83 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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81 | ||
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84 | 82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
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83 | ||
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84 | ||
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85 | -- REG DMA | |
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86 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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87 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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88 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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89 | ||
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90 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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91 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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92 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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93 | ||
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85 | 94 |
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86 | 95 | -- INPUT |
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87 | 96 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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88 | 97 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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89 | 98 | |
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90 | 99 | --f0 |
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91 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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92 | 100 | data_f0_in_valid : IN STD_LOGIC; |
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93 | 101 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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94 | 102 | --f1 |
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95 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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96 | 103 | data_f1_in_valid : IN STD_LOGIC; |
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97 | 104 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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98 | 105 | --f2 |
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99 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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100 | 106 | data_f2_in_valid : IN STD_LOGIC; |
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101 | 107 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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102 | 108 | --f3 |
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103 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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104 | 109 | data_f3_in_valid : IN STD_LOGIC; |
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105 | 110 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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106 | 111 | |
@@ -110,7 +115,7 ENTITY lpp_waveform IS | |||
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110 | 115 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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111 | 116 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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112 | 117 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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113 |
dma_buffer_new : |
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118 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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114 | 119 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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115 | 120 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); |
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116 | 121 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -178,9 +183,10 ARCHITECTURE beh OF lpp_waveform IS | |||
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178 | 183 | SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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179 | 184 | |
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180 | 185 | -- |
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186 | SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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187 | SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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181 | 188 | |
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182 |
SIGNAL |
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183 | ||
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189 | SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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184 | 190 | |
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185 | 191 | BEGIN -- beh |
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186 | 192 | |
@@ -357,19 +363,6 BEGIN -- beh | |||
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357 | 363 | END GENERATE all_sample_of_time_out; |
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358 | 364 | END GENERATE all_bit_of_time_out; |
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359 | 365 | |
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360 | -- DEBUG -- | |
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361 | --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; | |
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362 | --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; | |
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363 | --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; | |
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364 | --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; | |
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365 | ||
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366 | --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE | |
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367 | -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE | |
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368 | -- time_out_2(J, I) <= time_out_debug(J)(I); | |
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369 | -- END GENERATE all_sample_of_time_out; | |
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370 | --END GENERATE all_bit_of_time_out; | |
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371 | -- DEBUG -- | |
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372 | ||
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373 | 366 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter |
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374 | 367 | GENERIC MAP (tech => tech, |
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375 | 368 | nb_data_by_buffer_size => nb_data_by_buffer_size) |
@@ -386,62 +379,16 BEGIN -- beh | |||
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386 | 379 | data_out => wdata, |
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387 | 380 | data_out_wen => data_wen, |
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388 | 381 | full_almost => full_almost, |
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389 |
full => full |
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382 | full => full, | |
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383 | ||
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384 | time_out => arbiter_time_out, | |
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385 | time_out_new => arbiter_time_out_new | |
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386 | ||
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387 | ); | |
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390 | 388 | |
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391 | 389 | ----------------------------------------------------------------------------- |
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392 | -- DEBUG -- SNAPSHOT IN | |
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393 | --debug_f0_data_fifo_in_valid <= NOT data_wen(0); | |
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394 | --debug_f0_data_fifo_in <= wdata; | |
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395 | --debug_f1_data_fifo_in_valid <= NOT data_wen(1); | |
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396 | --debug_f1_data_fifo_in <= wdata; | |
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397 | --debug_f2_data_fifo_in_valid <= NOT data_wen(2); | |
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398 | --debug_f2_data_fifo_in <= wdata; | |
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399 | --debug_f3_data_fifo_in_valid <= NOT data_wen(3); | |
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400 | --debug_f3_data_fifo_in <= wdata;s | |
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401 | 390 | ----------------------------------------------------------------------------- |
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402 | 391 | |
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403 | ||
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404 | -- lpp_fifo_4_shared_1: lpp_fifo_4_shared | |
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405 | -- GENERIC MAP ( | |
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406 | -- tech => tech, | |
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407 | -- Mem_use => use_RAM, | |
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408 | -- EMPTY_ALMOST_LIMIT => 16, | |
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409 | -- FULL_ALMOST_LIMIT => 5, | |
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410 | -- DataSz => 32, | |
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411 | -- AddrSz => 7 | |
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412 | -- ) | |
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413 | -- PORT MAP ( | |
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414 | -- clk => clk, | |
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415 | -- rstn => rstn, | |
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416 | -- run => run, | |
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417 | -- empty_almost => s_empty_almost, | |
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418 | -- empty => s_empty, | |
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419 | -- r_en => s_data_ren, | |
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420 | -- r_data => s_rdata, | |
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421 | -- full_almost => full_almost, | |
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422 | -- full => full, | |
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423 | -- w_en => data_wen, | |
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424 | -- w_data => wdata); | |
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425 | ||
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426 | --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1 | |
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427 | -- PORT MAP ( | |
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428 | -- clk => clk, | |
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429 | -- rstn => rstn, | |
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430 | -- run => run, | |
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431 | -- o_empty_almost => empty_almost, | |
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432 | -- o_empty => empty, | |
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433 | ||
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434 | -- o_data_ren => data_ren, | |
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435 | -- o_rdata_0 => data_f0_data_out, | |
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436 | -- o_rdata_1 => data_f1_data_out, | |
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437 | -- o_rdata_2 => data_f2_data_out, | |
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438 | -- o_rdata_3 => data_f3_data_out, | |
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439 | ||
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440 | -- i_empty_almost => s_empty_almost, | |
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441 | -- i_empty => s_empty, | |
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442 | -- i_data_ren => s_data_ren, | |
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443 | -- i_rdata => s_rdata); | |
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444 | ||
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445 | 392 | generate_all_fifo: FOR I IN 0 TO 3 GENERATE |
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446 | 393 | lpp_fifo_1: lpp_fifo |
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447 | 394 | GENERIC MAP ( |
@@ -468,86 +415,34 BEGIN -- beh | |||
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468 | 415 | |
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469 | 416 | END GENERATE generate_all_fifo; |
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470 | 417 | |
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471 | ||
|
472 | ----empty <= s_empty; | |
|
473 | ----empty_almost <= s_empty_almost; | |
|
474 | ----s_data_ren <= data_ren; | |
|
475 | ||
|
476 | --data_f0_data_out <= s_rdata_v(31 downto 0); | |
|
477 | --data_f1_data_out <= s_rdata_v(31+32 downto 0+32); | |
|
478 | --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); | |
|
479 | --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); | |
|
480 | ||
|
481 | --data_ren <= data_f3_data_out_ren & | |
|
482 | -- data_f2_data_out_ren & | |
|
483 | -- data_f1_data_out_ren & | |
|
484 | -- data_f0_data_out_ren; | |
|
485 | ||
|
486 | --lpp_waveform_gen_address_1 : lpp_waveform_genaddress | |
|
487 | -- GENERIC MAP ( | |
|
488 | -- nb_data_by_buffer_size => nb_word_by_buffer_size) | |
|
489 | -- PORT MAP ( | |
|
490 | -- clk => clk, | |
|
491 | -- rstn => rstn, | |
|
492 | -- run => run, | |
|
493 | ||
|
494 | -- ------------------------------------------------------------------------- | |
|
495 | -- -- CONFIG | |
|
496 | -- ------------------------------------------------------------------------- | |
|
497 | -- nb_data_by_buffer => nb_word_by_buffer, | |
|
498 | ||
|
499 | -- addr_data_f0 => addr_data_f0, | |
|
500 | -- addr_data_f1 => addr_data_f1, | |
|
501 | -- addr_data_f2 => addr_data_f2, | |
|
502 | -- addr_data_f3 => addr_data_f3, | |
|
503 | -- ------------------------------------------------------------------------- | |
|
504 | -- -- CTRL | |
|
505 | -- ------------------------------------------------------------------------- | |
|
506 | -- -- IN | |
|
507 | -- empty => empty, | |
|
508 | -- empty_almost => empty_almost, | |
|
509 | -- data_ren => data_ren, | |
|
510 | ||
|
511 | -- ------------------------------------------------------------------------- | |
|
512 | -- -- STATUS | |
|
513 | -- ------------------------------------------------------------------------- | |
|
514 | -- status_full => status_full_s, | |
|
515 | -- status_full_ack => status_full_ack, | |
|
516 | -- status_full_err => status_full_err, | |
|
517 | ||
|
518 | -- ------------------------------------------------------------------------- | |
|
519 | -- -- ADDR DATA OUT | |
|
520 | -- ------------------------------------------------------------------------- | |
|
521 | -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, | |
|
522 | -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, | |
|
523 | -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, | |
|
524 | -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, | |
|
525 | ||
|
526 | -- data_f0_data_out_valid => data_f0_data_out_valid, | |
|
527 | -- data_f1_data_out_valid => data_f1_data_out_valid, | |
|
528 | -- data_f2_data_out_valid => data_f2_data_out_valid, | |
|
529 | -- data_f3_data_out_valid => data_f3_data_out_valid, | |
|
530 | ||
|
531 | -- data_f0_addr_out => data_f0_addr_out, | |
|
532 | -- data_f1_addr_out => data_f1_addr_out, | |
|
533 | -- data_f2_addr_out => data_f2_addr_out, | |
|
534 | -- data_f3_addr_out => data_f3_addr_out | |
|
535 | -- ); | |
|
536 | --status_full <= status_full_s; | |
|
537 | ||
|
538 | ||
|
539 | 418 | ----------------------------------------------------------------------------- |
|
540 | 419 | -- |
|
541 | 420 | ----------------------------------------------------------------------------- |
|
542 | 421 | |
|
543 | 422 | all_channel: FOR I IN 3 DOWNTO 0 GENERATE |
|
423 | ||
|
424 | PROCESS (clk, rstn) | |
|
425 | BEGIN | |
|
426 | IF rstn = '0' THEN | |
|
427 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); | |
|
428 | ELSIF clk'event AND clk = '1' THEN | |
|
429 | IF run = '0' THEN | |
|
430 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); | |
|
431 | ELSE | |
|
432 | IF arbiter_time_out_new(I) = '0' THEN | |
|
433 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; | |
|
434 | END IF; | |
|
435 | END IF; | |
|
436 | END IF; | |
|
437 | END PROCESS; | |
|
438 | ||
|
544 | 439 |
|
|
545 | 440 | PORT MAP ( |
|
546 | 441 | clk => clk, |
|
547 | 442 | rstn => rstn, |
|
548 | 443 | run => run, |
|
549 | 444 | |
|
550 |
fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), |
|
|
445 | fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), | |
|
551 | 446 | |
|
552 | 447 | fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), |
|
553 | 448 | fifo_empty => empty(I), |
@@ -565,7 +460,7 BEGIN -- beh | |||
|
565 | 460 | |
|
566 | 461 | status_buffer_ready => status_buffer_ready(I), -- TODO |
|
567 | 462 | addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO |
|
568 |
length_buffer => length_buffer |
|
|
463 | length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO | |
|
569 | 464 | ready_buffer => ready_buffer(I), -- TODO |
|
570 | 465 | buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO |
|
571 | 466 | error_buffer_full => error_buffer_full(I)); -- TODO |
@@ -57,23 +57,19 BEGIN | |||
|
57 | 57 | error <= '0'; |
|
58 | 58 | time_out <= (OTHERS => '0'); |
|
59 | 59 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
60 | IF run = '1' THEN | |
|
60 | 61 | CASE state IS |
|
61 | 62 | WHEN IDLE => |
|
62 | 63 | |
|
63 |
valid_out <= |
|
|
64 | valid_out <= valid_in; | |
|
64 | 65 | error <= '0'; |
|
65 | IF run = '1' AND valid_in = '1' THEN | |
|
66 | time_out <= time_in; | |
|
67 | ||
|
68 | IF valid_in = '1' THEN | |
|
66 | 69 |
state |
|
67 | valid_out <= '1'; | |
|
68 | time_out <= time_in; | |
|
69 | 70 | END IF; |
|
70 | 71 | |
|
71 | 72 | WHEN VALID => |
|
72 | IF run = '0' THEN | |
|
73 | state <= IDLE; | |
|
74 | valid_out <= '0'; | |
|
75 | error <= '0'; | |
|
76 | ELSE | |
|
77 | 73 | IF valid_in = '1' THEN |
|
78 | 74 | IF ack_in = '1' THEN |
|
79 | 75 | state <= VALID; |
@@ -88,10 +84,16 BEGIN | |||
|
88 | 84 | state <= IDLE; |
|
89 | 85 | valid_out <= '0'; |
|
90 | 86 | END IF; |
|
91 | END IF; | |
|
92 | 87 | |
|
93 | 88 | WHEN OTHERS => NULL; |
|
94 | 89 | END CASE; |
|
90 | ||
|
91 | ELSE | |
|
92 | state <= IDLE; | |
|
93 | valid_out <= '0'; | |
|
94 | error <= '0'; | |
|
95 | time_out <= (OTHERS => '0'); | |
|
96 | END IF; | |
|
95 | 97 | END IF; |
|
96 | 98 | END PROCESS FSM_SELECT_ADDRESS; |
|
97 | 99 |
@@ -44,6 +44,7 ENTITY lpp_waveform_fifo_arbiter IS | |||
|
44 | 44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
45 | 45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
46 | 46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
47 | ||
|
47 | 48 |
|
|
48 | 49 | |
|
49 | 50 | --------------------------------------------------------------------------- |
@@ -52,29 +53,31 ENTITY lpp_waveform_fifo_arbiter IS | |||
|
52 | 53 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | 54 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
54 | 55 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
55 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
56 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
57 | ||
|
58 | --------------------------------------------------------------------------- | |
|
59 | -- TIME INTERFACE (OUTPUT) | |
|
60 | --------------------------------------------------------------------------- | |
|
61 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
62 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
56 | 63 |
|
|
57 | 64 |
|
|
58 | 65 | END ENTITY; |
|
59 | 66 | |
|
60 | 67 | |
|
61 | 68 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
|
62 |
TYPE state_type_fifo_arbiter IS (IDLE, |
|
|
69 | TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST); | |
|
63 | 70 | SIGNAL state : state_type_fifo_arbiter; |
|
64 | 71 | |
|
65 | 72 | ----------------------------------------------------------------------------- |
|
66 | 73 | -- DATA MUX |
|
67 | 74 | ----------------------------------------------------------------------------- |
|
68 | SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
69 | SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
70 | SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
71 | SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
72 | 75 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 |
SIGNAL data_0 : WORD_VECTOR( |
|
|
74 |
SIGNAL data_1 : WORD_VECTOR( |
|
|
75 |
SIGNAL data_2 : WORD_VECTOR( |
|
|
76 |
SIGNAL data_3 : WORD_VECTOR( |
|
|
77 |
SIGNAL data_sel : WORD_VECTOR( |
|
|
76 | SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0); | |
|
77 | SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0); | |
|
78 | SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0); | |
|
79 | SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0); | |
|
80 | SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0); | |
|
78 | 81 | |
|
79 | 82 | ----------------------------------------------------------------------------- |
|
80 | 83 | -- RR and SELECTION |
@@ -93,13 +96,7 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||
|
93 | 96 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
94 | 97 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
95 | 98 | |
|
96 | --SIGNAL shift_data_enable : STD_LOGIC; | |
|
97 | --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
98 | --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
99 | ||
|
100 | --SIGNAL shift_time_enable : STD_LOGIC; | |
|
101 | --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
102 | --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
99 | SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
103 | 100 | |
|
104 | 101 | BEGIN |
|
105 | 102 | |
@@ -114,43 +111,39 BEGIN | |||
|
114 | 111 | data_out_wen <= (OTHERS => '1'); |
|
115 | 112 | sel_ack <= '0'; |
|
116 | 113 | state <= IDLE; |
|
114 | time_out <= (OTHERS => '0'); | |
|
115 | time_out_new <= (OTHERS => '0'); | |
|
117 | 116 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
118 | 117 | count_enable <= '0'; |
|
119 | 118 | data_in_ack <= (OTHERS => '0'); |
|
120 | 119 | data_out_wen <= (OTHERS => '1'); |
|
121 | 120 | sel_ack <= '0'; |
|
121 | time_out_new <= (OTHERS => '0'); | |
|
122 | 122 | IF run = '0' THEN |
|
123 | 123 | state <= IDLE; |
|
124 | time_out <= (OTHERS => '0'); | |
|
124 | 125 | ELSE |
|
125 | 126 | CASE state IS |
|
126 | 127 | WHEN IDLE => |
|
127 | 128 | IF no_sel = '0' THEN |
|
128 |
state <= |
|
|
129 | state <= DATA1; | |
|
129 | 130 | END IF; |
|
130 |
WHEN |
|
|
131 | WHEN DATA1 => | |
|
131 | 132 | count_enable <= '1'; |
|
132 | 133 | IF UNSIGNED(count) = 0 THEN |
|
133 |
|
|
|
134 | time_out <= time_sel; | |
|
135 | time_out_new <= sel; | |
|
136 | END IF; | |
|
134 | 137 |
|
|
135 | 138 |
|
|
136 | ELSE | |
|
137 | state <= DATA1; | |
|
138 | END IF; | |
|
139 | WHEN TIME2 => | |
|
140 | data_out_wen <= NOT sel; | |
|
141 | data_out <= data_sel(1) ; | |
|
142 | state <= DATA1; | |
|
143 | WHEN DATA1 => | |
|
144 | data_out_wen <= NOT sel; | |
|
145 | data_out <= data_sel(2); | |
|
146 | 139 | state <= DATA2; |
|
147 | 140 | WHEN DATA2 => |
|
148 | 141 | data_out_wen <= NOT sel; |
|
149 |
data_out <= data_sel( |
|
|
142 | data_out <= data_sel(1); | |
|
150 | 143 | state <= DATA3; |
|
151 | 144 | WHEN DATA3 => |
|
152 | 145 | data_out_wen <= NOT sel; |
|
153 |
data_out <= data_sel( |
|
|
146 | data_out <= data_sel(2); | |
|
154 | 147 | state <= LAST; |
|
155 | 148 | data_in_ack <= sel; |
|
156 | 149 | WHEN LAST => |
@@ -164,100 +157,16 BEGIN | |||
|
164 | 157 | END PROCESS; |
|
165 | 158 | ----------------------------------------------------------------------------- |
|
166 | 159 | |
|
167 | ||
|
168 | --PROCESS (clk, rstn) | |
|
169 | --BEGIN -- PROCESS | |
|
170 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
171 | -- count_enable <= '0'; | |
|
172 | -- shift_time_enable <= '0'; | |
|
173 | -- shift_data_enable <= '0'; | |
|
174 | -- data_in_ack <= (OTHERS => '0'); | |
|
175 | -- data_out_wen <= (OTHERS => '1'); | |
|
176 | -- sel_ack <= '0'; | |
|
177 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
178 | -- IF run = '0' OR no_sel = '1' THEN | |
|
179 | -- count_enable <= '0'; | |
|
180 | -- shift_time_enable <= '0'; | |
|
181 | -- shift_data_enable <= '0'; | |
|
182 | -- data_in_ack <= (OTHERS => '0'); | |
|
183 | -- data_out_wen <= (OTHERS => '1'); | |
|
184 | -- sel_ack <= '0'; | |
|
185 | -- ELSE | |
|
186 | -- --COUNT | |
|
187 | -- IF shift_data_s = "10" THEN | |
|
188 | -- count_enable <= '1'; | |
|
189 | -- ELSE | |
|
190 | -- count_enable <= '0'; | |
|
191 | -- END IF; | |
|
192 | -- --DATA | |
|
193 | -- IF shift_time_s = "10" THEN | |
|
194 | -- shift_data_enable <= '1'; | |
|
195 | -- ELSE | |
|
196 | -- shift_data_enable <= '0'; | |
|
197 | -- END IF; | |
|
198 | ||
|
199 | -- --TIME | |
|
200 | -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR | |
|
201 | -- shift_time_s = "00" OR | |
|
202 | -- shift_time_s = "01" | |
|
203 | -- THEN | |
|
204 | -- shift_time_enable <= '1'; | |
|
205 | -- ELSE | |
|
206 | -- shift_time_enable <= '0'; | |
|
207 | -- END IF; | |
|
208 | ||
|
209 | -- --ACK | |
|
210 | -- IF shift_data_s = "10" THEN | |
|
211 | -- data_in_ack <= sel; | |
|
212 | -- sel_ack <= '1'; | |
|
213 | -- ELSE | |
|
214 | -- data_in_ack <= (OTHERS => '0'); | |
|
215 | -- sel_ack <= '0'; | |
|
216 | -- END IF; | |
|
217 | ||
|
218 | -- --VALID OUT | |
|
219 | -- all_wen: FOR I IN 3 DOWNTO 0 LOOP | |
|
220 | -- IF sel(I) = '1' AND count_enable = '0' THEN | |
|
221 | -- data_out_wen(I) <= '0'; | |
|
222 | -- ELSE | |
|
223 | -- data_out_wen(I) <= '1'; | |
|
224 | -- END IF; | |
|
225 | -- END LOOP all_wen; | |
|
226 | ||
|
227 | -- END IF; | |
|
228 | -- END IF; | |
|
229 | --END PROCESS; | |
|
230 | ||
|
231 | 160 | ----------------------------------------------------------------------------- |
|
232 | 161 | -- DATA MUX |
|
233 | 162 | ----------------------------------------------------------------------------- |
|
234 | all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE | |
|
235 | I_time_in: IF I < 48 GENERATE | |
|
236 | data_0_v(I) <= time_in(0,I); | |
|
237 | data_1_v(I) <= time_in(1,I); | |
|
238 | data_2_v(I) <= time_in(2,I); | |
|
239 | data_3_v(I) <= time_in(3,I); | |
|
240 | END GENERATE I_time_in; | |
|
241 | I_null: IF (I > 47) AND (I < 32*2) GENERATE | |
|
242 | data_0_v(I) <= '0'; | |
|
243 | data_1_v(I) <= '0'; | |
|
244 | data_2_v(I) <= '0'; | |
|
245 | data_3_v(I) <= '0'; | |
|
246 | END GENERATE I_null; | |
|
247 | I_data_in: IF I > 32*2-1 GENERATE | |
|
248 | data_0_v(I) <= data_in(0,I-32*2); | |
|
249 | data_1_v(I) <= data_in(1,I-32*2); | |
|
250 | data_2_v(I) <= data_in(2,I-32*2); | |
|
251 | data_3_v(I) <= data_in(3,I-32*2); | |
|
252 | END GENERATE I_data_in; | |
|
253 | END GENERATE all_bit_data_in; | |
|
254 | 163 | |
|
255 |
all_word: FOR J IN |
|
|
164 | all_word: FOR J IN 2 DOWNTO 0 GENERATE | |
|
256 | 165 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE |
|
257 |
data_0(J)(I) <= data_ |
|
|
258 |
data_1(J)(I) <= data_ |
|
|
259 |
data_2(J)(I) <= data_ |
|
|
260 |
data_3(J)(I) <= data_ |
|
|
166 | data_0(J)(I) <= data_in(0,I+32*J); | |
|
167 | data_1(J)(I) <= data_in(1,I+32*J); | |
|
168 | data_2(J)(I) <= data_in(2,I+32*J); | |
|
169 | data_3(J)(I) <= data_in(3,I+32*J); | |
|
261 | 170 | END GENERATE all_data_bit; |
|
262 | 171 | END GENERATE all_word; |
|
263 | 172 | |
@@ -266,18 +175,18 BEGIN | |||
|
266 | 175 | data_2 WHEN sel(2) = '1' ELSE |
|
267 | 176 | data_3; |
|
268 | 177 | |
|
269 | --data_out <= data_sel(0) WHEN shift_time = "00" ELSE | |
|
270 | -- data_sel(1) WHEN shift_time = "01" ELSE | |
|
271 | -- data_sel(2) WHEN shift_data = "00" ELSE | |
|
272 | -- data_sel(3) WHEN shift_data = "01" ELSE | |
|
273 | -- data_sel(4); | |
|
178 | all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE | |
|
179 | time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE | |
|
180 | time_in(1,I) WHEN sel(1) = '1' ELSE | |
|
181 | time_in(2,I) WHEN sel(2) = '1' ELSE | |
|
182 | time_in(3,I); | |
|
183 | END GENERATE all_time_bit; | |
|
274 | 184 | |
|
275 | 185 | |
|
276 | 186 | ----------------------------------------------------------------------------- |
|
277 | 187 | -- RR and SELECTION |
|
278 | 188 | ----------------------------------------------------------------------------- |
|
279 | 189 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
|
280 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); | |
|
281 | 190 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); |
|
282 | 191 | END GENERATE all_input_rr; |
|
283 | 192 | |
@@ -286,9 +195,7 BEGIN | |||
|
286 | 195 | clk => clk, |
|
287 | 196 | rstn => rstn, |
|
288 | 197 | in_valid => valid_in_rr, |
|
289 |
out_grant => sel_s); |
|
|
290 | ||
|
291 | -- sel <= sel_s; | |
|
198 | out_grant => sel_s); | |
|
292 | 199 | |
|
293 | 200 | PROCESS (clk, rstn) |
|
294 | 201 | BEGIN -- PROCESS |
@@ -296,14 +203,7 BEGIN | |||
|
296 | 203 | sel <= "0000"; |
|
297 | 204 | sel_reg <= '0'; |
|
298 | 205 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
299 | -- sel_reg | |
|
300 | -- sel_ack | |
|
301 | -- sel_s | |
|
302 | -- sel = "0000 " | |
|
303 | --sel <= sel_s; | |
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304 | IF sel_reg = '0' OR sel_ack = '1' | |
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305 | --OR shift_data_s = "10" | |
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306 | THEN | |
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206 | IF sel_reg = '0' OR sel_ack = '1' THEN | |
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307 | 207 | sel <= sel_s; |
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308 | 208 | IF sel_s = "0000" THEN |
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309 | 209 | sel_reg <= '0'; |
@@ -333,35 +233,6 BEGIN | |||
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333 | 233 | data => count, |
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334 | 234 | data_s => count_s); |
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335 | 235 | |
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336 | --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg | |
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337 | -- GENERIC MAP ( | |
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338 | -- data_size => 2, | |
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339 | -- data_nb => 4) | |
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340 | -- PORT MAP ( | |
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341 | -- clk => clk, | |
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342 | -- rstn => rstn, | |
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343 | -- run => run, | |
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344 | -- max_count => "10", -- 2 | |
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345 | -- enable => shift_data_enable, | |
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346 | -- sel => sel, | |
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347 | -- data => shift_data, | |
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348 | -- data_s => shift_data_s); | |
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349 | ||
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350 | ||
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351 | --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg | |
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352 | -- GENERIC MAP ( | |
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353 | -- data_size => 2, | |
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354 | -- data_nb => 4) | |
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355 | -- PORT MAP ( | |
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356 | -- clk => clk, | |
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357 | -- rstn => rstn, | |
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358 | -- run => run, | |
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359 | -- max_count => "10", -- 2 | |
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360 | -- enable => shift_time_enable, | |
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361 | -- sel => sel, | |
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362 | -- data => shift_time, | |
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363 | -- data_s => shift_time_s); | |
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364 | ||
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365 | 236 | |
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366 | 237 | |
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367 | 238 | |
@@ -391,4 +262,3 END ARCHITECTURE; | |||
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391 | 262 | |
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392 | 263 | |
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393 | 264 | |
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394 |
@@ -105,7 +105,6 PACKAGE lpp_waveform_pkg IS | |||
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105 | 105 | tech : INTEGER; |
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106 | 106 | data_size : INTEGER; |
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107 | 107 | nb_data_by_buffer_size : INTEGER; |
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108 | nb_word_by_buffer_size : INTEGER; | |
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109 | 108 | nb_snapshot_param_size : INTEGER; |
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110 | 109 | delta_vector_size : INTEGER; |
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111 | 110 | delta_vector_size_f0_2 : INTEGER); |
@@ -127,24 +126,22 PACKAGE lpp_waveform_pkg IS | |||
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127 | 126 | burst_f1 : IN STD_LOGIC; |
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128 | 127 | burst_f2 : IN STD_LOGIC; |
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129 | 128 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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131 | 129 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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134 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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135 | 130 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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131 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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133 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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134 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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136 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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136 | 137 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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137 | 138 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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138 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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139 | 139 | data_f0_in_valid : IN STD_LOGIC; |
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140 | 140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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141 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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142 | 141 | data_f1_in_valid : IN STD_LOGIC; |
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143 | 142 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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144 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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145 | 143 | data_f2_in_valid : IN STD_LOGIC; |
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146 | 144 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
147 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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148 | 145 | data_f3_in_valid : IN STD_LOGIC; |
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149 | 146 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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150 | 147 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -168,26 +165,14 PACKAGE lpp_waveform_pkg IS | |||
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168 | 165 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
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169 | 166 | data_f3_data_out_ren : IN STD_LOGIC; |
|
170 | 167 | |
|
171 | --debug | |
|
172 |
|
|
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173 |
|
|
|
174 | --debug_f0_data_valid : OUT STD_LOGIC; | |
|
175 |
|
|
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176 | --debug_f1_data_valid : OUT STD_LOGIC; | |
|
177 |
|
|
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178 | --debug_f2_data_valid : OUT STD_LOGIC; | |
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179 | --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
180 | --debug_f3_data_valid : OUT STD_LOGIC; | |
|
181 | ||
|
182 | ----debug FIFO IN | |
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183 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
184 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
|
185 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
186 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
|
187 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
188 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
|
189 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
190 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC | |
|
168 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
169 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
170 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
171 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
172 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
173 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); | |
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174 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
175 | dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
191 | 176 | ); |
|
192 | 177 | END COMPONENT; |
|
193 | 178 | |
@@ -243,7 +228,10 PACKAGE lpp_waveform_pkg IS | |||
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243 | 228 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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244 | 229 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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245 | 230 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
246 |
full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
|
231 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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232 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
233 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
234 | ); | |
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247 | 235 | END COMPONENT; |
|
248 | 236 | |
|
249 | 237 | COMPONENT lpp_waveform_fifo |
@@ -370,7 +358,9 PACKAGE lpp_waveform_pkg IS | |||
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370 | 358 | enable : IN STD_LOGIC; |
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371 | 359 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); |
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372 | 360 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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373 |
data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) |
|
|
361 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
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362 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
363 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
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374 | 364 | END COMPONENT; |
|
375 | 365 | |
|
376 | 366 | COMPONENT lpp_waveform_fsmdma |
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