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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC
62 data_shaping_BW : OUT STD_LOGIC
63 --
63 --
64 --
64 --
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
67
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
69
70 --debug
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
79
80 ---- debug FIFO_IN
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
89
90 ----debug FIFO OUT
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
99
100 ----debug DMA IN
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
109 );
110 END lpp_lfr;
110 END lpp_lfr;
111
111
112 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
115 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
121 --
121 --
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 --
125 --
126 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f0_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
130 --
130 --
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 --
135 --
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139
139
140 -- SM
140 -- SM
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162
162
163 -- WFP
163 -- WFP
164 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173
173
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
175 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
176 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
175 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
177 SIGNAL enable_f0 : STD_LOGIC;
176 SIGNAL enable_f0 : STD_LOGIC;
178 SIGNAL enable_f1 : STD_LOGIC;
177 SIGNAL enable_f1 : STD_LOGIC;
179 SIGNAL enable_f2 : STD_LOGIC;
178 SIGNAL enable_f2 : STD_LOGIC;
180 SIGNAL enable_f3 : STD_LOGIC;
179 SIGNAL enable_f3 : STD_LOGIC;
181 SIGNAL burst_f0 : STD_LOGIC;
180 SIGNAL burst_f0 : STD_LOGIC;
182 SIGNAL burst_f1 : STD_LOGIC;
181 SIGNAL burst_f1 : STD_LOGIC;
183 SIGNAL burst_f2 : STD_LOGIC;
182 SIGNAL burst_f2 : STD_LOGIC;
184 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
188
183
189 SIGNAL run : STD_LOGIC;
184 SIGNAL run : STD_LOGIC;
190 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
185 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
191
186
192 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f0_data_out_valid : STD_LOGIC;
195 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
196 SIGNAL data_f0_data_out_ren : STD_LOGIC;
197 --f1
198 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL data_f1_data_out_valid : STD_LOGIC;
201 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
202 SIGNAL data_f1_data_out_ren : STD_LOGIC;
203 --f2
204 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL data_f2_data_out_valid : STD_LOGIC;
207 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
208 SIGNAL data_f2_data_out_ren : STD_LOGIC;
209 --f3
210 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f3_data_out_valid : STD_LOGIC;
213 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
214 SIGNAL data_f3_data_out_ren : STD_LOGIC;
215
216 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
217 --
188 --
218 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
219 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
191 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
222 --f1
193 --f1
223 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
195 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
196 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
226 --f2
197 --f2
227 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
229 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
230 --f3
201 --f3
231 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
203 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
233 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
234
205
206 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
207 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
208 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
209 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
211 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
236 -- DMA RR
213 -- DMA RR
237 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
238 SIGNAL dma_sel_valid : STD_LOGIC;
215 SIGNAL dma_sel_valid : STD_LOGIC;
239 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
241 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
242 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
243
220
244 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
245 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
246
223
247 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
248 -- DMA_REG
225 -- DMA_REG
249 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
250 SIGNAL ongoing_reg : STD_LOGIC;
227 SIGNAL ongoing_reg : STD_LOGIC;
251 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
252 SIGNAL dma_send_reg : STD_LOGIC;
229 SIGNAL dma_send_reg : STD_LOGIC;
253 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
230 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
254 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
231 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
256
233
257
234
258 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
259 -- DMA
236 -- DMA
260 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
261 SIGNAL dma_send : STD_LOGIC;
238 SIGNAL dma_send : STD_LOGIC;
262 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
239 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
263 SIGNAL dma_done : STD_LOGIC;
240 SIGNAL dma_done : STD_LOGIC;
264 SIGNAL dma_ren : STD_LOGIC;
241 SIGNAL dma_ren : STD_LOGIC;
265 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268
245
269 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
270 -- MS
247 -- MS
271 -----------------------------------------------------------------------------
248 -----------------------------------------------------------------------------
272
249
273 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL data_ms_valid : STD_LOGIC;
252 SIGNAL data_ms_valid : STD_LOGIC;
276 SIGNAL data_ms_valid_burst : STD_LOGIC;
253 SIGNAL data_ms_valid_burst : STD_LOGIC;
277 SIGNAL data_ms_ren : STD_LOGIC;
254 SIGNAL data_ms_ren : STD_LOGIC;
278 SIGNAL data_ms_done : STD_LOGIC;
255 SIGNAL data_ms_done : STD_LOGIC;
279 SIGNAL dma_ms_ongoing : STD_LOGIC;
256 SIGNAL dma_ms_ongoing : STD_LOGIC;
280
257
281 SIGNAL run_ms : STD_LOGIC;
258 SIGNAL run_ms : STD_LOGIC;
282 SIGNAL ms_softandhard_rstn : STD_LOGIC;
259 SIGNAL ms_softandhard_rstn : STD_LOGIC;
283
260
284 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
286 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
287 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
264 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
288
265
289
266
290 SIGNAL error_buffer_full : STD_LOGIC;
267 SIGNAL error_buffer_full : STD_LOGIC;
291 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
268 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
292
269
293 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
294 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
295
272
296 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
297 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
274 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
298 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
275 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
299 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
276 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
300 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
277 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
301 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
302 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
279 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
303 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
280 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
304 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
281 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
305 SIGNAL dma_grant_error : STD_LOGIC;
282 SIGNAL dma_grant_error : STD_LOGIC;
306
283
307 BEGIN
284 BEGIN
308
285
309 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
286 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
310 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
287 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
311
288
312 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
289 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
313 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
290 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
314 --END GENERATE all_channel;
291 --END GENERATE all_channel;
315
292
316 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
317 lpp_lfr_filter_1 : lpp_lfr_filter
294 lpp_lfr_filter_1 : lpp_lfr_filter
318 GENERIC MAP (
295 GENERIC MAP (
319 Mem_use => Mem_use)
296 Mem_use => Mem_use)
320 PORT MAP (
297 PORT MAP (
321 sample => sample_s,
298 sample => sample_s,
322 sample_val => sample_val,
299 sample_val => sample_val,
323 clk => clk,
300 clk => clk,
324 rstn => rstn,
301 rstn => rstn,
325 data_shaping_SP0 => data_shaping_SP0,
302 data_shaping_SP0 => data_shaping_SP0,
326 data_shaping_SP1 => data_shaping_SP1,
303 data_shaping_SP1 => data_shaping_SP1,
327 data_shaping_R0 => data_shaping_R0,
304 data_shaping_R0 => data_shaping_R0,
328 data_shaping_R1 => data_shaping_R1,
305 data_shaping_R1 => data_shaping_R1,
329 data_shaping_R2 => data_shaping_R2,
306 data_shaping_R2 => data_shaping_R2,
330 sample_f0_val => sample_f0_val,
307 sample_f0_val => sample_f0_val,
331 sample_f1_val => sample_f1_val,
308 sample_f1_val => sample_f1_val,
332 sample_f2_val => sample_f2_val,
309 sample_f2_val => sample_f2_val,
333 sample_f3_val => sample_f3_val,
310 sample_f3_val => sample_f3_val,
334 sample_f0_wdata => sample_f0_data,
311 sample_f0_wdata => sample_f0_data,
335 sample_f1_wdata => sample_f1_data,
312 sample_f1_wdata => sample_f1_data,
336 sample_f2_wdata => sample_f2_data,
313 sample_f2_wdata => sample_f2_data,
337 sample_f3_wdata => sample_f3_data);
314 sample_f3_wdata => sample_f3_data);
338
315
339 -----------------------------------------------------------------------------
316 -----------------------------------------------------------------------------
340 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
317 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
341 GENERIC MAP (
318 GENERIC MAP (
342 nb_data_by_buffer_size => nb_data_by_buffer_size,
319 nb_data_by_buffer_size => nb_data_by_buffer_size,
343 nb_word_by_buffer_size => nb_word_by_buffer_size,
320 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
344 nb_snapshot_param_size => nb_snapshot_param_size,
321 nb_snapshot_param_size => nb_snapshot_param_size,
345 delta_vector_size => delta_vector_size,
322 delta_vector_size => delta_vector_size,
346 delta_vector_size_f0_2 => delta_vector_size_f0_2,
323 delta_vector_size_f0_2 => delta_vector_size_f0_2,
347 pindex => pindex,
324 pindex => pindex,
348 paddr => paddr,
325 paddr => paddr,
349 pmask => pmask,
326 pmask => pmask,
350 pirq_ms => pirq_ms,
327 pirq_ms => pirq_ms,
351 pirq_wfp => pirq_wfp,
328 pirq_wfp => pirq_wfp,
352 top_lfr_version => top_lfr_version)
329 top_lfr_version => top_lfr_version)
353 PORT MAP (
330 PORT MAP (
354 HCLK => clk,
331 HCLK => clk,
355 HRESETn => rstn,
332 HRESETn => rstn,
356 apbi => apbi,
333 apbi => apbi,
357 apbo => apbo,
334 apbo => apbo,
358
335
359 run_ms => run_ms,
336 run_ms => run_ms,
360
337
361 ready_matrix_f0 => ready_matrix_f0,
338 ready_matrix_f0 => ready_matrix_f0,
362 ready_matrix_f1 => ready_matrix_f1,
339 ready_matrix_f1 => ready_matrix_f1,
363 ready_matrix_f2 => ready_matrix_f2,
340 ready_matrix_f2 => ready_matrix_f2,
364 error_buffer_full => error_buffer_full, -- TODO
341 error_buffer_full => error_buffer_full, -- TODO
365 error_input_fifo_write => error_input_fifo_write, -- TODO
342 error_input_fifo_write => error_input_fifo_write, -- TODO
366 status_ready_matrix_f0 => status_ready_matrix_f0,
343 status_ready_matrix_f0 => status_ready_matrix_f0,
367 status_ready_matrix_f1 => status_ready_matrix_f1,
344 status_ready_matrix_f1 => status_ready_matrix_f1,
368 status_ready_matrix_f2 => status_ready_matrix_f2,
345 status_ready_matrix_f2 => status_ready_matrix_f2,
369
346
370 matrix_time_f0 => matrix_time_f0,
347 matrix_time_f0 => matrix_time_f0,
371 matrix_time_f1 => matrix_time_f1,
348 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
349 matrix_time_f2 => matrix_time_f2,
373
350
374 addr_matrix_f0 => addr_matrix_f0,
351 addr_matrix_f0 => addr_matrix_f0,
375 addr_matrix_f1 => addr_matrix_f1,
352 addr_matrix_f1 => addr_matrix_f1,
376 addr_matrix_f2 => addr_matrix_f2,
353 addr_matrix_f2 => addr_matrix_f2,
377
354
378 length_matrix_f0 => length_matrix_f0,
355 length_matrix_f0 => length_matrix_f0,
379 length_matrix_f1 => length_matrix_f1,
356 length_matrix_f1 => length_matrix_f1,
380 length_matrix_f2 => length_matrix_f2,
357 length_matrix_f2 => length_matrix_f2,
381 -------------------------------------------------------------------------
358 -------------------------------------------------------------------------
382 status_full => status_full,
359 --status_full => status_full, -- TODo
383 status_full_ack => status_full_ack,
360 --status_full_ack => status_full_ack, -- TODo
384 status_full_err => status_full_err,
361 --status_full_err => status_full_err, -- TODo
385 status_new_err => status_new_err,
362 status_new_err => status_new_err,
386 data_shaping_BW => data_shaping_BW,
363 data_shaping_BW => data_shaping_BW,
387 data_shaping_SP0 => data_shaping_SP0,
364 data_shaping_SP0 => data_shaping_SP0,
388 data_shaping_SP1 => data_shaping_SP1,
365 data_shaping_SP1 => data_shaping_SP1,
389 data_shaping_R0 => data_shaping_R0,
366 data_shaping_R0 => data_shaping_R0,
390 data_shaping_R1 => data_shaping_R1,
367 data_shaping_R1 => data_shaping_R1,
391 data_shaping_R2 => data_shaping_R2,
368 data_shaping_R2 => data_shaping_R2,
392 delta_snapshot => delta_snapshot,
369 delta_snapshot => delta_snapshot,
393 delta_f0 => delta_f0,
370 delta_f0 => delta_f0,
394 delta_f0_2 => delta_f0_2,
371 delta_f0_2 => delta_f0_2,
395 delta_f1 => delta_f1,
372 delta_f1 => delta_f1,
396 delta_f2 => delta_f2,
373 delta_f2 => delta_f2,
397 nb_data_by_buffer => nb_data_by_buffer,
374 nb_data_by_buffer => nb_data_by_buffer,
398 nb_word_by_buffer => nb_word_by_buffer,
375 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
399 nb_snapshot_param => nb_snapshot_param,
376 nb_snapshot_param => nb_snapshot_param,
400 enable_f0 => enable_f0,
377 enable_f0 => enable_f0,
401 enable_f1 => enable_f1,
378 enable_f1 => enable_f1,
402 enable_f2 => enable_f2,
379 enable_f2 => enable_f2,
403 enable_f3 => enable_f3,
380 enable_f3 => enable_f3,
404 burst_f0 => burst_f0,
381 burst_f0 => burst_f0,
405 burst_f1 => burst_f1,
382 burst_f1 => burst_f1,
406 burst_f2 => burst_f2,
383 burst_f2 => burst_f2,
407 run => run,
384 run => run,
408 addr_data_f0 => addr_data_f0,
409 addr_data_f1 => addr_data_f1,
410 addr_data_f2 => addr_data_f2,
411 addr_data_f3 => addr_data_f3,
412 start_date => start_date,
385 start_date => start_date,
413 debug_signal => debug_signal);
386 -- debug_signal => debug_signal,
387 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
388 wfp_addr_buffer => wfp_addr_buffer,-- TODO
389 wfp_length_buffer => wfp_length_buffer,-- TODO
390
391 wfp_ready_buffer => wfp_ready_buffer,-- TODO
392 wfp_buffer_time => wfp_buffer_time,-- TODO
393 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
394 );
414
395
415 -----------------------------------------------------------------------------
396 -----------------------------------------------------------------------------
416 -----------------------------------------------------------------------------
397 -----------------------------------------------------------------------------
417 lpp_waveform_1 : lpp_waveform
398 lpp_waveform_1 : lpp_waveform
418 GENERIC MAP (
399 GENERIC MAP (
419 tech => inferred,
400 tech => inferred,
420 data_size => 6*16,
401 data_size => 6*16,
421 nb_data_by_buffer_size => nb_data_by_buffer_size,
402 nb_data_by_buffer_size => nb_data_by_buffer_size,
422 nb_word_by_buffer_size => nb_word_by_buffer_size,
423 nb_snapshot_param_size => nb_snapshot_param_size,
403 nb_snapshot_param_size => nb_snapshot_param_size,
424 delta_vector_size => delta_vector_size,
404 delta_vector_size => delta_vector_size,
425 delta_vector_size_f0_2 => delta_vector_size_f0_2
405 delta_vector_size_f0_2 => delta_vector_size_f0_2
426 )
406 )
427 PORT MAP (
407 PORT MAP (
428 clk => clk,
408 clk => clk,
429 rstn => rstn,
409 rstn => rstn,
430
410
431 reg_run => run,
411 reg_run => run,
432 reg_start_date => start_date,
412 reg_start_date => start_date,
433 reg_delta_snapshot => delta_snapshot,
413 reg_delta_snapshot => delta_snapshot,
434 reg_delta_f0 => delta_f0,
414 reg_delta_f0 => delta_f0,
435 reg_delta_f0_2 => delta_f0_2,
415 reg_delta_f0_2 => delta_f0_2,
436 reg_delta_f1 => delta_f1,
416 reg_delta_f1 => delta_f1,
437 reg_delta_f2 => delta_f2,
417 reg_delta_f2 => delta_f2,
438
418
439 enable_f0 => enable_f0,
419 enable_f0 => enable_f0,
440 enable_f1 => enable_f1,
420 enable_f1 => enable_f1,
441 enable_f2 => enable_f2,
421 enable_f2 => enable_f2,
442 enable_f3 => enable_f3,
422 enable_f3 => enable_f3,
443 burst_f0 => burst_f0,
423 burst_f0 => burst_f0,
444 burst_f1 => burst_f1,
424 burst_f1 => burst_f1,
445 burst_f2 => burst_f2,
425 burst_f2 => burst_f2,
446
426
447 nb_data_by_buffer => nb_data_by_buffer,
427 nb_data_by_buffer => nb_data_by_buffer,
448 nb_word_by_buffer => nb_word_by_buffer,
449 nb_snapshot_param => nb_snapshot_param,
428 nb_snapshot_param => nb_snapshot_param,
450 status_full => status_full,
451 status_full_ack => status_full_ack,
452 status_full_err => status_full_err,
453 status_new_err => status_new_err,
429 status_new_err => status_new_err,
430
431 status_buffer_ready => wfp_status_buffer_ready,
432 addr_buffer => wfp_addr_buffer,
433 length_buffer => wfp_length_buffer,
434 ready_buffer => wfp_ready_buffer,
435 buffer_time => wfp_buffer_time,
436 error_buffer_full => wfp_error_buffer_full,
454
437
455 coarse_time => coarse_time,
438 coarse_time => coarse_time,
456 fine_time => fine_time,
439 fine_time => fine_time,
457
440
458 --f0
441 --f0
459 addr_data_f0 => addr_data_f0,
460 data_f0_in_valid => sample_f0_val,
442 data_f0_in_valid => sample_f0_val,
461 data_f0_in => sample_f0_data,
443 data_f0_in => sample_f0_data,
462 --f1
444 --f1
463 addr_data_f1 => addr_data_f1,
464 data_f1_in_valid => sample_f1_val,
445 data_f1_in_valid => sample_f1_val,
465 data_f1_in => sample_f1_data,
446 data_f1_in => sample_f1_data,
466 --f2
447 --f2
467 addr_data_f2 => addr_data_f2,
468 data_f2_in_valid => sample_f2_val,
448 data_f2_in_valid => sample_f2_val,
469 data_f2_in => sample_f2_data,
449 data_f2_in => sample_f2_data,
470 --f3
450 --f3
471 addr_data_f3 => addr_data_f3,
472 data_f3_in_valid => sample_f3_val,
451 data_f3_in_valid => sample_f3_val,
473 data_f3_in => sample_f3_data,
452 data_f3_in => sample_f3_data,
474 -- OUTPUT -- DMA interface
453 -- OUTPUT -- DMA interface
475 --f0
454
476 data_f0_addr_out => data_f0_addr_out_s,
455 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
477 data_f0_data_out => data_f0_data_out,
456 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
478 data_f0_data_out_valid => data_f0_data_out_valid_s,
457 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
458 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
480 data_f0_data_out_ren => data_f0_data_out_ren,
459 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
481 --f1
460 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
482 data_f1_addr_out => data_f1_addr_out_s,
461 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
483 data_f1_data_out => data_f1_data_out,
462 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
484 data_f1_data_out_valid => data_f1_data_out_valid_s,
485 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
486 data_f1_data_out_ren => data_f1_data_out_ren,
487 --f2
488 data_f2_addr_out => data_f2_addr_out_s,
489 data_f2_data_out => data_f2_data_out,
490 data_f2_data_out_valid => data_f2_data_out_valid_s,
491 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
492 data_f2_data_out_ren => data_f2_data_out_ren,
493 --f3
494 data_f3_addr_out => data_f3_addr_out_s,
495 data_f3_data_out => data_f3_data_out,
496 data_f3_data_out_valid => data_f3_data_out_valid_s,
497 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
498 data_f3_data_out_ren => data_f3_data_out_ren ,
499
500 -------------------------------------------------------------------------
501 observation_reg => OPEN
502
503 );
504
505
506 -----------------------------------------------------------------------------
507 -- TEMP
508 -----------------------------------------------------------------------------
509
510 PROCESS (clk, rstn)
511 BEGIN -- PROCESS
512 IF rstn = '0' THEN -- asynchronous reset (active low)
513 data_f0_data_out_valid <= '0';
514 data_f0_data_out_valid_burst <= '0';
515 data_f1_data_out_valid <= '0';
516 data_f1_data_out_valid_burst <= '0';
517 data_f2_data_out_valid <= '0';
518 data_f2_data_out_valid_burst <= '0';
519 data_f3_data_out_valid <= '0';
520 data_f3_data_out_valid_burst <= '0';
521 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
522 data_f0_data_out_valid <= data_f0_data_out_valid_s;
523 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
524 data_f1_data_out_valid <= data_f1_data_out_valid_s;
525 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
526 data_f2_data_out_valid <= data_f2_data_out_valid_s;
527 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
528 data_f3_data_out_valid <= data_f3_data_out_valid_s;
529 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
530 END IF;
531 END PROCESS;
532
533 data_f0_addr_out <= data_f0_addr_out_s;
534 data_f1_addr_out <= data_f1_addr_out_s;
535 data_f2_addr_out <= data_f2_addr_out_s;
536 data_f3_addr_out <= data_f3_addr_out_s;
537
538 -----------------------------------------------------------------------------
539 -- RoundRobin Selection For DMA
540 -----------------------------------------------------------------------------
541
542 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
543 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
544 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
545 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
546
547 RR_Arbiter_4_1 : RR_Arbiter_4
548 PORT MAP (
549 clk => clk,
550 rstn => rstn,
551 in_valid => dma_rr_valid,
552 out_grant => dma_rr_grant_s);
553
554 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
555 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
556 dma_rr_valid_ms(2) <= '0';
557 dma_rr_valid_ms(3) <= '0';
558
559 RR_Arbiter_4_2 : RR_Arbiter_4
560 PORT MAP (
561 clk => clk,
562 rstn => rstn,
563 in_valid => dma_rr_valid_ms,
564 out_grant => dma_rr_grant_ms);
565
566 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
567
568
463
569 -----------------------------------------------------------------------------
464 );
570 -- in : dma_rr_grant
571 -- send
572 -- out : dma_sel
573 -- dma_valid_burst
574 -- dma_sel_valid
575 -----------------------------------------------------------------------------
576 PROCESS (clk, rstn)
577 BEGIN -- PROCESS
578 IF rstn = '0' THEN -- asynchronous reset (active low)
579 dma_sel <= (OTHERS => '0');
580 dma_send <= '0';
581 dma_valid_burst <= '0';
582 data_ms_done <= '0';
583 dma_ms_ongoing <= '0';
584 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
585 IF run = '1' THEN
586 data_ms_done <= '0';
587 IF dma_sel = "00000" OR dma_done = '1' THEN
588 dma_sel <= dma_rr_grant;
589 IF dma_rr_grant(0) = '1' THEN
590 dma_ms_ongoing <= '0';
591 dma_send <= '1';
592 dma_valid_burst <= data_f0_data_out_valid_burst;
593 dma_sel_valid <= data_f0_data_out_valid;
594 ELSIF dma_rr_grant(1) = '1' THEN
595 dma_ms_ongoing <= '0';
596 dma_send <= '1';
597 dma_valid_burst <= data_f1_data_out_valid_burst;
598 dma_sel_valid <= data_f1_data_out_valid;
599 ELSIF dma_rr_grant(2) = '1' THEN
600 dma_ms_ongoing <= '0';
601 dma_send <= '1';
602 dma_valid_burst <= data_f2_data_out_valid_burst;
603 dma_sel_valid <= data_f2_data_out_valid;
604 ELSIF dma_rr_grant(3) = '1' THEN
605 dma_ms_ongoing <= '0';
606 dma_send <= '1';
607 dma_valid_burst <= data_f3_data_out_valid_burst;
608 dma_sel_valid <= data_f3_data_out_valid;
609 ELSIF dma_rr_grant(4) = '1' THEN
610 dma_ms_ongoing <= '1';
611 dma_send <= '1';
612 dma_valid_burst <= data_ms_valid_burst;
613 dma_sel_valid <= data_ms_valid;
614 --ELSE
615 --dma_ms_ongoing <= '0';
616 END IF;
617
618 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
619 data_ms_done <= '1';
620 END IF;
621 ELSE
622 dma_sel <= dma_sel;
623 dma_send <= '0';
624 END IF;
625 ELSE
626 data_ms_done <= '0';
627 dma_sel <= (OTHERS => '0');
628 dma_send <= '0';
629 dma_valid_burst <= '0';
630 END IF;
631 END IF;
632 END PROCESS;
633
634
635 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
636 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
637 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
638 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
639 data_ms_addr;
640
641 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
642 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
643 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
644 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
645 data_ms_data;
646
647 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
648 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
649 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
650 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
651 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
652
653 dma_data_2 <= dma_data;
654
655
656 -----------------------------------------------------------------------------
657 -- DMA
658 -----------------------------------------------------------------------------
659 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
660 GENERIC MAP (
661 tech => inferred,
662 hindex => hindex)
663 PORT MAP (
664 HCLK => clk,
665 HRESETn => rstn,
666 run => run,
667 AHB_Master_In => OPEN,
668 AHB_Master_Out => OPEN,
669
670 send => dma_send,
671 valid_burst => dma_valid_burst,
672 done => dma_done,
673 ren => dma_ren,
674 address => dma_address,
675 data => dma_data_2);
676
465
677 -----------------------------------------------------------------------------
466 -----------------------------------------------------------------------------
678 -- Matrix Spectral
467 -- Matrix Spectral
679 -----------------------------------------------------------------------------
468 -----------------------------------------------------------------------------
680 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
469 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
681 NOT(sample_f0_val) & NOT(sample_f0_val);
470 NOT(sample_f0_val) & NOT(sample_f0_val);
682 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
471 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
683 NOT(sample_f1_val) & NOT(sample_f1_val);
472 NOT(sample_f1_val) & NOT(sample_f1_val);
684 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
473 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
685 NOT(sample_f2_val) & NOT(sample_f2_val);
474 NOT(sample_f2_val) & NOT(sample_f2_val);
686
475
687 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
476 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
688 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
477 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
689 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
478 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
690
479
691 -------------------------------------------------------------------------------
480 -------------------------------------------------------------------------------
692
481
693 ms_softandhard_rstn <= rstn AND run_ms AND run;
482 ms_softandhard_rstn <= rstn AND run_ms AND run;
694
483
695 -----------------------------------------------------------------------------
484 -----------------------------------------------------------------------------
696 lpp_lfr_ms_1 : lpp_lfr_ms
485 lpp_lfr_ms_1 : lpp_lfr_ms
697 GENERIC MAP (
486 GENERIC MAP (
698 Mem_use => Mem_use)
487 Mem_use => Mem_use)
699 PORT MAP (
488 PORT MAP (
700 clk => clk,
489 clk => clk,
701 rstn => ms_softandhard_rstn, --rstn,
490 rstn => ms_softandhard_rstn, --rstn,
702 run => run_ms,
491 run => run_ms,
703
492
704 coarse_time => coarse_time,
493 coarse_time => coarse_time,
705 fine_time => fine_time,
494 fine_time => fine_time,
706
495
707 sample_f0_wen => sample_f0_wen,
496 sample_f0_wen => sample_f0_wen,
708 sample_f0_wdata => sample_f0_wdata,
497 sample_f0_wdata => sample_f0_wdata,
709 sample_f1_wen => sample_f1_wen,
498 sample_f1_wen => sample_f1_wen,
710 sample_f1_wdata => sample_f1_wdata,
499 sample_f1_wdata => sample_f1_wdata,
711 sample_f2_wen => sample_f2_wen,
500 sample_f2_wen => sample_f2_wen,
712 sample_f2_wdata => sample_f2_wdata,
501 sample_f2_wdata => sample_f2_wdata,
713
502
714 --DMA
503 --DMA
715 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
504 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
716 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
505 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
717 dma_fifo_ren => dma_fifo_ren(4), -- IN
506 dma_fifo_ren => dma_fifo_ren(4), -- IN
718 dma_buffer_new => dma_buffer_new(4), -- OUT
507 dma_buffer_new => dma_buffer_new(4), -- OUT
719 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
508 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
720 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
509 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
721 dma_buffer_full => dma_buffer_full(4), -- IN
510 dma_buffer_full => dma_buffer_full(4), -- IN
722 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
511 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
723
512
724
513
725
514
726 --REG
515 --REG
727 ready_matrix_f0 => ready_matrix_f0,
516 ready_matrix_f0 => ready_matrix_f0,
728 ready_matrix_f1 => ready_matrix_f1,
517 ready_matrix_f1 => ready_matrix_f1,
729 ready_matrix_f2 => ready_matrix_f2,
518 ready_matrix_f2 => ready_matrix_f2,
730 error_buffer_full => error_buffer_full,
519 error_buffer_full => error_buffer_full,
731 error_input_fifo_write => error_input_fifo_write,
520 error_input_fifo_write => error_input_fifo_write,
732
521
733 status_ready_matrix_f0 => status_ready_matrix_f0,
522 status_ready_matrix_f0 => status_ready_matrix_f0,
734 status_ready_matrix_f1 => status_ready_matrix_f1,
523 status_ready_matrix_f1 => status_ready_matrix_f1,
735 status_ready_matrix_f2 => status_ready_matrix_f2,
524 status_ready_matrix_f2 => status_ready_matrix_f2,
736 addr_matrix_f0 => addr_matrix_f0,
525 addr_matrix_f0 => addr_matrix_f0,
737 addr_matrix_f1 => addr_matrix_f1,
526 addr_matrix_f1 => addr_matrix_f1,
738 addr_matrix_f2 => addr_matrix_f2,
527 addr_matrix_f2 => addr_matrix_f2,
739
528
740 length_matrix_f0 => length_matrix_f0,
529 length_matrix_f0 => length_matrix_f0,
741 length_matrix_f1 => length_matrix_f1,
530 length_matrix_f1 => length_matrix_f1,
742 length_matrix_f2 => length_matrix_f2,
531 length_matrix_f2 => length_matrix_f2,
743
532
744 matrix_time_f0 => matrix_time_f0,
533 matrix_time_f0 => matrix_time_f0,
745 matrix_time_f1 => matrix_time_f1,
534 matrix_time_f1 => matrix_time_f1,
746 matrix_time_f2 => matrix_time_f2);
535 matrix_time_f2 => matrix_time_f2);
747
536
748 -----------------------------------------------------------------------------
537 -----------------------------------------------------------------------------
749
538
750 DMA_SubSystem_1 : DMA_SubSystem
539 DMA_SubSystem_1 : DMA_SubSystem
751 GENERIC MAP (
540 GENERIC MAP (
752 hindex => hindex)
541 hindex => hindex)
753 PORT MAP (
542 PORT MAP (
754 clk => clk,
543 clk => clk,
755 rstn => rstn,
544 rstn => rstn,
756 run => run_ms,
545 run => run_ms,
757 ahbi => ahbi,
546 ahbi => ahbi,
758 ahbo => ahbo,
547 ahbo => ahbo,
759
548
760 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
549 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
761 fifo_data => dma_fifo_data, --fifo_data,
550 fifo_data => dma_fifo_data, --fifo_data,
762 fifo_ren => dma_fifo_ren, --fifo_ren,
551 fifo_ren => dma_fifo_ren, --fifo_ren,
763
552
764 buffer_new => dma_buffer_new, --buffer_new,
553 buffer_new => dma_buffer_new, --buffer_new,
765 buffer_addr => dma_buffer_addr, --buffer_addr,
554 buffer_addr => dma_buffer_addr, --buffer_addr,
766 buffer_length => dma_buffer_length, --buffer_length,
555 buffer_length => dma_buffer_length, --buffer_length,
767 buffer_full => dma_buffer_full, --buffer_full,
556 buffer_full => dma_buffer_full, --buffer_full,
768 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
557 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
769 grant_error => dma_grant_error); --grant_error);
558 grant_error => dma_grant_error); --grant_error);
770
559
771 END beh;
560 END beh;
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@@ -1,721 +1,770
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 -- error_bad_component_error : IN STD_LOGIC;
69 -- error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90
90
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94
94
95 ---------------------------------------------------------------------------
95 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
97 -- WaveForm picker Reg
97 -- WaveForm picker Reg
98 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102
102
103 -- OUT
103 -- OUT
104 data_shaping_BW : OUT STD_LOGIC;
104 data_shaping_BW : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
110
110
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119
119
120 enable_f0 : OUT STD_LOGIC;
120 enable_f0 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
124
124
125 burst_f0 : OUT STD_LOGIC;
125 burst_f0 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
128
128
129 run : OUT STD_LOGIC;
129 run : OUT STD_LOGIC;
130
130
131 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
133 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
136 ---------------------------------------------------------------------------
132
137 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
138 ---------------------------------------------------------------------------
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139
139 );
140 );
140
141
141 END lpp_lfr_apbreg;
142 END lpp_lfr_apbreg;
142
143
143 ARCHITECTURE beh OF lpp_lfr_apbreg IS
144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
144
145
145 CONSTANT REVISION : INTEGER := 1;
146 CONSTANT REVISION : INTEGER := 1;
146
147
147 CONSTANT pconfig : apb_config_type := (
148 CONSTANT pconfig : apb_config_type := (
148 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
149 1 => apb_iobar(paddr, pmask));
150 1 => apb_iobar(paddr, pmask));
150
151
151 TYPE lpp_SpectralMatrix_regs IS RECORD
152 TYPE lpp_SpectralMatrix_regs IS RECORD
152 config_active_interruption_onNewMatrix : STD_LOGIC;
153 config_active_interruption_onNewMatrix : STD_LOGIC;
153 config_active_interruption_onError : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
154 config_ms_run : STD_LOGIC;
155 config_ms_run : STD_LOGIC;
155 status_ready_matrix_f0_0 : STD_LOGIC;
156 status_ready_matrix_f0_0 : STD_LOGIC;
156 status_ready_matrix_f1_0 : STD_LOGIC;
157 status_ready_matrix_f1_0 : STD_LOGIC;
157 status_ready_matrix_f2_0 : STD_LOGIC;
158 status_ready_matrix_f2_0 : STD_LOGIC;
158 status_ready_matrix_f0_1 : STD_LOGIC;
159 status_ready_matrix_f0_1 : STD_LOGIC;
159 status_ready_matrix_f1_1 : STD_LOGIC;
160 status_ready_matrix_f1_1 : STD_LOGIC;
160 status_ready_matrix_f2_1 : STD_LOGIC;
161 status_ready_matrix_f2_1 : STD_LOGIC;
161 -- status_error_bad_component_error : STD_LOGIC;
162 -- status_error_bad_component_error : STD_LOGIC;
162 status_error_buffer_full : STD_LOGIC;
163 status_error_buffer_full : STD_LOGIC;
163 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
164
165
165 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171
172
172 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173
174
174 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 END RECORD;
181 END RECORD;
181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182
183
183 TYPE lpp_WaveformPicker_regs IS RECORD
184 TYPE lpp_WaveformPicker_regs IS RECORD
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 data_shaping_BW : STD_LOGIC;
188 data_shaping_BW : STD_LOGIC;
188 data_shaping_SP0 : STD_LOGIC;
189 data_shaping_SP0 : STD_LOGIC;
189 data_shaping_SP1 : STD_LOGIC;
190 data_shaping_SP1 : STD_LOGIC;
190 data_shaping_R0 : STD_LOGIC;
191 data_shaping_R0 : STD_LOGIC;
191 data_shaping_R1 : STD_LOGIC;
192 data_shaping_R1 : STD_LOGIC;
192 data_shaping_R2 : STD_LOGIC;
193 data_shaping_R2 : STD_LOGIC;
193 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
196 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
199 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
201 enable_f0 : STD_LOGIC;
202 enable_f0 : STD_LOGIC;
202 enable_f1 : STD_LOGIC;
203 enable_f1 : STD_LOGIC;
203 enable_f2 : STD_LOGIC;
204 enable_f2 : STD_LOGIC;
204 enable_f3 : STD_LOGIC;
205 enable_f3 : STD_LOGIC;
205 burst_f0 : STD_LOGIC;
206 burst_f0 : STD_LOGIC;
206 burst_f1 : STD_LOGIC;
207 burst_f1 : STD_LOGIC;
207 burst_f2 : STD_LOGIC;
208 burst_f2 : STD_LOGIC;
208 run : STD_LOGIC;
209 run : STD_LOGIC;
209 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
210 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
211 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
212 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
214 END RECORD;
216 END RECORD;
215 SIGNAL reg_wp : lpp_WaveformPicker_regs;
217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
216
218
217 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
218
220
219 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
220 -- IRQ
222 -- IRQ
221 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
222 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
223 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL ored_irq_wfp : STD_LOGIC;
229 SIGNAL ored_irq_wfp : STD_LOGIC;
228
230
229 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
230 --
232 --
231 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
232 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
233 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
234 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
235
237
236 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
237 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
239
241
240 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
241 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243
245
244 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
245 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247
249
248 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
249 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251
253
252 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
253 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255 SIGNAL apbo_irq_ms : STD_LOGIC;
257 SIGNAL apbo_irq_ms : STD_LOGIC;
256 SIGNAL apbo_irq_wfp : STD_LOGIC;
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 -----------------------------------------------------------------------------
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
257
261
258 BEGIN -- beh
262 BEGIN -- beh
259
263
260 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
261 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
262 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
263
267
264 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
265 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
266
270
267
271
268 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
269 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
270 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
271
275
272
276
273 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
274 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
275 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
276 data_shaping_R0 <= reg_wp.data_shaping_R0;
280 data_shaping_R0 <= reg_wp.data_shaping_R0;
277 data_shaping_R1 <= reg_wp.data_shaping_R1;
281 data_shaping_R1 <= reg_wp.data_shaping_R1;
278 data_shaping_R2 <= reg_wp.data_shaping_R2;
282 data_shaping_R2 <= reg_wp.data_shaping_R2;
279
283
280 delta_snapshot <= reg_wp.delta_snapshot;
284 delta_snapshot <= reg_wp.delta_snapshot;
281 delta_f0 <= reg_wp.delta_f0;
285 delta_f0 <= reg_wp.delta_f0;
282 delta_f0_2 <= reg_wp.delta_f0_2;
286 delta_f0_2 <= reg_wp.delta_f0_2;
283 delta_f1 <= reg_wp.delta_f1;
287 delta_f1 <= reg_wp.delta_f1;
284 delta_f2 <= reg_wp.delta_f2;
288 delta_f2 <= reg_wp.delta_f2;
285 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
286 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
287 nb_snapshot_param <= reg_wp.nb_snapshot_param;
290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
288
291
289 enable_f0 <= reg_wp.enable_f0;
292 enable_f0 <= reg_wp.enable_f0;
290 enable_f1 <= reg_wp.enable_f1;
293 enable_f1 <= reg_wp.enable_f1;
291 enable_f2 <= reg_wp.enable_f2;
294 enable_f2 <= reg_wp.enable_f2;
292 enable_f3 <= reg_wp.enable_f3;
295 enable_f3 <= reg_wp.enable_f3;
293
296
294 burst_f0 <= reg_wp.burst_f0;
297 burst_f0 <= reg_wp.burst_f0;
295 burst_f1 <= reg_wp.burst_f1;
298 burst_f1 <= reg_wp.burst_f1;
296 burst_f2 <= reg_wp.burst_f2;
299 burst_f2 <= reg_wp.burst_f2;
297
300
298 run <= reg_wp.run;
301 run <= reg_wp.run;
299
302
300 addr_data_f0 <= reg_wp.addr_data_f0;
303 --addr_data_f0 <= reg_wp.addr_data_f0;
301 addr_data_f1 <= reg_wp.addr_data_f1;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
302 addr_data_f2 <= reg_wp.addr_data_f2;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
303 addr_data_f3 <= reg_wp.addr_data_f3;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
304
307
305 start_date <= reg_wp.start_date;
308 start_date <= reg_wp.start_date;
306
309
307 length_matrix_f0 <= reg_sp.length_matrix;
310 --length_matrix_f0 <= reg_sp.length_matrix;
308 length_matrix_f1 <= reg_sp.length_matrix;
311 --length_matrix_f1 <= reg_sp.length_matrix;
309 length_matrix_f2 <= reg_sp.length_matrix;
312 --length_matrix_f2 <= reg_sp.length_matrix;
310
313
311
314
312 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
315 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
313 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
316 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
314 BEGIN -- PROCESS lpp_dma_top
317 BEGIN -- PROCESS lpp_dma_top
315 IF HRESETn = '0' THEN -- asynchronous reset (active low)
318 IF HRESETn = '0' THEN -- asynchronous reset (active low)
316 reg_sp.config_active_interruption_onNewMatrix <= '0';
319 reg_sp.config_active_interruption_onNewMatrix <= '0';
317 reg_sp.config_active_interruption_onError <= '0';
320 reg_sp.config_active_interruption_onError <= '0';
318 reg_sp.config_ms_run <= '1';
321 reg_sp.config_ms_run <= '1';
319 reg_sp.status_ready_matrix_f0_0 <= '0';
322 reg_sp.status_ready_matrix_f0_0 <= '0';
320 reg_sp.status_ready_matrix_f1_0 <= '0';
323 reg_sp.status_ready_matrix_f1_0 <= '0';
321 reg_sp.status_ready_matrix_f2_0 <= '0';
324 reg_sp.status_ready_matrix_f2_0 <= '0';
322 reg_sp.status_ready_matrix_f0_1 <= '0';
325 reg_sp.status_ready_matrix_f0_1 <= '0';
323 reg_sp.status_ready_matrix_f1_1 <= '0';
326 reg_sp.status_ready_matrix_f1_1 <= '0';
324 reg_sp.status_ready_matrix_f2_1 <= '0';
327 reg_sp.status_ready_matrix_f2_1 <= '0';
325 -- reg_sp.status_error_bad_component_error <= '0';
326 reg_sp.status_error_buffer_full <= '0';
328 reg_sp.status_error_buffer_full <= '0';
327 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
329 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
328
330
329 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
331 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
330 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
332 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
331 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
332
334
333 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
335 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
336 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
335 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
337 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
336
338
337 reg_sp.length_matrix <= (OTHERS => '0');
339 reg_sp.length_matrix <= (OTHERS => '0');
338
340
339 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
341 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
340 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
342 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
341 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
342
344
343 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
345 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
344 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
346 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
345 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
347 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
346
348
347 prdata <= (OTHERS => '0');
349 prdata <= (OTHERS => '0');
348
350
349
351
350 apbo_irq_ms <= '0';
352 apbo_irq_ms <= '0';
351 apbo_irq_wfp <= '0';
353 apbo_irq_wfp <= '0';
352
354
353
355
354 status_full_ack <= (OTHERS => '0');
356 -- status_full_ack <= (OTHERS => '0');
355
357
356 reg_wp.data_shaping_BW <= '0';
358 reg_wp.data_shaping_BW <= '0';
357 reg_wp.data_shaping_SP0 <= '0';
359 reg_wp.data_shaping_SP0 <= '0';
358 reg_wp.data_shaping_SP1 <= '0';
360 reg_wp.data_shaping_SP1 <= '0';
359 reg_wp.data_shaping_R0 <= '0';
361 reg_wp.data_shaping_R0 <= '0';
360 reg_wp.data_shaping_R1 <= '0';
362 reg_wp.data_shaping_R1 <= '0';
361 reg_wp.data_shaping_R2 <= '0';
363 reg_wp.data_shaping_R2 <= '0';
362 reg_wp.enable_f0 <= '0';
364 reg_wp.enable_f0 <= '0';
363 reg_wp.enable_f1 <= '0';
365 reg_wp.enable_f1 <= '0';
364 reg_wp.enable_f2 <= '0';
366 reg_wp.enable_f2 <= '0';
365 reg_wp.enable_f3 <= '0';
367 reg_wp.enable_f3 <= '0';
366 reg_wp.burst_f0 <= '0';
368 reg_wp.burst_f0 <= '0';
367 reg_wp.burst_f1 <= '0';
369 reg_wp.burst_f1 <= '0';
368 reg_wp.burst_f2 <= '0';
370 reg_wp.burst_f2 <= '0';
369 reg_wp.run <= '0';
371 reg_wp.run <= '0';
370 reg_wp.addr_data_f0 <= (OTHERS => '0');
372 -- reg_wp.status_full <= (OTHERS => '0');
371 reg_wp.addr_data_f1 <= (OTHERS => '0');
373 -- reg_wp.status_full_err <= (OTHERS => '0');
372 reg_wp.addr_data_f2 <= (OTHERS => '0');
373 reg_wp.addr_data_f3 <= (OTHERS => '0');
374 reg_wp.status_full <= (OTHERS => '0');
375 reg_wp.status_full_err <= (OTHERS => '0');
376 reg_wp.status_new_err <= (OTHERS => '0');
374 reg_wp.status_new_err <= (OTHERS => '0');
375 reg_wp.error_buffer_full <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
376 reg_wp.delta_snapshot <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
377 reg_wp.delta_f0 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
378 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
379 reg_wp.delta_f1 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
380 reg_wp.delta_f2 <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
381 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
382 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '0');
383 reg_wp.start_date <= (OTHERS => '0');
385
384
386 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
385 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
387
386
388 status_full_ack <= (OTHERS => '0');
387 -- status_full_ack <= (OTHERS => '0');
389
388
390 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
389 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
391 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
390 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
392 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
391 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
393
392
394 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
393 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
395 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
394 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
396 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
395 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
397
396
398 -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
397 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
398 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
399 END LOOP all_status_ready_buffer_bit;
400
399
401
400 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
402 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
401 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
403 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
402 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
404 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
403 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
405 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
404
406
405
407
406
408
407 all_status : FOR I IN 3 DOWNTO 0 LOOP
409 all_status : FOR I IN 3 DOWNTO 0 LOOP
408 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
410 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
409 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
411 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
410 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
411 END LOOP all_status;
412 END LOOP all_status;
412
413
413 paddr := "000000";
414 paddr := "000000";
414 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
415 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
415 prdata <= (OTHERS => '0');
416 prdata <= (OTHERS => '0');
416 IF apbi.psel(pindex) = '1' THEN
417 IF apbi.psel(pindex) = '1' THEN
417 -- APB DMA READ --
418 -- APB DMA READ --
418 CASE paddr(7 DOWNTO 2) IS
419 CASE paddr(7 DOWNTO 2) IS
419 --0
420 --0
420 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
421 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
421 prdata(1) <= reg_sp.config_active_interruption_onError;
422 prdata(1) <= reg_sp.config_active_interruption_onError;
422 prdata(2) <= reg_sp.config_ms_run;
423 prdata(2) <= reg_sp.config_ms_run;
423 --1
424 --1
424 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
425 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
425 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
426 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
426 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
427 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
427 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
428 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
428 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
429 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
429 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
430 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
430 -- prdata(6) <= reg_sp.status_error_bad_component_error;
431 -- prdata(6) <= reg_sp.status_error_bad_component_error;
431 prdata(7) <= reg_sp.status_error_buffer_full;
432 prdata(7) <= reg_sp.status_error_buffer_full;
432 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
433 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
433 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
434 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
434 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
435 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
435 --2
436 --2
436 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
437 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
437 --3
438 --3
438 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
439 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
439 --4
440 --4
440 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
441 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
441 --5
442 --5
442 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
443 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
443 --6
444 --6
444 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
445 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
445 --7
446 --7
446 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
447 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
447 --8
448 --8
448 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
449 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
449 --9
450 --9
450 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
451 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
451 --10
452 --10
452 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
453 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
453 --11
454 --11
454 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
455 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
455 --12
456 --12
456 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
457 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
457 --13
458 --13
458 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
459 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
459 --14
460 --14
460 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
461 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
461 --15
462 --15
462 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
463 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
463 --16
464 --16
464 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
465 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
465 --17
466 --17
466 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
467 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
467 --18
468 --18
468 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
469 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
469 --19
470 --19
470 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
471 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
471 --20
472 --20
472 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
473 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
473 ---------------------------------------------------------------------
474 ---------------------------------------------------------------------
474 --20
475 --20
475 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
476 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
476 prdata(1) <= reg_wp.data_shaping_SP0;
477 prdata(1) <= reg_wp.data_shaping_SP0;
477 prdata(2) <= reg_wp.data_shaping_SP1;
478 prdata(2) <= reg_wp.data_shaping_SP1;
478 prdata(3) <= reg_wp.data_shaping_R0;
479 prdata(3) <= reg_wp.data_shaping_R0;
479 prdata(4) <= reg_wp.data_shaping_R1;
480 prdata(4) <= reg_wp.data_shaping_R1;
480 prdata(5) <= reg_wp.data_shaping_R2;
481 prdata(5) <= reg_wp.data_shaping_R2;
481 --21
482 --21
482 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
483 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
483 prdata(1) <= reg_wp.enable_f1;
484 prdata(1) <= reg_wp.enable_f1;
484 prdata(2) <= reg_wp.enable_f2;
485 prdata(2) <= reg_wp.enable_f2;
485 prdata(3) <= reg_wp.enable_f3;
486 prdata(3) <= reg_wp.enable_f3;
486 prdata(4) <= reg_wp.burst_f0;
487 prdata(4) <= reg_wp.burst_f0;
487 prdata(5) <= reg_wp.burst_f1;
488 prdata(5) <= reg_wp.burst_f1;
488 prdata(6) <= reg_wp.burst_f2;
489 prdata(6) <= reg_wp.burst_f2;
489 prdata(7) <= reg_wp.run;
490 prdata(7) <= reg_wp.run;
490 --22
491 --22
491 WHEN "010111" => prdata <= reg_wp.addr_data_f0;
492 --ON GOING \/
492 --23
493 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);
493 WHEN "011000" => prdata <= reg_wp.addr_data_f1;
494 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
494 --24
495 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);
495 WHEN "011001" => prdata <= reg_wp.addr_data_f2;
496 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
496 --25
497 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);
497 WHEN "011010" => prdata <= reg_wp.addr_data_f3;
498 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
498 --26
499 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);
499 WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
500 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
500 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
501 --ON GOING /\
501 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
502 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
503 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
504 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
505 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
506 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
502 --27
507 --27
503 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
508 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
504 --28
509 --28
505 WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
510 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
506 --29
511 --29
507 WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
512 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 --30
513 --30
509 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
514 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
510 --31
515 --31
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
516 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
512 --32
517 --32
513 WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
518 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
514 --33
519 --33
515 WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
520 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
516 --34
521 --34
517 WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
522 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
518 --35
523 --35
519 WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
524 WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
525 WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
526 WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1);
527 WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16);
528 WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2);
529 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16);
530 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3);
531 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16);
532
533 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4);
534 WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16);
535 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5);
536 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16);
537 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6);
538 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16);
539 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7);
540 WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16);
541 WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
542
543 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
520 ----------------------------------------------------
544 ----------------------------------------------------
521 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
545 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
522 WHEN OTHERS => NULL;
546 WHEN OTHERS => NULL;
523
547
524 END CASE;
548 END CASE;
525 IF (apbi.pwrite AND apbi.penable) = '1' THEN
549 IF (apbi.pwrite AND apbi.penable) = '1' THEN
526 -- APB DMA WRITE --
550 -- APB DMA WRITE --
527 CASE paddr(7 DOWNTO 2) IS
551 CASE paddr(7 DOWNTO 2) IS
528 --
552 --
529 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
553 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
530 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
554 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
531 reg_sp.config_ms_run <= apbi.pwdata(2);
555 reg_sp.config_ms_run <= apbi.pwdata(2);
532
556
533 WHEN "000001" =>
557 WHEN "000001" =>
534 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
558 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
535 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
559 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
536 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
560 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
537 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
561 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
538 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
562 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
539 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
563 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
540 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
564 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
541 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
565 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
542 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
566 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
543 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
567 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
544 --2
568 --2
545 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
569 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
546 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
570 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
547 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
571 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
548 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
572 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
549 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
573 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
550 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
574 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
551 --8 to 19
575 --8 to 19
552 --20
576 --20
553 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
577 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
554 --20
578 --20
555 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
579 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
556 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
580 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
557 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
581 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
558 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
582 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
559 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
583 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
560 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
584 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
561 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
585 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
562 reg_wp.enable_f1 <= apbi.pwdata(1);
586 reg_wp.enable_f1 <= apbi.pwdata(1);
563 reg_wp.enable_f2 <= apbi.pwdata(2);
587 reg_wp.enable_f2 <= apbi.pwdata(2);
564 reg_wp.enable_f3 <= apbi.pwdata(3);
588 reg_wp.enable_f3 <= apbi.pwdata(3);
565 reg_wp.burst_f0 <= apbi.pwdata(4);
589 reg_wp.burst_f0 <= apbi.pwdata(4);
566 reg_wp.burst_f1 <= apbi.pwdata(5);
590 reg_wp.burst_f1 <= apbi.pwdata(5);
567 reg_wp.burst_f2 <= apbi.pwdata(6);
591 reg_wp.burst_f2 <= apbi.pwdata(6);
568 reg_wp.run <= apbi.pwdata(7);
592 reg_wp.run <= apbi.pwdata(7);
569 --22
593 --22
570 WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata;
594 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
571 WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata;
595 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
572 WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata;
596 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
573 WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata;
597 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
598 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
599 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
600 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
601 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
574 --26
602 --26
575 WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
603 WHEN "011111" =>
576 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
604 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
577 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
605 reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I);
578 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
606 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
579 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
607 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
580 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
608 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
581 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
609 END LOOP all_reg_wp_status_bit;
582 WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
610
583 WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
611 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
584 WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
612 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
585 WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
613 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
586 WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
614 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
587 WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
615 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
588 WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
616 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
589 WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
617 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
590 WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
618 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
619
620 WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
621
622
623
624
625
626 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
591 --
627 --
592 WHEN OTHERS => NULL;
628 WHEN OTHERS => NULL;
593 END CASE;
629 END CASE;
594 END IF;
630 END IF;
595 END IF;
631 END IF;
596 --apbo.pirq(pirq_ms) <=
632 --apbo.pirq(pirq_ms) <=
597 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
633 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
598 ready_matrix_f1 OR
634 ready_matrix_f1 OR
599 ready_matrix_f2)
635 ready_matrix_f2)
600 )
636 )
601 OR
637 OR
602 (reg_sp.config_active_interruption_onError AND (
638 (reg_sp.config_active_interruption_onError AND (
603 -- error_bad_component_error OR
639 -- error_bad_component_error OR
604 error_buffer_full
640 error_buffer_full
605 OR error_input_fifo_write(0)
641 OR error_input_fifo_write(0)
606 OR error_input_fifo_write(1)
642 OR error_input_fifo_write(1)
607 OR error_input_fifo_write(2))
643 OR error_input_fifo_write(2))
608 ));
644 ));
609 -- apbo.pirq(pirq_wfp)
645 -- apbo.pirq(pirq_wfp)
610 apbo_irq_wfp<= ored_irq_wfp;
646 apbo_irq_wfp<= ored_irq_wfp;
611
647
612 END IF;
648 END IF;
613 END PROCESS lpp_lfr_apbreg;
649 END PROCESS lpp_lfr_apbreg;
614
650
615 apbo.pirq(pirq_ms) <= apbo_irq_ms;
651 apbo.pirq(pirq_ms) <= apbo_irq_ms;
616 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
652 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
617
653
618 apbo.pindex <= pindex;
654 apbo.pindex <= pindex;
619 apbo.pconfig <= pconfig;
655 apbo.pconfig <= pconfig;
620 apbo.prdata <= prdata;
656 apbo.prdata <= prdata;
621
657
622 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
623 -- IRQ
659 -- IRQ
624 -----------------------------------------------------------------------------
660 -----------------------------------------------------------------------------
625 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
661 irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err;
626
662
627 PROCESS (HCLK, HRESETn)
663 PROCESS (HCLK, HRESETn)
628 BEGIN -- PROCESS
664 BEGIN -- PROCESS
629 IF HRESETn = '0' THEN -- asynchronous reset (active low)
665 IF HRESETn = '0' THEN -- asynchronous reset (active low)
630 irq_wfp_reg <= (OTHERS => '0');
666 irq_wfp_reg <= (OTHERS => '0');
631 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
667 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
632 irq_wfp_reg <= irq_wfp_reg_s;
668 irq_wfp_reg <= irq_wfp_reg_s;
633 END IF;
669 END IF;
634 END PROCESS;
670 END PROCESS;
635
671
636 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
672 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
637 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
673 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
638 END GENERATE all_irq_wfp;
674 END GENERATE all_irq_wfp;
639
675
640 irq_wfp_ZERO <= (OTHERS => '0');
676 irq_wfp_ZERO <= (OTHERS => '0');
641 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
677 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
642
678
643 run_ms <= reg_sp.config_ms_run;
679 run_ms <= reg_sp.config_ms_run;
644
680
645 -----------------------------------------------------------------------------
681 -----------------------------------------------------------------------------
646 --
682 --
647 -----------------------------------------------------------------------------
683 -----------------------------------------------------------------------------
648 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
684 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
649 PORT MAP (
685 PORT MAP (
650 clk => HCLK,
686 clk => HCLK,
651 rstn => HRESETn,
687 rstn => HRESETn,
652
688
653 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
689 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
654 reg0_ready_matrix => reg0_ready_matrix_f0,
690 reg0_ready_matrix => reg0_ready_matrix_f0,
655 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
691 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
656 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
692 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
657
693
658 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
694 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
659 reg1_ready_matrix => reg1_ready_matrix_f0,
695 reg1_ready_matrix => reg1_ready_matrix_f0,
660 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
696 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
661 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
697 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
662
698
663 ready_matrix => ready_matrix_f0,
699 ready_matrix => ready_matrix_f0,
664 status_ready_matrix => status_ready_matrix_f0,
700 status_ready_matrix => status_ready_matrix_f0,
665 addr_matrix => addr_matrix_f0,
701 addr_matrix => addr_matrix_f0,
666 matrix_time => matrix_time_f0);
702 matrix_time => matrix_time_f0);
667
703
668 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
704 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
669 PORT MAP (
705 PORT MAP (
670 clk => HCLK,
706 clk => HCLK,
671 rstn => HRESETn,
707 rstn => HRESETn,
672
708
673 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
709 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
674 reg0_ready_matrix => reg0_ready_matrix_f1,
710 reg0_ready_matrix => reg0_ready_matrix_f1,
675 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
711 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
676 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
712 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
677
713
678 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
714 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
679 reg1_ready_matrix => reg1_ready_matrix_f1,
715 reg1_ready_matrix => reg1_ready_matrix_f1,
680 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
716 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
681 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
717 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
682
718
683 ready_matrix => ready_matrix_f1,
719 ready_matrix => ready_matrix_f1,
684 status_ready_matrix => status_ready_matrix_f1,
720 status_ready_matrix => status_ready_matrix_f1,
685 addr_matrix => addr_matrix_f1,
721 addr_matrix => addr_matrix_f1,
686 matrix_time => matrix_time_f1);
722 matrix_time => matrix_time_f1);
687
723
688 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
724 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
689 PORT MAP (
725 PORT MAP (
690 clk => HCLK,
726 clk => HCLK,
691 rstn => HRESETn,
727 rstn => HRESETn,
692
728
693 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
729 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
694 reg0_ready_matrix => reg0_ready_matrix_f2,
730 reg0_ready_matrix => reg0_ready_matrix_f2,
695 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
731 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
696 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
732 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
697
733
698 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
734 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
699 reg1_ready_matrix => reg1_ready_matrix_f2,
735 reg1_ready_matrix => reg1_ready_matrix_f2,
700 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
736 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
701 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
737 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
702
738
703 ready_matrix => ready_matrix_f2,
739 ready_matrix => ready_matrix_f2,
704 status_ready_matrix => status_ready_matrix_f2,
740 status_ready_matrix => status_ready_matrix_f2,
705 addr_matrix => addr_matrix_f2,
741 addr_matrix => addr_matrix_f2,
706 matrix_time => matrix_time_f2);
742 matrix_time => matrix_time_f2);
707
743
708 -----------------------------------------------------------------------------
744 -----------------------------------------------------------------------------
709 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
745 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
710 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
746 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
711 reg_sp.status_error_input_fifo_write(2) &--10
747 PORT MAP (
712 reg_sp.status_error_input_fifo_write(1) &--9
748 clk => HCLK,
713 reg_sp.status_error_input_fifo_write(0) &--8
749 rstn => HRESETn,
714 reg_sp.status_error_buffer_full &
750
715 '0' &
751 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
716 -- reg_sp.status_error_bad_component_error & --7 6
752 reg0_ready_matrix => reg_ready_buffer_f(2*I),
717 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
753 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
718 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
754 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
719 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
755
756 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
757 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
758 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
759 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
760
761 ready_matrix => wfp_ready_buffer(I),
762 status_ready_matrix => wfp_status_buffer_ready(I),
763 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
764 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
765 );
766
767 END GENERATE all_wfp_pointer;
768 -----------------------------------------------------------------------------
720
769
721 END beh;
770 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,393 +1,389
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER);
73 PORT (
73 PORT (
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 dma_fifo_burst_valid : OUT STD_LOGIC;
85 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_ren : IN STD_LOGIC;
87 dma_fifo_ren : IN STD_LOGIC;
88 dma_buffer_new : OUT STD_LOGIC;
88 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_full : IN STD_LOGIC;
91 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full_err : IN STD_LOGIC;
92 dma_buffer_full_err : IN STD_LOGIC;
93 ready_matrix_f0 : OUT STD_LOGIC;
93 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f1 : OUT STD_LOGIC;
94 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f2 : OUT STD_LOGIC;
95 ready_matrix_f2 : OUT STD_LOGIC;
96 error_buffer_full : OUT STD_LOGIC;
96 error_buffer_full : OUT STD_LOGIC;
97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 status_ready_matrix_f0 : IN STD_LOGIC;
98 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f1 : IN STD_LOGIC;
99 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f2 : IN STD_LOGIC;
100 status_ready_matrix_f2 : IN STD_LOGIC;
101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 END COMPONENT;
110 END COMPONENT;
111
111
112 COMPONENT lpp_lfr_ms_fsmdma
112 COMPONENT lpp_lfr_ms_fsmdma
113 PORT (
113 PORT (
114 clk : IN STD_ULOGIC;
114 clk : IN STD_ULOGIC;
115 rstn : IN STD_ULOGIC;
115 rstn : IN STD_ULOGIC;
116 run : IN STD_LOGIC;
116 run : IN STD_LOGIC;
117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 fifo_empty : IN STD_LOGIC;
120 fifo_empty : IN STD_LOGIC;
121 fifo_empty_threshold : IN STD_LOGIC;
121 fifo_empty_threshold : IN STD_LOGIC;
122 fifo_ren : OUT STD_LOGIC;
122 fifo_ren : OUT STD_LOGIC;
123 dma_fifo_valid_burst : OUT STD_LOGIC;
123 dma_fifo_valid_burst : OUT STD_LOGIC;
124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 dma_fifo_ren : IN STD_LOGIC;
125 dma_fifo_ren : IN STD_LOGIC;
126 dma_buffer_new : OUT STD_LOGIC;
126 dma_buffer_new : OUT STD_LOGIC;
127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 dma_buffer_full : IN STD_LOGIC;
129 dma_buffer_full : IN STD_LOGIC;
130 dma_buffer_full_err : IN STD_LOGIC;
130 dma_buffer_full_err : IN STD_LOGIC;
131 status_ready_matrix_f0 : IN STD_LOGIC;
131 status_ready_matrix_f0 : IN STD_LOGIC;
132 status_ready_matrix_f1 : IN STD_LOGIC;
132 status_ready_matrix_f1 : IN STD_LOGIC;
133 status_ready_matrix_f2 : IN STD_LOGIC;
133 status_ready_matrix_f2 : IN STD_LOGIC;
134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 ready_matrix_f0 : OUT STD_LOGIC;
140 ready_matrix_f0 : OUT STD_LOGIC;
141 ready_matrix_f1 : OUT STD_LOGIC;
141 ready_matrix_f1 : OUT STD_LOGIC;
142 ready_matrix_f2 : OUT STD_LOGIC;
142 ready_matrix_f2 : OUT STD_LOGIC;
143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 error_buffer_full : OUT STD_LOGIC);
146 error_buffer_full : OUT STD_LOGIC);
147 END COMPONENT;
147 END COMPONENT;
148
148
149 COMPONENT lpp_lfr_ms_FFT
149 COMPONENT lpp_lfr_ms_FFT
150 PORT (
150 PORT (
151 clk : IN STD_LOGIC;
151 clk : IN STD_LOGIC;
152 rstn : IN STD_LOGIC;
152 rstn : IN STD_LOGIC;
153 sample_valid : IN STD_LOGIC;
153 sample_valid : IN STD_LOGIC;
154 fft_read : IN STD_LOGIC;
154 fft_read : IN STD_LOGIC;
155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 sample_load : OUT STD_LOGIC;
156 sample_load : OUT STD_LOGIC;
157 fft_pong : OUT STD_LOGIC;
157 fft_pong : OUT STD_LOGIC;
158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_valid : OUT STD_LOGIC;
160 fft_data_valid : OUT STD_LOGIC;
161 fft_ready : OUT STD_LOGIC);
161 fft_ready : OUT STD_LOGIC);
162 END COMPONENT;
162 END COMPONENT;
163
163
164 COMPONENT lpp_lfr_filter
164 COMPONENT lpp_lfr_filter
165 GENERIC (
165 GENERIC (
166 Mem_use : INTEGER);
166 Mem_use : INTEGER);
167 PORT (
167 PORT (
168 sample : IN Samples(7 DOWNTO 0);
168 sample : IN Samples(7 DOWNTO 0);
169 sample_val : IN STD_LOGIC;
169 sample_val : IN STD_LOGIC;
170 clk : IN STD_LOGIC;
170 clk : IN STD_LOGIC;
171 rstn : IN STD_LOGIC;
171 rstn : IN STD_LOGIC;
172 data_shaping_SP0 : IN STD_LOGIC;
172 data_shaping_SP0 : IN STD_LOGIC;
173 data_shaping_SP1 : IN STD_LOGIC;
173 data_shaping_SP1 : IN STD_LOGIC;
174 data_shaping_R0 : IN STD_LOGIC;
174 data_shaping_R0 : IN STD_LOGIC;
175 data_shaping_R1 : IN STD_LOGIC;
175 data_shaping_R1 : IN STD_LOGIC;
176 data_shaping_R2 : IN STD_LOGIC;
176 data_shaping_R2 : IN STD_LOGIC;
177 sample_f0_val : OUT STD_LOGIC;
177 sample_f0_val : OUT STD_LOGIC;
178 sample_f1_val : OUT STD_LOGIC;
178 sample_f1_val : OUT STD_LOGIC;
179 sample_f2_val : OUT STD_LOGIC;
179 sample_f2_val : OUT STD_LOGIC;
180 sample_f3_val : OUT STD_LOGIC;
180 sample_f3_val : OUT STD_LOGIC;
181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
185 END COMPONENT;
185 END COMPONENT;
186
186
187 COMPONENT lpp_lfr
187 COMPONENT lpp_lfr
188 GENERIC (
188 GENERIC (
189 Mem_use : INTEGER;
189 Mem_use : INTEGER;
190 nb_data_by_buffer_size : INTEGER;
190 nb_data_by_buffer_size : INTEGER;
191 nb_word_by_buffer_size : INTEGER;
191 nb_word_by_buffer_size : INTEGER;
192 nb_snapshot_param_size : INTEGER;
192 nb_snapshot_param_size : INTEGER;
193 delta_vector_size : INTEGER;
193 delta_vector_size : INTEGER;
194 delta_vector_size_f0_2 : INTEGER;
194 delta_vector_size_f0_2 : INTEGER;
195 pindex : INTEGER;
195 pindex : INTEGER;
196 paddr : INTEGER;
196 paddr : INTEGER;
197 pmask : INTEGER;
197 pmask : INTEGER;
198 pirq_ms : INTEGER;
198 pirq_ms : INTEGER;
199 pirq_wfp : INTEGER;
199 pirq_wfp : INTEGER;
200 hindex : INTEGER;
200 hindex : INTEGER;
201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
202 );
202 );
203 PORT (
203 PORT (
204 clk : IN STD_LOGIC;
204 clk : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
206 sample_B : IN Samples(2 DOWNTO 0);
206 sample_B : IN Samples(2 DOWNTO 0);
207 sample_E : IN Samples(4 DOWNTO 0);
207 sample_E : IN Samples(4 DOWNTO 0);
208 sample_val : IN STD_LOGIC;
208 sample_val : IN STD_LOGIC;
209 apbi : IN apb_slv_in_type;
209 apbi : IN apb_slv_in_type;
210 apbo : OUT apb_slv_out_type;
210 apbo : OUT apb_slv_out_type;
211 ahbi : IN AHB_Mst_In_Type;
211 ahbi : IN AHB_Mst_In_Type;
212 ahbo : OUT AHB_Mst_Out_Type;
212 ahbo : OUT AHB_Mst_Out_Type;
213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
215 data_shaping_BW : OUT STD_LOGIC;
215 data_shaping_BW : OUT STD_LOGIC;
216 --
216 --
217 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
217 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
218 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
218 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
219 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
220 );
220 );
221 END COMPONENT;
221 END COMPONENT;
222
222
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
225 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
226 COMPONENT lpp_lfr_WFP_nMS
226 COMPONENT lpp_lfr_WFP_nMS
227 GENERIC (
227 GENERIC (
228 Mem_use : INTEGER;
228 Mem_use : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
232 delta_vector_size : INTEGER;
232 delta_vector_size : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
234 pindex : INTEGER;
234 pindex : INTEGER;
235 paddr : INTEGER;
235 paddr : INTEGER;
236 pmask : INTEGER;
236 pmask : INTEGER;
237 pirq_ms : INTEGER;
237 pirq_ms : INTEGER;
238 pirq_wfp : INTEGER;
238 pirq_wfp : INTEGER;
239 hindex : INTEGER;
239 hindex : INTEGER;
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
241 PORT (
241 PORT (
242 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
244 sample_B : IN Samples(2 DOWNTO 0);
244 sample_B : IN Samples(2 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
246 sample_val : IN STD_LOGIC;
246 sample_val : IN STD_LOGIC;
247 apbi : IN apb_slv_in_type;
247 apbi : IN apb_slv_in_type;
248 apbo : OUT apb_slv_out_type;
248 apbo : OUT apb_slv_out_type;
249 ahbi : IN AHB_Mst_In_Type;
249 ahbi : IN AHB_Mst_In_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
253 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_BW : OUT STD_LOGIC;
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
255 END COMPONENT;
255 END COMPONENT;
256 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
257
257
258 COMPONENT lpp_lfr_apbreg
258 COMPONENT lpp_lfr_apbreg
259 GENERIC (
259 GENERIC (
260 nb_data_by_buffer_size : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
261 nb_word_by_buffer_size : INTEGER;
262 nb_snapshot_param_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
263 delta_vector_size : INTEGER;
262 delta_vector_size : INTEGER;
264 delta_vector_size_f0_2 : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
265 pindex : INTEGER;
264 pindex : INTEGER;
266 paddr : INTEGER;
265 paddr : INTEGER;
267 pmask : INTEGER;
266 pmask : INTEGER;
268 pirq_ms : INTEGER;
267 pirq_ms : INTEGER;
269 pirq_wfp : INTEGER;
268 pirq_wfp : INTEGER;
270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
271 PORT (
270 PORT (
272 HCLK : IN STD_ULOGIC;
271 HCLK : IN STD_ULOGIC;
273 HRESETn : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
274 apbi : IN apb_slv_in_type;
273 apbi : IN apb_slv_in_type;
275 apbo : OUT apb_slv_out_type;
274 apbo : OUT apb_slv_out_type;
276 run_ms : OUT STD_LOGIC;
275 run_ms : OUT STD_LOGIC;
277 ready_matrix_f0 : IN STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
278 ready_matrix_f1 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
279 ready_matrix_f2 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
280 error_buffer_full : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
281 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
282 status_ready_matrix_f0 : OUT STD_LOGIC;
281 status_ready_matrix_f0 : OUT STD_LOGIC;
283 status_ready_matrix_f1 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
284 status_ready_matrix_f2 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
285 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
288 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
291 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
294 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
295 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
294 data_shaping_BW : OUT STD_LOGIC;
296 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
295 data_shaping_SP0 : OUT STD_LOGIC;
297 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
296 data_shaping_SP1 : OUT STD_LOGIC;
298 data_shaping_BW : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
299 data_shaping_SP0 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
300 data_shaping_SP1 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
301 data_shaping_R0 : OUT STD_LOGIC;
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 data_shaping_R1 : OUT STD_LOGIC;
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
303 data_shaping_R2 : OUT STD_LOGIC;
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
304 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
306 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
307 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
308 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
307 enable_f0 : OUT STD_LOGIC;
309 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
308 enable_f1 : OUT STD_LOGIC;
310 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
309 enable_f2 : OUT STD_LOGIC;
311 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
310 enable_f3 : OUT STD_LOGIC;
312 enable_f0 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
313 enable_f1 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
314 enable_f2 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
315 enable_f3 : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
316 burst_f0 : OUT STD_LOGIC;
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
317 burst_f1 : OUT STD_LOGIC;
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
318 burst_f2 : OUT STD_LOGIC;
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
319 run : OUT STD_LOGIC;
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
320 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
321 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
322 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
323 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
324 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
325 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
326 END COMPONENT;
322 END COMPONENT;
327
323
328 COMPONENT lpp_top_ms
324 COMPONENT lpp_top_ms
329 GENERIC (
325 GENERIC (
330 Mem_use : INTEGER;
326 Mem_use : INTEGER;
331 nb_burst_available_size : INTEGER;
327 nb_burst_available_size : INTEGER;
332 nb_snapshot_param_size : INTEGER;
328 nb_snapshot_param_size : INTEGER;
333 delta_snapshot_size : INTEGER;
329 delta_snapshot_size : INTEGER;
334 delta_f2_f0_size : INTEGER;
330 delta_f2_f0_size : INTEGER;
335 delta_f2_f1_size : INTEGER;
331 delta_f2_f1_size : INTEGER;
336 pindex : INTEGER;
332 pindex : INTEGER;
337 paddr : INTEGER;
333 paddr : INTEGER;
338 pmask : INTEGER;
334 pmask : INTEGER;
339 pirq_ms : INTEGER;
335 pirq_ms : INTEGER;
340 pirq_wfp : INTEGER;
336 pirq_wfp : INTEGER;
341 hindex_wfp : INTEGER;
337 hindex_wfp : INTEGER;
342 hindex_ms : INTEGER);
338 hindex_ms : INTEGER);
343 PORT (
339 PORT (
344 clk : IN STD_LOGIC;
340 clk : IN STD_LOGIC;
345 rstn : IN STD_LOGIC;
341 rstn : IN STD_LOGIC;
346 sample_B : IN Samples14v(2 DOWNTO 0);
342 sample_B : IN Samples14v(2 DOWNTO 0);
347 sample_E : IN Samples14v(4 DOWNTO 0);
343 sample_E : IN Samples14v(4 DOWNTO 0);
348 sample_val : IN STD_LOGIC;
344 sample_val : IN STD_LOGIC;
349 apbi : IN apb_slv_in_type;
345 apbi : IN apb_slv_in_type;
350 apbo : OUT apb_slv_out_type;
346 apbo : OUT apb_slv_out_type;
351 ahbi_ms : IN AHB_Mst_In_Type;
347 ahbi_ms : IN AHB_Mst_In_Type;
352 ahbo_ms : OUT AHB_Mst_Out_Type;
348 ahbo_ms : OUT AHB_Mst_Out_Type;
353 data_shaping_BW : OUT STD_LOGIC;
349 data_shaping_BW : OUT STD_LOGIC;
354 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
350 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
355 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
351 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
356 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
352 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
357 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
353 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
358
354
359 );
355 );
360 END COMPONENT;
356 END COMPONENT;
361
357
362 COMPONENT lpp_apbreg_ms_pointer
358 COMPONENT lpp_apbreg_ms_pointer
363 PORT (
359 PORT (
364 clk : IN STD_LOGIC;
360 clk : IN STD_LOGIC;
365 rstn : IN STD_LOGIC;
361 rstn : IN STD_LOGIC;
366 reg0_status_ready_matrix : IN STD_LOGIC;
362 reg0_status_ready_matrix : IN STD_LOGIC;
367 reg0_ready_matrix : OUT STD_LOGIC;
363 reg0_ready_matrix : OUT STD_LOGIC;
368 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
364 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
369 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
365 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
370 reg1_status_ready_matrix : IN STD_LOGIC;
366 reg1_status_ready_matrix : IN STD_LOGIC;
371 reg1_ready_matrix : OUT STD_LOGIC;
367 reg1_ready_matrix : OUT STD_LOGIC;
372 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
368 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
369 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
374 ready_matrix : IN STD_LOGIC;
370 ready_matrix : IN STD_LOGIC;
375 status_ready_matrix : OUT STD_LOGIC;
371 status_ready_matrix : OUT STD_LOGIC;
376 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
372 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
377 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
373 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
378 END COMPONENT;
374 END COMPONENT;
379
375
380 COMPONENT lpp_lfr_ms_reg_head
376 COMPONENT lpp_lfr_ms_reg_head
381 PORT (
377 PORT (
382 clk : IN STD_LOGIC;
378 clk : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
379 rstn : IN STD_LOGIC;
384 in_wen : IN STD_LOGIC;
380 in_wen : IN STD_LOGIC;
385 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
381 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
386 in_full : IN STD_LOGIC;
382 in_full : IN STD_LOGIC;
387 in_empty : IN STD_LOGIC;
383 in_empty : IN STD_LOGIC;
388 out_wen : OUT STD_LOGIC;
384 out_wen : OUT STD_LOGIC;
389 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
385 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
390 out_full : OUT STD_LOGIC);
386 out_full : OUT STD_LOGIC);
391 END COMPONENT;
387 END COMPONENT;
392
388
393 END lpp_lfr_pkg;
389 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,576 +1,471
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
42
42
43 GENERIC (
43 GENERIC (
44 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
45 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
46 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
47 nb_word_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
49 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
50 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
51
51
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
55
56 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59
59
60 --config
60 --config
61 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68
68
69 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
73
73
74 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
77
77
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83
84
85 -- REG DMA
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93
85 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
86 -- INPUT
95 -- INPUT
87 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
89
98
90 --f0
99 --f0
91 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 data_f0_in_valid : IN STD_LOGIC;
100 data_f0_in_valid : IN STD_LOGIC;
93 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
94 --f1
102 --f1
95 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data_f1_in_valid : IN STD_LOGIC;
103 data_f1_in_valid : IN STD_LOGIC;
97 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
98 --f2
105 --f2
99 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 data_f2_in_valid : IN STD_LOGIC;
106 data_f2_in_valid : IN STD_LOGIC;
101 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 --f3
108 --f3
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 data_f3_in_valid : IN STD_LOGIC;
109 data_f3_in_valid : IN STD_LOGIC;
105 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106
111
107 ---------------------------------------------------------------------------
112 ---------------------------------------------------------------------------
108 -- DMA --------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
109
114
110 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
111 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
112 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
113 dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
114 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
115 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
116 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
118
123
119 );
124 );
120
125
121 END lpp_waveform;
126 END lpp_waveform;
122
127
123 ARCHITECTURE beh OF lpp_waveform IS
128 ARCHITECTURE beh OF lpp_waveform IS
124 SIGNAL start_snapshot_f0 : STD_LOGIC;
129 SIGNAL start_snapshot_f0 : STD_LOGIC;
125 SIGNAL start_snapshot_f1 : STD_LOGIC;
130 SIGNAL start_snapshot_f1 : STD_LOGIC;
126 SIGNAL start_snapshot_f2 : STD_LOGIC;
131 SIGNAL start_snapshot_f2 : STD_LOGIC;
127
132
128 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
129 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
130 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
131 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
132
137
133 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137
142
138 SIGNAL data_f0_out_valid : STD_LOGIC;
143 SIGNAL data_f0_out_valid : STD_LOGIC;
139 SIGNAL data_f1_out_valid : STD_LOGIC;
144 SIGNAL data_f1_out_valid : STD_LOGIC;
140 SIGNAL data_f2_out_valid : STD_LOGIC;
145 SIGNAL data_f2_out_valid : STD_LOGIC;
141 SIGNAL data_f3_out_valid : STD_LOGIC;
146 SIGNAL data_f3_out_valid : STD_LOGIC;
142 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
143 --
148 --
144 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
145 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
146 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 --
162 --
158 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 --
167 --
163 SIGNAL run : STD_LOGIC;
168 SIGNAL run : STD_LOGIC;
164 --
169 --
165 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
166 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
167 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
168 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
169 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
170 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 --
177 --
173
178
174 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
175 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
179
184
180 --
185 --
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
181
188
182 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
183
184
190
185 BEGIN -- beh
191 BEGIN -- beh
186
192
187 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
188
194
189 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
195 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
190 GENERIC MAP (
196 GENERIC MAP (
191 delta_vector_size => delta_vector_size,
197 delta_vector_size => delta_vector_size,
192 delta_vector_size_f0_2 => delta_vector_size_f0_2
198 delta_vector_size_f0_2 => delta_vector_size_f0_2
193 )
199 )
194 PORT MAP (
200 PORT MAP (
195 clk => clk,
201 clk => clk,
196 rstn => rstn,
202 rstn => rstn,
197 reg_run => reg_run,
203 reg_run => reg_run,
198 reg_start_date => reg_start_date,
204 reg_start_date => reg_start_date,
199 reg_delta_snapshot => reg_delta_snapshot,
205 reg_delta_snapshot => reg_delta_snapshot,
200 reg_delta_f0 => reg_delta_f0,
206 reg_delta_f0 => reg_delta_f0,
201 reg_delta_f0_2 => reg_delta_f0_2,
207 reg_delta_f0_2 => reg_delta_f0_2,
202 reg_delta_f1 => reg_delta_f1,
208 reg_delta_f1 => reg_delta_f1,
203 reg_delta_f2 => reg_delta_f2,
209 reg_delta_f2 => reg_delta_f2,
204 coarse_time => coarse_time(30 DOWNTO 0),
210 coarse_time => coarse_time(30 DOWNTO 0),
205 data_f0_valid => data_f0_in_valid,
211 data_f0_valid => data_f0_in_valid,
206 data_f2_valid => data_f2_in_valid,
212 data_f2_valid => data_f2_in_valid,
207 start_snapshot_f0 => start_snapshot_f0,
213 start_snapshot_f0 => start_snapshot_f0,
208 start_snapshot_f1 => start_snapshot_f1,
214 start_snapshot_f1 => start_snapshot_f1,
209 start_snapshot_f2 => start_snapshot_f2,
215 start_snapshot_f2 => start_snapshot_f2,
210 wfp_on => run);
216 wfp_on => run);
211
217
212 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
218 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
213 GENERIC MAP (
219 GENERIC MAP (
214 data_size => data_size,
220 data_size => data_size,
215 nb_snapshot_param_size => nb_snapshot_param_size)
221 nb_snapshot_param_size => nb_snapshot_param_size)
216 PORT MAP (
222 PORT MAP (
217 clk => clk,
223 clk => clk,
218 rstn => rstn,
224 rstn => rstn,
219 run => run,
225 run => run,
220 enable => enable_f0,
226 enable => enable_f0,
221 burst_enable => burst_f0,
227 burst_enable => burst_f0,
222 nb_snapshot_param => nb_snapshot_param,
228 nb_snapshot_param => nb_snapshot_param,
223 start_snapshot => start_snapshot_f0,
229 start_snapshot => start_snapshot_f0,
224 data_in => data_f0_in,
230 data_in => data_f0_in,
225 data_in_valid => data_f0_in_valid,
231 data_in_valid => data_f0_in_valid,
226 data_out => data_f0_out,
232 data_out => data_f0_out,
227 data_out_valid => data_f0_out_valid);
233 data_out_valid => data_f0_out_valid);
228
234
229 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
235 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
230
236
231 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
237 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
232 GENERIC MAP (
238 GENERIC MAP (
233 data_size => data_size,
239 data_size => data_size,
234 nb_snapshot_param_size => nb_snapshot_param_size+1)
240 nb_snapshot_param_size => nb_snapshot_param_size+1)
235 PORT MAP (
241 PORT MAP (
236 clk => clk,
242 clk => clk,
237 rstn => rstn,
243 rstn => rstn,
238 run => run,
244 run => run,
239 enable => enable_f1,
245 enable => enable_f1,
240 burst_enable => burst_f1,
246 burst_enable => burst_f1,
241 nb_snapshot_param => nb_snapshot_param_more_one,
247 nb_snapshot_param => nb_snapshot_param_more_one,
242 start_snapshot => start_snapshot_f1,
248 start_snapshot => start_snapshot_f1,
243 data_in => data_f1_in,
249 data_in => data_f1_in,
244 data_in_valid => data_f1_in_valid,
250 data_in_valid => data_f1_in_valid,
245 data_out => data_f1_out,
251 data_out => data_f1_out,
246 data_out_valid => data_f1_out_valid);
252 data_out_valid => data_f1_out_valid);
247
253
248 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
254 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
249 GENERIC MAP (
255 GENERIC MAP (
250 data_size => data_size,
256 data_size => data_size,
251 nb_snapshot_param_size => nb_snapshot_param_size+1)
257 nb_snapshot_param_size => nb_snapshot_param_size+1)
252 PORT MAP (
258 PORT MAP (
253 clk => clk,
259 clk => clk,
254 rstn => rstn,
260 rstn => rstn,
255 run => run,
261 run => run,
256 enable => enable_f2,
262 enable => enable_f2,
257 burst_enable => burst_f2,
263 burst_enable => burst_f2,
258 nb_snapshot_param => nb_snapshot_param_more_one,
264 nb_snapshot_param => nb_snapshot_param_more_one,
259 start_snapshot => start_snapshot_f2,
265 start_snapshot => start_snapshot_f2,
260 data_in => data_f2_in,
266 data_in => data_f2_in,
261 data_in_valid => data_f2_in_valid,
267 data_in_valid => data_f2_in_valid,
262 data_out => data_f2_out,
268 data_out => data_f2_out,
263 data_out_valid => data_f2_out_valid);
269 data_out_valid => data_f2_out_valid);
264
270
265 lpp_waveform_burst_f3 : lpp_waveform_burst
271 lpp_waveform_burst_f3 : lpp_waveform_burst
266 GENERIC MAP (
272 GENERIC MAP (
267 data_size => data_size)
273 data_size => data_size)
268 PORT MAP (
274 PORT MAP (
269 clk => clk,
275 clk => clk,
270 rstn => rstn,
276 rstn => rstn,
271 run => run,
277 run => run,
272 enable => enable_f3,
278 enable => enable_f3,
273 data_in => data_f3_in,
279 data_in => data_f3_in,
274 data_in_valid => data_f3_in_valid,
280 data_in_valid => data_f3_in_valid,
275 data_out => data_f3_out,
281 data_out => data_f3_out,
276 data_out_valid => data_f3_out_valid);
282 data_out_valid => data_f3_out_valid);
277
283
278 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
279 -- DEBUG -- SNAPSHOT OUT
285 -- DEBUG -- SNAPSHOT OUT
280 --debug_f0_data_valid <= data_f0_out_valid;
286 --debug_f0_data_valid <= data_f0_out_valid;
281 --debug_f0_data <= data_f0_out;
287 --debug_f0_data <= data_f0_out;
282 --debug_f1_data_valid <= data_f1_out_valid;
288 --debug_f1_data_valid <= data_f1_out_valid;
283 --debug_f1_data <= data_f1_out;
289 --debug_f1_data <= data_f1_out;
284 --debug_f2_data_valid <= data_f2_out_valid;
290 --debug_f2_data_valid <= data_f2_out_valid;
285 --debug_f2_data <= data_f2_out;
291 --debug_f2_data <= data_f2_out;
286 --debug_f3_data_valid <= data_f3_out_valid;
292 --debug_f3_data_valid <= data_f3_out_valid;
287 --debug_f3_data <= data_f3_out;
293 --debug_f3_data <= data_f3_out;
288 -----------------------------------------------------------------------------
294 -----------------------------------------------------------------------------
289
295
290 PROCESS (clk, rstn)
296 PROCESS (clk, rstn)
291 BEGIN -- PROCESS
297 BEGIN -- PROCESS
292 IF rstn = '0' THEN -- asynchronous reset (active low)
298 IF rstn = '0' THEN -- asynchronous reset (active low)
293 time_reg1 <= (OTHERS => '0');
299 time_reg1 <= (OTHERS => '0');
294 time_reg2 <= (OTHERS => '0');
300 time_reg2 <= (OTHERS => '0');
295 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
301 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
296 time_reg1 <= fine_time & coarse_time;
302 time_reg1 <= fine_time & coarse_time;
297 time_reg2 <= time_reg1;
303 time_reg2 <= time_reg1;
298 END IF;
304 END IF;
299 END PROCESS;
305 END PROCESS;
300
306
301 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
307 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
302 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
308 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
303 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
309 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
304 PORT MAP (
310 PORT MAP (
305 HCLK => clk,
311 HCLK => clk,
306 HRESETn => rstn,
312 HRESETn => rstn,
307 run => run,
313 run => run,
308 valid_in => valid_in(I),
314 valid_in => valid_in(I),
309 ack_in => valid_ack(I),
315 ack_in => valid_ack(I),
310 time_in => time_reg2, -- Todo
316 time_in => time_reg2, -- Todo
311 valid_out => valid_out(I),
317 valid_out => valid_out(I),
312 time_out => time_out(I), -- Todo
318 time_out => time_out(I), -- Todo
313 error => status_new_err(I));
319 error => status_new_err(I));
314 END GENERATE all_input_valid;
320 END GENERATE all_input_valid;
315
321
316 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
322 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
317 data_f0_out((16*6)-1 DOWNTO 16*5) &
323 data_f0_out((16*6)-1 DOWNTO 16*5) &
318 data_f0_out((16*3)-1 DOWNTO 16*2) &
324 data_f0_out((16*3)-1 DOWNTO 16*2) &
319 data_f0_out((16*4)-1 DOWNTO 16*3) &
325 data_f0_out((16*4)-1 DOWNTO 16*3) &
320 data_f0_out((16*1)-1 DOWNTO 16*0) &
326 data_f0_out((16*1)-1 DOWNTO 16*0) &
321 data_f0_out((16*2)-1 DOWNTO 16*1) ;
327 data_f0_out((16*2)-1 DOWNTO 16*1) ;
322
328
323 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
329 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
324 data_f1_out((16*6)-1 DOWNTO 16*5) &
330 data_f1_out((16*6)-1 DOWNTO 16*5) &
325 data_f1_out((16*3)-1 DOWNTO 16*2) &
331 data_f1_out((16*3)-1 DOWNTO 16*2) &
326 data_f1_out((16*4)-1 DOWNTO 16*3) &
332 data_f1_out((16*4)-1 DOWNTO 16*3) &
327 data_f1_out((16*1)-1 DOWNTO 16*0) &
333 data_f1_out((16*1)-1 DOWNTO 16*0) &
328 data_f1_out((16*2)-1 DOWNTO 16*1) ;
334 data_f1_out((16*2)-1 DOWNTO 16*1) ;
329
335
330 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
336 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
331 data_f2_out((16*6)-1 DOWNTO 16*5) &
337 data_f2_out((16*6)-1 DOWNTO 16*5) &
332 data_f2_out((16*3)-1 DOWNTO 16*2) &
338 data_f2_out((16*3)-1 DOWNTO 16*2) &
333 data_f2_out((16*4)-1 DOWNTO 16*3) &
339 data_f2_out((16*4)-1 DOWNTO 16*3) &
334 data_f2_out((16*1)-1 DOWNTO 16*0) &
340 data_f2_out((16*1)-1 DOWNTO 16*0) &
335 data_f2_out((16*2)-1 DOWNTO 16*1) ;
341 data_f2_out((16*2)-1 DOWNTO 16*1) ;
336
342
337 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
343 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
338 data_f3_out((16*6)-1 DOWNTO 16*5) &
344 data_f3_out((16*6)-1 DOWNTO 16*5) &
339 data_f3_out((16*3)-1 DOWNTO 16*2) &
345 data_f3_out((16*3)-1 DOWNTO 16*2) &
340 data_f3_out((16*4)-1 DOWNTO 16*3) &
346 data_f3_out((16*4)-1 DOWNTO 16*3) &
341 data_f3_out((16*1)-1 DOWNTO 16*0) &
347 data_f3_out((16*1)-1 DOWNTO 16*0) &
342 data_f3_out((16*2)-1 DOWNTO 16*1) ;
348 data_f3_out((16*2)-1 DOWNTO 16*1) ;
343
349
344 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
350 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
345 data_out(0, I) <= data_f0_out_swap(I);
351 data_out(0, I) <= data_f0_out_swap(I);
346 data_out(1, I) <= data_f1_out_swap(I);
352 data_out(1, I) <= data_f1_out_swap(I);
347 data_out(2, I) <= data_f2_out_swap(I);
353 data_out(2, I) <= data_f2_out_swap(I);
348 data_out(3, I) <= data_f3_out_swap(I);
354 data_out(3, I) <= data_f3_out_swap(I);
349 END GENERATE all_bit_of_data_out;
355 END GENERATE all_bit_of_data_out;
350
356
351 -----------------------------------------------------------------------------
357 -----------------------------------------------------------------------------
352 -- TODO : debug
358 -- TODO : debug
353 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
354 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
360 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
355 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
361 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
356 time_out_2(J, I) <= time_out(J)(I);
362 time_out_2(J, I) <= time_out(J)(I);
357 END GENERATE all_sample_of_time_out;
363 END GENERATE all_sample_of_time_out;
358 END GENERATE all_bit_of_time_out;
364 END GENERATE all_bit_of_time_out;
359
365
360 -- DEBUG --
361 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
362 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
363 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
364 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
365
366 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
367 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
368 -- time_out_2(J, I) <= time_out_debug(J)(I);
369 -- END GENERATE all_sample_of_time_out;
370 --END GENERATE all_bit_of_time_out;
371 -- DEBUG --
372
373 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
366 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
374 GENERIC MAP (tech => tech,
367 GENERIC MAP (tech => tech,
375 nb_data_by_buffer_size => nb_data_by_buffer_size)
368 nb_data_by_buffer_size => nb_data_by_buffer_size)
376 PORT MAP (
369 PORT MAP (
377 clk => clk,
370 clk => clk,
378 rstn => rstn,
371 rstn => rstn,
379 run => run,
372 run => run,
380 nb_data_by_buffer => nb_data_by_buffer,
373 nb_data_by_buffer => nb_data_by_buffer,
381 data_in_valid => valid_out,
374 data_in_valid => valid_out,
382 data_in_ack => valid_ack,
375 data_in_ack => valid_ack,
383 data_in => data_out,
376 data_in => data_out,
384 time_in => time_out_2,
377 time_in => time_out_2,
385
378
386 data_out => wdata,
379 data_out => wdata,
387 data_out_wen => data_wen,
380 data_out_wen => data_wen,
388 full_almost => full_almost,
381 full_almost => full_almost,
389 full => full);
382 full => full,
383
384 time_out => arbiter_time_out,
385 time_out_new => arbiter_time_out_new
386
387 );
390
388
391 -----------------------------------------------------------------------------
389 -----------------------------------------------------------------------------
392 -- DEBUG -- SNAPSHOT IN
393 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
394 --debug_f0_data_fifo_in <= wdata;
395 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
396 --debug_f1_data_fifo_in <= wdata;
397 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
398 --debug_f2_data_fifo_in <= wdata;
399 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
400 --debug_f3_data_fifo_in <= wdata;s
401 -----------------------------------------------------------------------------
390 -----------------------------------------------------------------------------
402
391
403
404 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
405 -- GENERIC MAP (
406 -- tech => tech,
407 -- Mem_use => use_RAM,
408 -- EMPTY_ALMOST_LIMIT => 16,
409 -- FULL_ALMOST_LIMIT => 5,
410 -- DataSz => 32,
411 -- AddrSz => 7
412 -- )
413 -- PORT MAP (
414 -- clk => clk,
415 -- rstn => rstn,
416 -- run => run,
417 -- empty_almost => s_empty_almost,
418 -- empty => s_empty,
419 -- r_en => s_data_ren,
420 -- r_data => s_rdata,
421 -- full_almost => full_almost,
422 -- full => full,
423 -- w_en => data_wen,
424 -- w_data => wdata);
425
426 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
427 -- PORT MAP (
428 -- clk => clk,
429 -- rstn => rstn,
430 -- run => run,
431 -- o_empty_almost => empty_almost,
432 -- o_empty => empty,
433
434 -- o_data_ren => data_ren,
435 -- o_rdata_0 => data_f0_data_out,
436 -- o_rdata_1 => data_f1_data_out,
437 -- o_rdata_2 => data_f2_data_out,
438 -- o_rdata_3 => data_f3_data_out,
439
440 -- i_empty_almost => s_empty_almost,
441 -- i_empty => s_empty,
442 -- i_data_ren => s_data_ren,
443 -- i_rdata => s_rdata);
444
445 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
392 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
446 lpp_fifo_1: lpp_fifo
393 lpp_fifo_1: lpp_fifo
447 GENERIC MAP (
394 GENERIC MAP (
448 tech => tech,
395 tech => tech,
449 Mem_use => use_RAM,
396 Mem_use => use_RAM,
450 EMPTY_THRESHOLD_LIMIT => 15,
397 EMPTY_THRESHOLD_LIMIT => 15,
451 FULL_THRESHOLD_LIMIT => 3,
398 FULL_THRESHOLD_LIMIT => 3,
452 DataSz => 32,
399 DataSz => 32,
453 AddrSz => 7)
400 AddrSz => 7)
454 PORT MAP (
401 PORT MAP (
455 clk => clk,
402 clk => clk,
456 rstn => rstn,
403 rstn => rstn,
457 reUse => '0',
404 reUse => '0',
458 run => run,
405 run => run,
459 ren => data_ren(I),
406 ren => data_ren(I),
460 rdata => s_rdata_v((I+1)*32-1 downto I*32),
407 rdata => s_rdata_v((I+1)*32-1 downto I*32),
461 wen => data_wen(I),
408 wen => data_wen(I),
462 wdata => wdata,
409 wdata => wdata,
463 empty => empty(I),
410 empty => empty(I),
464 full => full(I),
411 full => full(I),
465 full_almost => OPEN,
412 full_almost => OPEN,
466 empty_threshold => empty_almost(I),
413 empty_threshold => empty_almost(I),
467 full_threshold => full_almost(I) );
414 full_threshold => full_almost(I) );
468
415
469 END GENERATE generate_all_fifo;
416 END GENERATE generate_all_fifo;
470
417
471
472 ----empty <= s_empty;
473 ----empty_almost <= s_empty_almost;
474 ----s_data_ren <= data_ren;
475
476 --data_f0_data_out <= s_rdata_v(31 downto 0);
477 --data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
478 --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
479 --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
480
481 --data_ren <= data_f3_data_out_ren &
482 -- data_f2_data_out_ren &
483 -- data_f1_data_out_ren &
484 -- data_f0_data_out_ren;
485
486 --lpp_waveform_gen_address_1 : lpp_waveform_genaddress
487 -- GENERIC MAP (
488 -- nb_data_by_buffer_size => nb_word_by_buffer_size)
489 -- PORT MAP (
490 -- clk => clk,
491 -- rstn => rstn,
492 -- run => run,
493
494 -- -------------------------------------------------------------------------
495 -- -- CONFIG
496 -- -------------------------------------------------------------------------
497 -- nb_data_by_buffer => nb_word_by_buffer,
498
499 -- addr_data_f0 => addr_data_f0,
500 -- addr_data_f1 => addr_data_f1,
501 -- addr_data_f2 => addr_data_f2,
502 -- addr_data_f3 => addr_data_f3,
503 -- -------------------------------------------------------------------------
504 -- -- CTRL
505 -- -------------------------------------------------------------------------
506 -- -- IN
507 -- empty => empty,
508 -- empty_almost => empty_almost,
509 -- data_ren => data_ren,
510
511 -- -------------------------------------------------------------------------
512 -- -- STATUS
513 -- -------------------------------------------------------------------------
514 -- status_full => status_full_s,
515 -- status_full_ack => status_full_ack,
516 -- status_full_err => status_full_err,
517
518 -- -------------------------------------------------------------------------
519 -- -- ADDR DATA OUT
520 -- -------------------------------------------------------------------------
521 -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
522 -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
523 -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
524 -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
525
526 -- data_f0_data_out_valid => data_f0_data_out_valid,
527 -- data_f1_data_out_valid => data_f1_data_out_valid,
528 -- data_f2_data_out_valid => data_f2_data_out_valid,
529 -- data_f3_data_out_valid => data_f3_data_out_valid,
530
531 -- data_f0_addr_out => data_f0_addr_out,
532 -- data_f1_addr_out => data_f1_addr_out,
533 -- data_f2_addr_out => data_f2_addr_out,
534 -- data_f3_addr_out => data_f3_addr_out
535 -- );
536 --status_full <= status_full_s;
537
538
539 -----------------------------------------------------------------------------
418 -----------------------------------------------------------------------------
540 --
419 --
541 -----------------------------------------------------------------------------
420 -----------------------------------------------------------------------------
542
421
543 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
422 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
423
424 PROCESS (clk, rstn)
425 BEGIN
426 IF rstn = '0' THEN
427 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
428 ELSIF clk'event AND clk = '1' THEN
429 IF run = '0' THEN
430 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
431 ELSE
432 IF arbiter_time_out_new(I) = '0' THEN
433 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
434 END IF;
435 END IF;
436 END IF;
437 END PROCESS;
438
544 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
439 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
545 PORT MAP (
440 PORT MAP (
546 clk => clk,
441 clk => clk,
547 rstn => rstn,
442 rstn => rstn,
548 run => run,
443 run => run,
549
444
550 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
445 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I),
551
446
552 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
447 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
553 fifo_empty => empty(I),
448 fifo_empty => empty(I),
554 fifo_empty_threshold => empty_almost(I),
449 fifo_empty_threshold => empty_almost(I),
555 fifo_ren => data_ren(I),
450 fifo_ren => data_ren(I),
556
451
557 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
452 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
558 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
453 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
559 dma_fifo_ren => dma_fifo_ren(I),
454 dma_fifo_ren => dma_fifo_ren(I),
560 dma_buffer_new => dma_buffer_new(I),
455 dma_buffer_new => dma_buffer_new(I),
561 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
456 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
562 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
457 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
563 dma_buffer_full => dma_buffer_full(I),
458 dma_buffer_full => dma_buffer_full(I),
564 dma_buffer_full_err => dma_buffer_full_err(I),
459 dma_buffer_full_err => dma_buffer_full_err(I),
565
460
566 status_buffer_ready => status_buffer_ready(I), -- TODO
461 status_buffer_ready => status_buffer_ready(I), -- TODO
567 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
462 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
568 length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO
463 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
569 ready_buffer => ready_buffer(I), -- TODO
464 ready_buffer => ready_buffer(I), -- TODO
570 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
465 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
571 error_buffer_full => error_buffer_full(I)); -- TODO
466 error_buffer_full => error_buffer_full(I)); -- TODO
572
467
573 END GENERATE all_channel;
468 END GENERATE all_channel;
574
469
575
470
576 END beh;
471 END beh;
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@@ -1,98 +1,100
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25
25
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29
29
30
30
31 ENTITY lpp_waveform_dma_genvalid IS
31 ENTITY lpp_waveform_dma_genvalid IS
32 PORT (
32 PORT (
33 HCLK : IN STD_LOGIC;
33 HCLK : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
35 run : IN STD_LOGIC;
36
36
37 valid_in : IN STD_LOGIC;
37 valid_in : IN STD_LOGIC;
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
39
39
40 ack_in : IN STD_LOGIC;
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 error : OUT STD_LOGIC
43 error : OUT STD_LOGIC
44 );
44 );
45 END;
45 END;
46
46
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
48 TYPE state_fsm IS (IDLE, VALID);
48 TYPE state_fsm IS (IDLE, VALID);
49 SIGNAL state : state_fsm;
49 SIGNAL state : state_fsm;
50 BEGIN
50 BEGIN
51
51
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
53 BEGIN
53 BEGIN
54 IF HRESETn = '0' THEN
54 IF HRESETn = '0' THEN
55 state <= IDLE;
55 state <= IDLE;
56 valid_out <= '0';
56 valid_out <= '0';
57 error <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
58 time_out <= (OTHERS => '0');
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
60 CASE state IS
60 IF run = '1' THEN
61 WHEN IDLE =>
61 CASE state IS
62
62 WHEN IDLE =>
63 valid_out <= '0';
63
64 error <= '0';
64 valid_out <= valid_in;
65 IF run = '1' AND valid_in = '1' THEN
65 error <= '0';
66 state <= VALID;
67 valid_out <= '1';
68 time_out <= time_in;
66 time_out <= time_in;
69 END IF;
70
67
71 WHEN VALID =>
68 IF valid_in = '1' THEN
72 IF run = '0' THEN
69 state <= VALID;
73 state <= IDLE;
70 END IF;
74 valid_out <= '0';
71
75 error <= '0';
72 WHEN VALID =>
76 ELSE
77 IF valid_in = '1' THEN
73 IF valid_in = '1' THEN
78 IF ack_in = '1' THEN
74 IF ack_in = '1' THEN
79 state <= VALID;
75 state <= VALID;
80 valid_out <= '1';
76 valid_out <= '1';
81 time_out <= time_in;
77 time_out <= time_in;
82 ELSE
78 ELSE
83 state <= IDLE;
79 state <= IDLE;
84 error <= '1';
80 error <= '1';
85 valid_out <= '0';
81 valid_out <= '0';
86 END IF;
82 END IF;
87 ELSIF ack_in = '1' THEN
83 ELSIF ack_in = '1' THEN
88 state <= IDLE;
84 state <= IDLE;
89 valid_out <= '0';
85 valid_out <= '0';
90 END IF;
86 END IF;
91 END IF;
87
92
88 WHEN OTHERS => NULL;
93 WHEN OTHERS => NULL;
89 END CASE;
94 END CASE;
90
91 ELSE
92 state <= IDLE;
93 valid_out <= '0';
94 error <= '0';
95 time_out <= (OTHERS => '0');
96 END IF;
95 END IF;
97 END IF;
96 END PROCESS FSM_SELECT_ADDRESS;
98 END PROCESS FSM_SELECT_ADDRESS;
97
99
98 END Behavioral;
100 END Behavioral;
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@@ -1,394 +1,264
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
31 GENERIC(
31 GENERIC(
32 tech : INTEGER := 0;
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER := 11
33 nb_data_by_buffer_size : INTEGER := 11
34 );
34 );
35 PORT(
35 PORT(
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- SNAPSHOT INTERFACE (INPUT)
42 -- SNAPSHOT INTERFACE (INPUT)
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48
49
49 ---------------------------------------------------------------------------
50 ---------------------------------------------------------------------------
50 -- FIFO INTERFACE (OUTPUT)
51 -- FIFO INTERFACE (OUTPUT)
51 ---------------------------------------------------------------------------
52 ---------------------------------------------------------------------------
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
56 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57
58 ---------------------------------------------------------------------------
59 -- TIME INTERFACE (OUTPUT)
60 ---------------------------------------------------------------------------
61 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
62 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
56
63
57 );
64 );
58 END ENTITY;
65 END ENTITY;
59
66
60
67
61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
68 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
69 TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
63 SIGNAL state : state_type_fifo_arbiter;
70 SIGNAL state : state_type_fifo_arbiter;
64
71
65 -----------------------------------------------------------------------------
72 -----------------------------------------------------------------------------
66 -- DATA MUX
73 -- DATA MUX
67 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
75 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
78
81
79 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
80 -- RR and SELECTION
83 -- RR and SELECTION
81 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
86 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL sel_reg : STD_LOGIC;
88 SIGNAL sel_reg : STD_LOGIC;
86 SIGNAL sel_ack : STD_LOGIC;
89 SIGNAL sel_ack : STD_LOGIC;
87 SIGNAL no_sel : STD_LOGIC;
90 SIGNAL no_sel : STD_LOGIC;
88
91
89 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
90 -- REG
93 -- REG
91 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
92 SIGNAL count_enable : STD_LOGIC;
95 SIGNAL count_enable : STD_LOGIC;
93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
96 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
97 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95
98
96 --SIGNAL shift_data_enable : STD_LOGIC;
99 SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
99
100 --SIGNAL shift_time_enable : STD_LOGIC;
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
103
100
104 BEGIN
101 BEGIN
105
102
106 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
107 -- CONTROL
104 -- CONTROL
108 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
109 PROCESS (clk, rstn)
106 PROCESS (clk, rstn)
110 BEGIN -- PROCESS
107 BEGIN -- PROCESS
111 IF rstn = '0' THEN -- asynchronous reset (active low)
108 IF rstn = '0' THEN -- asynchronous reset (active low)
112 count_enable <= '0';
109 count_enable <= '0';
113 data_in_ack <= (OTHERS => '0');
110 data_in_ack <= (OTHERS => '0');
114 data_out_wen <= (OTHERS => '1');
111 data_out_wen <= (OTHERS => '1');
115 sel_ack <= '0';
112 sel_ack <= '0';
116 state <= IDLE;
113 state <= IDLE;
114 time_out <= (OTHERS => '0');
115 time_out_new <= (OTHERS => '0');
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
116 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 count_enable <= '0';
117 count_enable <= '0';
119 data_in_ack <= (OTHERS => '0');
118 data_in_ack <= (OTHERS => '0');
120 data_out_wen <= (OTHERS => '1');
119 data_out_wen <= (OTHERS => '1');
121 sel_ack <= '0';
120 sel_ack <= '0';
121 time_out_new <= (OTHERS => '0');
122 IF run = '0' THEN
122 IF run = '0' THEN
123 state <= IDLE;
123 state <= IDLE;
124 time_out <= (OTHERS => '0');
124 ELSE
125 ELSE
125 CASE state IS
126 CASE state IS
126 WHEN IDLE =>
127 WHEN IDLE =>
127 IF no_sel = '0' THEN
128 IF no_sel = '0' THEN
128 state <= TIME1;
129 state <= DATA1;
129 END IF;
130 END IF;
130 WHEN TIME1 =>
131 WHEN DATA1 =>
131 count_enable <= '1';
132 count_enable <= '1';
132 IF UNSIGNED(count) = 0 THEN
133 IF UNSIGNED(count) = 0 THEN
133 state <= TIME2;
134 time_out <= time_sel;
134 data_out_wen <= NOT sel;
135 time_out_new <= sel;
135 data_out <= data_sel(0);
136 ELSE
137 state <= DATA1;
138 END IF;
136 END IF;
139 WHEN TIME2 =>
140 data_out_wen <= NOT sel;
137 data_out_wen <= NOT sel;
141 data_out <= data_sel(1) ;
138 data_out <= data_sel(0);
142 state <= DATA1;
143 WHEN DATA1 =>
144 data_out_wen <= NOT sel;
145 data_out <= data_sel(2);
146 state <= DATA2;
139 state <= DATA2;
147 WHEN DATA2 =>
140 WHEN DATA2 =>
148 data_out_wen <= NOT sel;
141 data_out_wen <= NOT sel;
149 data_out <= data_sel(3);
142 data_out <= data_sel(1);
150 state <= DATA3;
143 state <= DATA3;
151 WHEN DATA3 =>
144 WHEN DATA3 =>
152 data_out_wen <= NOT sel;
145 data_out_wen <= NOT sel;
153 data_out <= data_sel(4);
146 data_out <= data_sel(2);
154 state <= LAST;
147 state <= LAST;
155 data_in_ack <= sel;
148 data_in_ack <= sel;
156 WHEN LAST =>
149 WHEN LAST =>
157 state <= IDLE;
150 state <= IDLE;
158 sel_ack <= '1';
151 sel_ack <= '1';
159
152
160 WHEN OTHERS => NULL;
153 WHEN OTHERS => NULL;
161 END CASE;
154 END CASE;
162 END IF;
155 END IF;
163 END IF;
156 END IF;
164 END PROCESS;
157 END PROCESS;
165 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
166
167
168 --PROCESS (clk, rstn)
169 --BEGIN -- PROCESS
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 -- count_enable <= '0';
172 -- shift_time_enable <= '0';
173 -- shift_data_enable <= '0';
174 -- data_in_ack <= (OTHERS => '0');
175 -- data_out_wen <= (OTHERS => '1');
176 -- sel_ack <= '0';
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 -- IF run = '0' OR no_sel = '1' THEN
179 -- count_enable <= '0';
180 -- shift_time_enable <= '0';
181 -- shift_data_enable <= '0';
182 -- data_in_ack <= (OTHERS => '0');
183 -- data_out_wen <= (OTHERS => '1');
184 -- sel_ack <= '0';
185 -- ELSE
186 -- --COUNT
187 -- IF shift_data_s = "10" THEN
188 -- count_enable <= '1';
189 -- ELSE
190 -- count_enable <= '0';
191 -- END IF;
192 -- --DATA
193 -- IF shift_time_s = "10" THEN
194 -- shift_data_enable <= '1';
195 -- ELSE
196 -- shift_data_enable <= '0';
197 -- END IF;
198
199 -- --TIME
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 -- shift_time_s = "00" OR
202 -- shift_time_s = "01"
203 -- THEN
204 -- shift_time_enable <= '1';
205 -- ELSE
206 -- shift_time_enable <= '0';
207 -- END IF;
208
209 -- --ACK
210 -- IF shift_data_s = "10" THEN
211 -- data_in_ack <= sel;
212 -- sel_ack <= '1';
213 -- ELSE
214 -- data_in_ack <= (OTHERS => '0');
215 -- sel_ack <= '0';
216 -- END IF;
217
218 -- --VALID OUT
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 -- data_out_wen(I) <= '0';
222 -- ELSE
223 -- data_out_wen(I) <= '1';
224 -- END IF;
225 -- END LOOP all_wen;
226
227 -- END IF;
228 -- END IF;
229 --END PROCESS;
230
159
231 -----------------------------------------------------------------------------
160 -----------------------------------------------------------------------------
232 -- DATA MUX
161 -- DATA MUX
233 -----------------------------------------------------------------------------
162 -----------------------------------------------------------------------------
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
235 I_time_in: IF I < 48 GENERATE
236 data_0_v(I) <= time_in(0,I);
237 data_1_v(I) <= time_in(1,I);
238 data_2_v(I) <= time_in(2,I);
239 data_3_v(I) <= time_in(3,I);
240 END GENERATE I_time_in;
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
242 data_0_v(I) <= '0';
243 data_1_v(I) <= '0';
244 data_2_v(I) <= '0';
245 data_3_v(I) <= '0';
246 END GENERATE I_null;
247 I_data_in: IF I > 32*2-1 GENERATE
248 data_0_v(I) <= data_in(0,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
252 END GENERATE I_data_in;
253 END GENERATE all_bit_data_in;
254
163
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
164 all_word: FOR J IN 2 DOWNTO 0 GENERATE
256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
165 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
257 data_0(J)(I) <= data_0_v(J*32+I);
166 data_0(J)(I) <= data_in(0,I+32*J);
258 data_1(J)(I) <= data_1_v(J*32+I);
167 data_1(J)(I) <= data_in(1,I+32*J);
259 data_2(J)(I) <= data_2_v(J*32+I);
168 data_2(J)(I) <= data_in(2,I+32*J);
260 data_3(J)(I) <= data_3_v(J*32+I);
169 data_3(J)(I) <= data_in(3,I+32*J);
261 END GENERATE all_data_bit;
170 END GENERATE all_data_bit;
262 END GENERATE all_word;
171 END GENERATE all_word;
263
172
264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
173 data_sel <= data_0 WHEN sel(0) = '1' ELSE
265 data_1 WHEN sel(1) = '1' ELSE
174 data_1 WHEN sel(1) = '1' ELSE
266 data_2 WHEN sel(2) = '1' ELSE
175 data_2 WHEN sel(2) = '1' ELSE
267 data_3;
176 data_3;
268
177
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
178 all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
179 time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
180 time_in(1,I) WHEN sel(1) = '1' ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
181 time_in(2,I) WHEN sel(2) = '1' ELSE
273 -- data_sel(4);
182 time_in(3,I);
183 END GENERATE all_time_bit;
274
184
275
185
276 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
277 -- RR and SELECTION
187 -- RR and SELECTION
278 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
189 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
190 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
282 END GENERATE all_input_rr;
191 END GENERATE all_input_rr;
283
192
284 RR_Arbiter_4_1 : RR_Arbiter_4
193 RR_Arbiter_4_1 : RR_Arbiter_4
285 PORT MAP (
194 PORT MAP (
286 clk => clk,
195 clk => clk,
287 rstn => rstn,
196 rstn => rstn,
288 in_valid => valid_in_rr,
197 in_valid => valid_in_rr,
289 out_grant => sel_s); --sel_s);
198 out_grant => sel_s);
290
291 -- sel <= sel_s;
292
199
293 PROCESS (clk, rstn)
200 PROCESS (clk, rstn)
294 BEGIN -- PROCESS
201 BEGIN -- PROCESS
295 IF rstn = '0' THEN -- asynchronous reset (active low)
202 IF rstn = '0' THEN -- asynchronous reset (active low)
296 sel <= "0000";
203 sel <= "0000";
297 sel_reg <= '0';
204 sel_reg <= '0';
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
205 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 -- sel_reg
206 IF sel_reg = '0' OR sel_ack = '1' THEN
300 -- sel_ack
301 -- sel_s
302 -- sel = "0000 "
303 --sel <= sel_s;
304 IF sel_reg = '0' OR sel_ack = '1'
305 --OR shift_data_s = "10"
306 THEN
307 sel <= sel_s;
207 sel <= sel_s;
308 IF sel_s = "0000" THEN
208 IF sel_s = "0000" THEN
309 sel_reg <= '0';
209 sel_reg <= '0';
310 ELSE
210 ELSE
311 sel_reg <= '1';
211 sel_reg <= '1';
312 END IF;
212 END IF;
313 END IF;
213 END IF;
314 END IF;
214 END IF;
315 END PROCESS;
215 END PROCESS;
316
216
317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
217 no_sel <= '1' WHEN sel = "0000" ELSE '0';
318
218
319 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
320 -- REG
220 -- REG
321 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
322 reg_count_i: lpp_waveform_fifo_arbiter_reg
222 reg_count_i: lpp_waveform_fifo_arbiter_reg
323 GENERIC MAP (
223 GENERIC MAP (
324 data_size => nb_data_by_buffer_size,
224 data_size => nb_data_by_buffer_size,
325 data_nb => 4)
225 data_nb => 4)
326 PORT MAP (
226 PORT MAP (
327 clk => clk,
227 clk => clk,
328 rstn => rstn,
228 rstn => rstn,
329 run => run,
229 run => run,
330 max_count => nb_data_by_buffer,
230 max_count => nb_data_by_buffer,
331 enable => count_enable,
231 enable => count_enable,
332 sel => sel,
232 sel => sel,
333 data => count,
233 data => count,
334 data_s => count_s);
234 data_s => count_s);
335
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
337 -- GENERIC MAP (
338 -- data_size => 2,
339 -- data_nb => 4)
340 -- PORT MAP (
341 -- clk => clk,
342 -- rstn => rstn,
343 -- run => run,
344 -- max_count => "10", -- 2
345 -- enable => shift_data_enable,
346 -- sel => sel,
347 -- data => shift_data,
348 -- data_s => shift_data_s);
349
350
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
352 -- GENERIC MAP (
353 -- data_size => 2,
354 -- data_nb => 4)
355 -- PORT MAP (
356 -- clk => clk,
357 -- rstn => rstn,
358 -- run => run,
359 -- max_count => "10", -- 2
360 -- enable => shift_time_enable,
361 -- sel => sel,
362 -- data => shift_time,
363 -- data_s => shift_time_s);
364
235
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367
238
368 END ARCHITECTURE;
239 END ARCHITECTURE;
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Show file before | Show file after | Hide comments
@@ -1,402 +1,392
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
25
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31
31
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
36
36
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40
40
41 -----------------------------------------------------------------------------
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
43 -----------------------------------------------------------------------------
44
44
45 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER;
47 data_size : INTEGER;
48 nb_snapshot_param_size : INTEGER);
48 nb_snapshot_param_size : INTEGER);
49 PORT (
49 PORT (
50 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 run : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 start_snapshot : IN STD_LOGIC;
56 start_snapshot : IN STD_LOGIC;
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 data_in_valid : IN STD_LOGIC;
58 data_in_valid : IN STD_LOGIC;
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 data_out_valid : OUT STD_LOGIC);
60 data_out_valid : OUT STD_LOGIC);
61 END COMPONENT;
61 END COMPONENT;
62
62
63 COMPONENT lpp_waveform_burst
63 COMPONENT lpp_waveform_burst
64 GENERIC (
64 GENERIC (
65 data_size : INTEGER);
65 data_size : INTEGER);
66 PORT (
66 PORT (
67 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 run : IN STD_LOGIC;
69 run : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 data_out_valid : OUT STD_LOGIC);
74 data_out_valid : OUT STD_LOGIC);
75 END COMPONENT;
75 END COMPONENT;
76
76
77 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
78 GENERIC (
78 GENERIC (
79 delta_vector_size : INTEGER;
79 delta_vector_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
80 delta_vector_size_f0_2 : INTEGER);
81 PORT (
81 PORT (
82 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 data_f0_valid : IN STD_LOGIC;
92 data_f0_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
97 wfp_on : OUT STD_LOGIC);
98 END COMPONENT;
98 END COMPONENT;
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 --
101 --
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
104 GENERIC (
104 GENERIC (
105 tech : INTEGER;
105 tech : INTEGER;
106 data_size : INTEGER;
106 data_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
110 delta_vector_size : INTEGER;
109 delta_vector_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER);
110 delta_vector_size_f0_2 : INTEGER);
112 PORT (
111 PORT (
113 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
113 rstn : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
114 reg_run : IN STD_LOGIC;
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
115 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
118 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 enable_f0 : IN STD_LOGIC;
121 enable_f0 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
122 enable_f1 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
123 enable_f2 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
124 enable_f3 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
125 burst_f0 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
126 burst_f1 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
127 burst_f2 : IN STD_LOGIC;
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
128 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
129 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
130 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
131 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
133 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
134 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
139 data_f0_in_valid : IN STD_LOGIC;
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 data_f1_in_valid : IN STD_LOGIC;
141 data_f1_in_valid : IN STD_LOGIC;
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 data_f2_in_valid : IN STD_LOGIC;
143 data_f2_in_valid : IN STD_LOGIC;
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 data_f3_in_valid : IN STD_LOGIC;
145 data_f3_in_valid : IN STD_LOGIC;
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_f0_data_out_valid : OUT STD_LOGIC;
149 data_f0_data_out_valid : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
150 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
151 data_f0_data_out_ren : IN STD_LOGIC;
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_valid : OUT STD_LOGIC;
154 data_f1_data_out_valid : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
155 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
156 data_f1_data_out_ren : IN STD_LOGIC;
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
158 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f2_data_out_valid : OUT STD_LOGIC;
159 data_f2_data_out_valid : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
160 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
161 data_f2_data_out_ren : IN STD_LOGIC;
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_f3_data_out_valid : OUT STD_LOGIC;
164 data_f3_data_out_valid : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
165 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
166 data_f3_data_out_ren : IN STD_LOGIC;
170
167
171 --debug
168 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
172 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
169 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
173 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
174 --debug_f0_data_valid : OUT STD_LOGIC;
171 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
175 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
176 --debug_f1_data_valid : OUT STD_LOGIC;
173 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
177 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
178 --debug_f2_data_valid : OUT STD_LOGIC;
175 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
179 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
180 --debug_f3_data_valid : OUT STD_LOGIC;
181
182 ----debug FIFO IN
183 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
185 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
187 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
189 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
191 );
176 );
192 END COMPONENT;
177 END COMPONENT;
193
178
194 COMPONENT lpp_waveform_dma_genvalid
179 COMPONENT lpp_waveform_dma_genvalid
195 PORT (
180 PORT (
196 HCLK : IN STD_LOGIC;
181 HCLK : IN STD_LOGIC;
197 HRESETn : IN STD_LOGIC;
182 HRESETn : IN STD_LOGIC;
198 run : IN STD_LOGIC;
183 run : IN STD_LOGIC;
199 valid_in : IN STD_LOGIC;
184 valid_in : IN STD_LOGIC;
200 ack_in : IN STD_LOGIC;
185 ack_in : IN STD_LOGIC;
201 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
186 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
202 valid_out : OUT STD_LOGIC;
187 valid_out : OUT STD_LOGIC;
203 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
204 error : OUT STD_LOGIC);
189 error : OUT STD_LOGIC);
205 END COMPONENT;
190 END COMPONENT;
206
191
207 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
208 -- FIFO
193 -- FIFO
209 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
210 COMPONENT lpp_waveform_fifo_ctrl
195 COMPONENT lpp_waveform_fifo_ctrl
211 GENERIC (
196 GENERIC (
212 offset : INTEGER;
197 offset : INTEGER;
213 length : INTEGER);
198 length : INTEGER);
214 PORT (
199 PORT (
215 clk : IN STD_LOGIC;
200 clk : IN STD_LOGIC;
216 rstn : IN STD_LOGIC;
201 rstn : IN STD_LOGIC;
217 run : IN STD_LOGIC;
202 run : IN STD_LOGIC;
218 ren : IN STD_LOGIC;
203 ren : IN STD_LOGIC;
219 wen : IN STD_LOGIC;
204 wen : IN STD_LOGIC;
220 mem_re : OUT STD_LOGIC;
205 mem_re : OUT STD_LOGIC;
221 mem_we : OUT STD_LOGIC;
206 mem_we : OUT STD_LOGIC;
222 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
207 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
223 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
208 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
224 empty_almost : OUT STD_LOGIC;
209 empty_almost : OUT STD_LOGIC;
225 empty : OUT STD_LOGIC;
210 empty : OUT STD_LOGIC;
226 full_almost : OUT STD_LOGIC;
211 full_almost : OUT STD_LOGIC;
227 full : OUT STD_LOGIC);
212 full : OUT STD_LOGIC);
228 END COMPONENT;
213 END COMPONENT;
229
214
230 COMPONENT lpp_waveform_fifo_arbiter
215 COMPONENT lpp_waveform_fifo_arbiter
231 GENERIC (
216 GENERIC (
232 tech : INTEGER;
217 tech : INTEGER;
233 nb_data_by_buffer_size : INTEGER);
218 nb_data_by_buffer_size : INTEGER);
234 PORT (
219 PORT (
235 clk : IN STD_LOGIC;
220 clk : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
221 rstn : IN STD_LOGIC;
237 run : IN STD_LOGIC;
222 run : IN STD_LOGIC;
238 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
223 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
239 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
224 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
225 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
226 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
242 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
227 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
243 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
228 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
244 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
229 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
230 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
231 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
232 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
233 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
234 );
247 END COMPONENT;
235 END COMPONENT;
248
236
249 COMPONENT lpp_waveform_fifo
237 COMPONENT lpp_waveform_fifo
250 GENERIC (
238 GENERIC (
251 tech : INTEGER);
239 tech : INTEGER);
252 PORT (
240 PORT (
253 clk : IN STD_LOGIC;
241 clk : IN STD_LOGIC;
254 rstn : IN STD_LOGIC;
242 rstn : IN STD_LOGIC;
255 run : IN STD_LOGIC;
243 run : IN STD_LOGIC;
256 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
244 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
257 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
258 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
247 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
260 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
248 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
250 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
263 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
264 END COMPONENT;
252 END COMPONENT;
265
253
266 COMPONENT lpp_waveform_fifo_headreg
254 COMPONENT lpp_waveform_fifo_headreg
267 GENERIC (
255 GENERIC (
268 tech : INTEGER);
256 tech : INTEGER);
269 PORT (
257 PORT (
270 clk : IN STD_LOGIC;
258 clk : IN STD_LOGIC;
271 rstn : IN STD_LOGIC;
259 rstn : IN STD_LOGIC;
272 run : IN STD_LOGIC;
260 run : IN STD_LOGIC;
273 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
274 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
275 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
263 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
276 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
264 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
278 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
266 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
279 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
267 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
280 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
268 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
269 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
282 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
270 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
283 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
271 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
284 END COMPONENT;
272 END COMPONENT;
285
273
286 COMPONENT lpp_waveform_fifo_latencyCorrection
274 COMPONENT lpp_waveform_fifo_latencyCorrection
287 GENERIC (
275 GENERIC (
288 tech : INTEGER);
276 tech : INTEGER);
289 PORT (
277 PORT (
290 clk : IN STD_LOGIC;
278 clk : IN STD_LOGIC;
291 rstn : IN STD_LOGIC;
279 rstn : IN STD_LOGIC;
292 run : IN STD_LOGIC;
280 run : IN STD_LOGIC;
293 empty_almost : OUT STD_LOGIC;
281 empty_almost : OUT STD_LOGIC;
294 empty : OUT STD_LOGIC;
282 empty : OUT STD_LOGIC;
295 data_ren : IN STD_LOGIC;
283 data_ren : IN STD_LOGIC;
296 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
297 empty_almost_fifo : IN STD_LOGIC;
285 empty_almost_fifo : IN STD_LOGIC;
298 empty_fifo : IN STD_LOGIC;
286 empty_fifo : IN STD_LOGIC;
299 data_ren_fifo : OUT STD_LOGIC;
287 data_ren_fifo : OUT STD_LOGIC;
300 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
288 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
301 END COMPONENT;
289 END COMPONENT;
302
290
303 COMPONENT lpp_waveform_fifo_withoutLatency
291 COMPONENT lpp_waveform_fifo_withoutLatency
304 GENERIC (
292 GENERIC (
305 tech : INTEGER);
293 tech : INTEGER);
306 PORT (
294 PORT (
307 clk : IN STD_LOGIC;
295 clk : IN STD_LOGIC;
308 rstn : IN STD_LOGIC;
296 rstn : IN STD_LOGIC;
309 run : IN STD_LOGIC;
297 run : IN STD_LOGIC;
310 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
298 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
311 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
299 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
312 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
300 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
313 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
301 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
302 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
303 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
316 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
304 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
317 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
305 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
318 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
306 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
319 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
307 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
308 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
321 END COMPONENT;
309 END COMPONENT;
322
310
323 -----------------------------------------------------------------------------
311 -----------------------------------------------------------------------------
324 -- GEN ADDRESS
312 -- GEN ADDRESS
325 -----------------------------------------------------------------------------
313 -----------------------------------------------------------------------------
326 COMPONENT lpp_waveform_genaddress
314 COMPONENT lpp_waveform_genaddress
327 GENERIC (
315 GENERIC (
328 nb_data_by_buffer_size : INTEGER);
316 nb_data_by_buffer_size : INTEGER);
329 PORT (
317 PORT (
330 clk : IN STD_LOGIC;
318 clk : IN STD_LOGIC;
331 rstn : IN STD_LOGIC;
319 rstn : IN STD_LOGIC;
332 run : IN STD_LOGIC;
320 run : IN STD_LOGIC;
333 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
321 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
334 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
322 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
335 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
323 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
336 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
324 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
337 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
325 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
338 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
326 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
340 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
341 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
342 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
343 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
331 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
344 data_f0_data_out_valid_burst : OUT STD_LOGIC;
332 data_f0_data_out_valid_burst : OUT STD_LOGIC;
345 data_f1_data_out_valid_burst : OUT STD_LOGIC;
333 data_f1_data_out_valid_burst : OUT STD_LOGIC;
346 data_f2_data_out_valid_burst : OUT STD_LOGIC;
334 data_f2_data_out_valid_burst : OUT STD_LOGIC;
347 data_f3_data_out_valid_burst : OUT STD_LOGIC;
335 data_f3_data_out_valid_burst : OUT STD_LOGIC;
348 data_f0_data_out_valid : OUT STD_LOGIC;
336 data_f0_data_out_valid : OUT STD_LOGIC;
349 data_f1_data_out_valid : OUT STD_LOGIC;
337 data_f1_data_out_valid : OUT STD_LOGIC;
350 data_f2_data_out_valid : OUT STD_LOGIC;
338 data_f2_data_out_valid : OUT STD_LOGIC;
351 data_f3_data_out_valid : OUT STD_LOGIC;
339 data_f3_data_out_valid : OUT STD_LOGIC;
352 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
340 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
341 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
342 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
343 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
356 END COMPONENT;
344 END COMPONENT;
357
345
358 -----------------------------------------------------------------------------
346 -----------------------------------------------------------------------------
359 -- lpp_waveform_fifo_arbiter_reg
347 -- lpp_waveform_fifo_arbiter_reg
360 -----------------------------------------------------------------------------
348 -----------------------------------------------------------------------------
361 COMPONENT lpp_waveform_fifo_arbiter_reg
349 COMPONENT lpp_waveform_fifo_arbiter_reg
362 GENERIC (
350 GENERIC (
363 data_size : INTEGER;
351 data_size : INTEGER;
364 data_nb : INTEGER);
352 data_nb : INTEGER);
365 PORT (
353 PORT (
366 clk : IN STD_LOGIC;
354 clk : IN STD_LOGIC;
367 rstn : IN STD_LOGIC;
355 rstn : IN STD_LOGIC;
368 run : IN STD_LOGIC;
356 run : IN STD_LOGIC;
369 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
357 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
370 enable : IN STD_LOGIC;
358 enable : IN STD_LOGIC;
371 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
359 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
372 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
360 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
373 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
361 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
362 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
363 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
374 END COMPONENT;
364 END COMPONENT;
375
365
376 COMPONENT lpp_waveform_fsmdma
366 COMPONENT lpp_waveform_fsmdma
377 PORT (
367 PORT (
378 clk : IN STD_ULOGIC;
368 clk : IN STD_ULOGIC;
379 rstn : IN STD_ULOGIC;
369 rstn : IN STD_ULOGIC;
380 run : IN STD_LOGIC;
370 run : IN STD_LOGIC;
381 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
371 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
382 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
372 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
383 fifo_empty : IN STD_LOGIC;
373 fifo_empty : IN STD_LOGIC;
384 fifo_empty_threshold : IN STD_LOGIC;
374 fifo_empty_threshold : IN STD_LOGIC;
385 fifo_ren : OUT STD_LOGIC;
375 fifo_ren : OUT STD_LOGIC;
386 dma_fifo_valid_burst : OUT STD_LOGIC;
376 dma_fifo_valid_burst : OUT STD_LOGIC;
387 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
377 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
388 dma_fifo_ren : IN STD_LOGIC;
378 dma_fifo_ren : IN STD_LOGIC;
389 dma_buffer_new : OUT STD_LOGIC;
379 dma_buffer_new : OUT STD_LOGIC;
390 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
380 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
391 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
381 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
392 dma_buffer_full : IN STD_LOGIC;
382 dma_buffer_full : IN STD_LOGIC;
393 dma_buffer_full_err : IN STD_LOGIC;
383 dma_buffer_full_err : IN STD_LOGIC;
394 status_buffer_ready : IN STD_LOGIC;
384 status_buffer_ready : IN STD_LOGIC;
395 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
385 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
396 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
386 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
397 ready_buffer : OUT STD_LOGIC;
387 ready_buffer : OUT STD_LOGIC;
398 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
388 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
399 error_buffer_full : OUT STD_LOGIC);
389 error_buffer_full : OUT STD_LOGIC);
400 END COMPONENT;
390 END COMPONENT;
401
391
402 END lpp_waveform_pkg;
392 END lpp_waveform_pkg;
Show file before | Show file after | Hide comments
@@ -1,14 +1,15
1 lpp_waveform_pkg.vhd
1 lpp_waveform_pkg.vhd
2 lpp_waveform.vhd
2 lpp_waveform.vhd
3 lpp_waveform_burst.vhd
3 lpp_waveform_burst.vhd
4 lpp_waveform_fifo_withoutLatency.vhd
4 lpp_waveform_fifo_withoutLatency.vhd
5 lpp_waveform_fifo_latencyCorrection.vhd
5 lpp_waveform_fifo_latencyCorrection.vhd
6 lpp_waveform_fifo.vhd
6 lpp_waveform_fifo.vhd
7 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_arbiter.vhd
8 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo_ctrl.vhd
9 lpp_waveform_fifo_headreg.vhd
9 lpp_waveform_fifo_headreg.vhd
10 lpp_waveform_snapshot.vhd
10 lpp_waveform_snapshot.vhd
11 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot_controler.vhd
12 lpp_waveform_genaddress.vhd
12 lpp_waveform_genaddress.vhd
13 lpp_waveform_dma_genvalid.vhd
13 lpp_waveform_dma_genvalid.vhd
14 lpp_waveform_fifo_arbiter_reg.vhd
14 lpp_waveform_fifo_arbiter_reg.vhd
15 lpp_waveform_fsmdma.vhd
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