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modif 1 : echange des ahbslave 0 (srctrle-0ws) et slave 2 (DSU)...
pellion -
r572:049317d554b2 JC
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@@ -1,124 +1,124
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
4
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
77
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
105
106 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -1,569 +1,572
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 0;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
77 SRBANKSZ : INTEGER := 8
78
78
79 );
79 );
80 PORT (
80 PORT (
81 clk : IN STD_ULOGIC;
81 clk : IN STD_ULOGIC;
82 reset : IN STD_ULOGIC;
82 reset : IN STD_ULOGIC;
83
83
84 errorn : OUT STD_ULOGIC;
84 errorn : OUT STD_ULOGIC;
85
85
86 -- UART AHB ---------------------------------------------------------------
86 -- UART AHB ---------------------------------------------------------------
87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89
89
90 -- UART APB ---------------------------------------------------------------
90 -- UART APB ---------------------------------------------------------------
91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93
93
94 -- RAM --------------------------------------------------------------------
94 -- RAM --------------------------------------------------------------------
95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 nSRAM_BE0 : OUT STD_LOGIC;
97 nSRAM_BE0 : OUT STD_LOGIC;
98 nSRAM_BE1 : OUT STD_LOGIC;
98 nSRAM_BE1 : OUT STD_LOGIC;
99 nSRAM_BE2 : OUT STD_LOGIC;
99 nSRAM_BE2 : OUT STD_LOGIC;
100 nSRAM_BE3 : OUT STD_LOGIC;
100 nSRAM_BE3 : OUT STD_LOGIC;
101 nSRAM_WE : OUT STD_LOGIC;
101 nSRAM_WE : OUT STD_LOGIC;
102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 nSRAM_OE : OUT STD_LOGIC;
103 nSRAM_OE : OUT STD_LOGIC;
104 nSRAM_READY : IN STD_LOGIC;
104 nSRAM_READY : IN STD_LOGIC;
105 SRAM_MBE : INOUT STD_LOGIC;
105 SRAM_MBE : INOUT STD_LOGIC;
106 -- APB --------------------------------------------------------------------
106 -- APB --------------------------------------------------------------------
107 apbi_ext : OUT apb_slv_in_type;
107 apbi_ext : OUT apb_slv_in_type;
108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 -- AHB_Slave --------------------------------------------------------------
109 -- AHB_Slave --------------------------------------------------------------
110 ahbi_s_ext : OUT ahb_slv_in_type;
110 ahbi_s_ext : OUT ahb_slv_in_type;
111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 -- AHB_Master -------------------------------------------------------------
112 -- AHB_Master -------------------------------------------------------------
113 ahbi_m_ext : OUT AHB_Mst_In_Type;
113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115
115
116 );
116 );
117 END;
117 END;
118
118
119 ARCHITECTURE Behavioral OF leon3_soc IS
119 ARCHITECTURE Behavioral OF leon3_soc IS
120
120
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 -- CONFIG -------------------------------------------------------------------
122 -- CONFIG -------------------------------------------------------------------
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
124
125 -- Clock generator
125 -- Clock generator
126 CONSTANT CFG_CLKMUL : INTEGER := (1);
126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 -- LEON3 processor core
130 -- LEON3 processor core
131 CONSTANT CFG_LEON3 : INTEGER := 1;
131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 CONSTANT CFG_V8 : INTEGER := 0;
134 CONSTANT CFG_V8 : INTEGER := 0;
135 CONSTANT CFG_MAC : INTEGER := 0;
135 CONSTANT CFG_MAC : INTEGER := 0;
136 CONSTANT CFG_SVT : INTEGER := 0;
136 CONSTANT CFG_SVT : INTEGER := 0;
137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 CONSTANT CFG_LDDEL : INTEGER := (1);
138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 CONSTANT CFG_NWP : INTEGER := (0);
139 CONSTANT CFG_NWP : INTEGER := (0);
140 CONSTANT CFG_PWD : INTEGER := 1*2;
140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 -- 1*(8 + 16 * 0) => grfpu-light
142 -- 1*(8 + 16 * 0) => grfpu-light
143 -- 1*(8 + 16 * 1) => netlist
143 -- 1*(8 + 16 * 1) => netlist
144 -- 0*(8 + 16 * 0) => No FPU
144 -- 0*(8 + 16 * 0) => No FPU
145 -- 0*(8 + 16 * 1) => No FPU;
145 -- 0*(8 + 16 * 1) => No FPU;
146 CONSTANT CFG_ICEN : INTEGER := 1;
146 CONSTANT CFG_ICEN : INTEGER := 1;
147 CONSTANT CFG_ISETS : INTEGER := 1;
147 CONSTANT CFG_ISETS : INTEGER := 1;
148 CONSTANT CFG_ISETSZ : INTEGER := 4;
148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 CONSTANT CFG_ILINE : INTEGER := 4;
149 CONSTANT CFG_ILINE : INTEGER := 4;
150 CONSTANT CFG_IREPL : INTEGER := 0;
150 CONSTANT CFG_IREPL : INTEGER := 0;
151 CONSTANT CFG_ILOCK : INTEGER := 0;
151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 CONSTANT CFG_DCEN : INTEGER := 1;
155 CONSTANT CFG_DCEN : INTEGER := 1;
156 CONSTANT CFG_DSETS : INTEGER := 1;
156 CONSTANT CFG_DSETS : INTEGER := 1;
157 CONSTANT CFG_DSETSZ : INTEGER := 4;
157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 CONSTANT CFG_DLINE : INTEGER := 4;
158 CONSTANT CFG_DLINE : INTEGER := 4;
159 CONSTANT CFG_DREPL : INTEGER := 0;
159 CONSTANT CFG_DREPL : INTEGER := 0;
160 CONSTANT CFG_DLOCK : INTEGER := 0;
160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 CONSTANT CFG_MMUEN : INTEGER := 0;
165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 CONSTANT CFG_TLB_REP : INTEGER := 1;
169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170
170
171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 CONSTANT CFG_ITBSZ : INTEGER := 0;
172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 CONSTANT CFG_ATBSZ : INTEGER := 0;
173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174
174
175 -- AMBA settings
175 -- AMBA settings
176 CONSTANT CFG_DEFMST : INTEGER := (0);
176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 CONSTANT CFG_RROBIN : INTEGER := 1;
177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 CONSTANT CFG_SPLIT : INTEGER := 0;
178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181
181
182 -- DSU UART
182 -- DSU UART
183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184
184
185 -- LEON2 memory controller
185 -- LEON2 memory controller
186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187
187
188 -- UART 1
188 -- UART 1
189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191
191
192 -- LEON3 interrupt controller
192 -- LEON3 interrupt controller
193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194
194
195 -- Modular timer
195 -- Modular timer
196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 CONSTANT CFG_GPT_SW : INTEGER := (8);
198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 CONSTANT CFG_GPT_TW : INTEGER := (32);
199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 -- SIGNALs
207 -- SIGNALs
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 -- CLK & RST --
210 -- CLK & RST --
211 SIGNAL clk2x : STD_ULOGIC;
211 SIGNAL clk2x : STD_ULOGIC;
212 SIGNAL clkmn : STD_ULOGIC;
212 SIGNAL clkmn : STD_ULOGIC;
213 SIGNAL clkm : STD_ULOGIC;
213 SIGNAL clkm : STD_ULOGIC;
214 SIGNAL rstn : STD_ULOGIC;
214 SIGNAL rstn : STD_ULOGIC;
215 SIGNAL rstraw : STD_ULOGIC;
215 SIGNAL rstraw : STD_ULOGIC;
216 SIGNAL pciclk : STD_ULOGIC;
216 SIGNAL pciclk : STD_ULOGIC;
217 SIGNAL sdclkl : STD_ULOGIC;
217 SIGNAL sdclkl : STD_ULOGIC;
218 SIGNAL cgi : clkgen_in_type;
218 SIGNAL cgi : clkgen_in_type;
219 SIGNAL cgo : clkgen_out_type;
219 SIGNAL cgo : clkgen_out_type;
220 --- AHB / APB
220 --- AHB / APB
221 SIGNAL apbi : apb_slv_in_type;
221 SIGNAL apbi : apb_slv_in_type;
222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 SIGNAL ahbsi : ahb_slv_in_type;
223 SIGNAL ahbsi : ahb_slv_in_type;
224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 SIGNAL ahbmi : ahb_mst_in_type;
225 SIGNAL ahbmi : ahb_mst_in_type;
226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 --UART
227 --UART
228 SIGNAL ahbuarti : uart_in_type;
228 SIGNAL ahbuarti : uart_in_type;
229 SIGNAL ahbuarto : uart_out_type;
229 SIGNAL ahbuarto : uart_out_type;
230 SIGNAL apbuarti : uart_in_type;
230 SIGNAL apbuarti : uart_in_type;
231 SIGNAL apbuarto : uart_out_type;
231 SIGNAL apbuarto : uart_out_type;
232 --MEM CTRLR
232 --MEM CTRLR
233 SIGNAL memi : memory_in_type;
233 SIGNAL memi : memory_in_type;
234 SIGNAL memo : memory_out_type;
234 SIGNAL memo : memory_out_type;
235 SIGNAL wpo : wprot_out_type;
235 SIGNAL wpo : wprot_out_type;
236 SIGNAL sdo : sdram_out_type;
236 SIGNAL sdo : sdram_out_type;
237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 SIGNAL nSRAM_OE_s : STD_LOGIC;
240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 --IRQ
241 --IRQ
242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 --Timer
244 --Timer
245 SIGNAL gpti : gptimer_in_type;
245 SIGNAL gpti : gptimer_in_type;
246 SIGNAL gpto : gptimer_out_type;
246 SIGNAL gpto : gptimer_out_type;
247 --DSU
247 --DSU
248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 SIGNAL dsui : dsu_in_type;
250 SIGNAL dsui : dsu_in_type;
251 SIGNAL dsuo : dsu_out_type;
251 SIGNAL dsuo : dsu_out_type;
252 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
253
253
254
254
255 BEGIN
255 BEGIN
256
256
257
257
258 ----------------------------------------------------------------------
258 ----------------------------------------------------------------------
259 --- Reset and Clock generation -------------------------------------
259 --- Reset and Clock generation -------------------------------------
260 ----------------------------------------------------------------------
260 ----------------------------------------------------------------------
261
261
262 cgi.pllctrl <= "00";
262 cgi.pllctrl <= "00";
263 cgi.pllrst <= rstraw;
263 cgi.pllrst <= rstraw;
264
264
265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266
266
267 clkgen0 : clkgen -- clock generator
267 clkgen0 : clkgen -- clock generator
268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271
271
272 ----------------------------------------------------------------------
272 ----------------------------------------------------------------------
273 --- LEON3 processor / DSU / IRQ ------------------------------------
273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 ----------------------------------------------------------------------
274 ----------------------------------------------------------------------
275
275
276 l3 : IF CFG_LEON3 = 1 GENERATE
276 l3 : IF CFG_LEON3 = 1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 irqi(i), irqo(i), dbgi(i), dbgo(i));
287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 END GENERATE leon3_non_radhard;
288 END GENERATE leon3_non_radhard;
289
289
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 cpu : ENTITY gaisler.leon3ft
291 cpu : ENTITY gaisler.leon3ft
292 GENERIC MAP (
292 GENERIC MAP (
293 HINDEX => i, --: integer; --CPU_HINDEX,
293 HINDEX => i, --: integer; --CPU_HINDEX,
294 FABTECH => fabtech, --CFG_TECH,
294 FABTECH => fabtech, --CFG_TECH,
295 MEMTECH => memtech, --CFG_TECH,
295 MEMTECH => memtech, --CFG_TECH,
296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 FPU => CFG_FPU, --CFG_FPU,
298 FPU => CFG_FPU, --CFG_FPU,
299 V8 => CFG_V8, --CFG_V8,
299 V8 => CFG_V8, --CFG_V8,
300 CP => 0, --CFG_CP,
300 CP => 0, --CFG_CP,
301 MAC => CFG_MAC, --CFG_MAC,
301 MAC => CFG_MAC, --CFG_MAC,
302 PCLOW => pclow, --CFG_PCLOW,
302 PCLOW => pclow, --CFG_PCLOW,
303 NOTAG => 0, --CFG_NOTAG,
303 NOTAG => 0, --CFG_NOTAG,
304 NWP => CFG_NWP, --CFG_NWP,
304 NWP => CFG_NWP, --CFG_NWP,
305 ICEN => CFG_ICEN, --CFG_ICEN,
305 ICEN => CFG_ICEN, --CFG_ICEN,
306 IREPL => CFG_IREPL, --CFG_IREPL,
306 IREPL => CFG_IREPL, --CFG_IREPL,
307 ISETS => CFG_ISETS, --CFG_ISETS,
307 ISETS => CFG_ISETS, --CFG_ISETS,
308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 DCEN => CFG_DCEN, --CFG_DCEN,
311 DCEN => CFG_DCEN, --CFG_DCEN,
312 DREPL => CFG_DREPL, --CFG_DREPL,
312 DREPL => CFG_DREPL, --CFG_DREPL,
313 DSETS => CFG_DSETS, --CFG_DSETS,
313 DSETS => CFG_DSETS, --CFG_DSETS,
314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 PWD => CFG_PWD, --CFG_PWD,
332 PWD => CFG_PWD, --CFG_PWD,
333 SVT => CFG_SVT, --CFG_SVT,
333 SVT => CFG_SVT, --CFG_SVT,
334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 CACHED => 0, --: integer; --CFG_DFIXED,
341 CACHED => 0, --: integer; --CFG_DFIXED,
342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 BP => 1) --CFG_BP
345 BP => 1) --CFG_BP
346 PORT MAP ( --
346 PORT MAP ( --
347 rstn => rstn, --rst_n,
347 rstn => rstn, --rst_n,
348 clk => clkm, --clk,
348 clk => clkm, --clk,
349 ahbi => ahbmi, --ahbmi,
349 ahbi => ahbmi, --ahbmi,
350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 ahbsi => ahbsi, --ahbsi,
351 ahbsi => ahbsi, --ahbsi,
352 ahbso => ahbso, --ahbso,
352 ahbso => ahbso, --ahbso,
353 irqi => irqi(i), --irqi(CPU_HINDEX),
353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 irqo => irqo(i), --irqo(CPU_HINDEX),
354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 gclk => clkm --clk
357 gclk => clkm --clk
358 );
358 );
359 END GENERATE leon3_radhard_i;
359 END GENERATE leon3_radhard_i;
360
360
361 END GENERATE;
361 END GENERATE;
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363
363
364 dsugen : IF CFG_DSU = 1 GENERATE
364 dsugen : IF CFG_DSU = 1 GENERATE
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
367 haddr => 16#900#, hmask => 16#F00#,
368 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 irq => 0, kbytes => CFG_ATBSZ)
370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 dbgo, dbgi, dsui, dsuo);
369 dsui.enable <= '1';
372 dsui.enable <= '1';
370 dsui.break <= '0';
373 dsui.break <= '0';
371 END GENERATE;
374 END GENERATE;
372 END GENERATE;
375 END GENERATE;
373
376
374 nodsu : IF CFG_DSU = 0 GENERATE
377 nodsu : IF CFG_DSU = 0 GENERATE
375 ahbso(2) <= ahbs_none;
378 ahbso(2) <= ahbs_none;
376 dsuo.tstop <= '0';
379 dsuo.tstop <= '0';
377 dsuo.active <= '0';
380 dsuo.active <= '0';
378 END GENERATE;
381 END GENERATE;
379
382
380 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
383 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
381 irqctrl0 : irqmp -- interrupt controller
384 irqctrl0 : irqmp -- interrupt controller
382 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
385 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
383 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
386 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
384 END GENERATE;
387 END GENERATE;
385 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
388 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
386 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
389 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
387 irqi(i).irl <= "0000";
390 irqi(i).irl <= "0000";
388 END GENERATE;
391 END GENERATE;
389 apbo(2) <= apb_none;
392 apbo(2) <= apb_none;
390 END GENERATE;
393 END GENERATE;
391
394
392 ----------------------------------------------------------------------
395 ----------------------------------------------------------------------
393 --- Memory controllers ---------------------------------------------
396 --- Memory controllers ---------------------------------------------
394 ----------------------------------------------------------------------
397 ----------------------------------------------------------------------
395 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
398 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
396 memctrlr : mctrl GENERIC MAP (
399 memctrlr : mctrl GENERIC MAP (
397 hindex => 0,
400 hindex => 0,
398 pindex => 0,
401 pindex => 0,
399 paddr => 0,
402 paddr => 0,
400 srbanks => 1
403 srbanks => 1
401 )
404 )
402 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
405 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
403 memi.bexcn <= '1';
406 memi.bexcn <= '1';
404 memi.brdyn <= '1';
407 memi.brdyn <= '1';
405
408
406 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
409 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
407 nSRAM_OE_s <= memo.ramoen(0);
410 nSRAM_OE_s <= memo.ramoen(0);
408 END GENERATE;
411 END GENERATE;
409
412
410 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
413 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
411 memctrlr : srctrle_0ws
414 memctrlr : srctrle_0ws
412 GENERIC MAP(
415 GENERIC MAP(
413 hindex => 0,
416 hindex => 2, -- TODO : hindex => 0
414 pindex => 0,
417 pindex => 0,
415 paddr => 0,
418 paddr => 0,
416 srbanks => 2,
419 srbanks => 2,
417 banksz => SRBANKSZ, --512k * 32
420 banksz => SRBANKSZ, --512k * 32
418 rmw => 1,
421 rmw => 1,
419 --Aeroflex memory generics:
422 --Aeroflex memory generics:
420 mbpbusy => BYPASS_EDAC_MEMCTRLR,
423 mbpbusy => BYPASS_EDAC_MEMCTRLR,
421 mprog => 1, -- program memory by default values after reset
424 mprog => 1, -- program memory by default values after reset
422 mpsrate => 15, -- default scrub rate period
425 mpsrate => 15, -- default scrub rate period
423 mpb2s => 14, -- default busy to scrub delay
426 mpb2s => 14, -- default busy to scrub delay
424 mpapb => 1, -- instantiate apb register
427 mpapb => 1, -- instantiate apb register
425 mchipcnt => 2,
428 mchipcnt => 2,
426 mpenall => 1 -- when 0 program only E1 chip, else program all dies
429 mpenall => 1 -- when 0 program only E1 chip, else program all dies
427 )
430 )
428 PORT MAP (
431 PORT MAP (
429 rst => rstn,
432 rst => rstn,
430 clk => clkm,
433 clk => clkm,
431 ahbsi => ahbsi,
434 ahbsi => ahbsi,
432 ahbso => ahbso(0),
435 ahbso => ahbso(2), -- TODO :ahbso(0),
433 apbi => apbi,
436 apbi => apbi,
434 apbo => apbo(0),
437 apbo => apbo(0),
435 sri => memi,
438 sri => memi,
436 sro => memo,
439 sro => memo,
437 --Aeroflex memory signals:
440 --Aeroflex memory signals:
438 ucerr => OPEN, -- uncorrectable error signal
441 ucerr => OPEN, -- uncorrectable error signal
439 mbe => mbe, -- enable memory programming
442 mbe => mbe, -- enable memory programming
440 mbe_drive => mbe_drive -- drive the MBE memory signal
443 mbe_drive => mbe_drive -- drive the MBE memory signal
441 );
444 );
442
445
443 memi.brdyn <= nSRAM_READY;
446 memi.brdyn <= nSRAM_READY;
444
447
445 mbe_pad : iopad
448 mbe_pad : iopad
446 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
449 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
447 PORT MAP(pad => SRAM_MBE,
450 PORT MAP(pad => SRAM_MBE,
448 i => mbe,
451 i => mbe,
449 en => mbe_drive,
452 en => mbe_drive,
450 o => memi.bexcn);
453 o => memi.bexcn);
451
454
452 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
455 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
453 nSRAM_OE_s <= memo.oen;
456 nSRAM_OE_s <= memo.oen;
454
457
455 END GENERATE;
458 END GENERATE;
456
459
457
460
458 memi.writen <= '1';
461 memi.writen <= '1';
459 memi.wrn <= "1111";
462 memi.wrn <= "1111";
460 memi.bwidth <= "10";
463 memi.bwidth <= "10";
461
464
462 bdr : FOR i IN 0 TO 3 GENERATE
465 bdr : FOR i IN 0 TO 3 GENERATE
463 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
466 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
464 PORT MAP (
467 PORT MAP (
465 data(31-i*8 DOWNTO 24-i*8),
468 data(31-i*8 DOWNTO 24-i*8),
466 memo.data(31-i*8 DOWNTO 24-i*8),
469 memo.data(31-i*8 DOWNTO 24-i*8),
467 memo.bdrive(i),
470 memo.bdrive(i),
468 memi.data(31-i*8 DOWNTO 24-i*8));
471 memi.data(31-i*8 DOWNTO 24-i*8));
469 END GENERATE;
472 END GENERATE;
470
473
471 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
474 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
472 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
475 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
473 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
476 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
474 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
477 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
475 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
478 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
476 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
479 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
477 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
480 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
478 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
481 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
479 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
482 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
480
483
481
484
482
485
483 ----------------------------------------------------------------------
486 ----------------------------------------------------------------------
484 --- AHB CONTROLLER -------------------------------------------------
487 --- AHB CONTROLLER -------------------------------------------------
485 ----------------------------------------------------------------------
488 ----------------------------------------------------------------------
486 ahb0 : ahbctrl -- AHB arbiter/multiplexer
489 ahb0 : ahbctrl -- AHB arbiter/multiplexer
487 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
490 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
488 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
491 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
489 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
492 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
490 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
493 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
491
494
492 ----------------------------------------------------------------------
495 ----------------------------------------------------------------------
493 --- AHB UART -------------------------------------------------------
496 --- AHB UART -------------------------------------------------------
494 ----------------------------------------------------------------------
497 ----------------------------------------------------------------------
495 dcomgen : IF CFG_AHB_UART = 1 GENERATE
498 dcomgen : IF CFG_AHB_UART = 1 GENERATE
496 dcom0 : ahbuart
499 dcom0 : ahbuart
497 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
500 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
498 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
501 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
499 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
502 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
500 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
503 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
501 END GENERATE;
504 END GENERATE;
502 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
505 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
503
506
504 ----------------------------------------------------------------------
507 ----------------------------------------------------------------------
505 --- APB Bridge -----------------------------------------------------
508 --- APB Bridge -----------------------------------------------------
506 ----------------------------------------------------------------------
509 ----------------------------------------------------------------------
507 apb0 : apbctrl -- AHB/APB bridge
510 apb0 : apbctrl -- AHB/APB bridge
508 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
511 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
509 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
512 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
510
513
511 ----------------------------------------------------------------------
514 ----------------------------------------------------------------------
512 --- GPT Timer ------------------------------------------------------
515 --- GPT Timer ------------------------------------------------------
513 ----------------------------------------------------------------------
516 ----------------------------------------------------------------------
514 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
517 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
515 timer0 : gptimer -- timer unit
518 timer0 : gptimer -- timer unit
516 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
519 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
517 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
520 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
518 nbits => CFG_GPT_TW)
521 nbits => CFG_GPT_TW)
519 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
522 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
520 gpti.dhalt <= dsuo.tstop;
523 gpti.dhalt <= dsuo.tstop;
521 gpti.extclk <= '0';
524 gpti.extclk <= '0';
522 END GENERATE;
525 END GENERATE;
523 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
526 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
524
527
525
528
526 ----------------------------------------------------------------------
529 ----------------------------------------------------------------------
527 --- APB UART -------------------------------------------------------
530 --- APB UART -------------------------------------------------------
528 ----------------------------------------------------------------------
531 ----------------------------------------------------------------------
529 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
532 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
530 uart1 : apbuart -- UART 1
533 uart1 : apbuart -- UART 1
531 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
534 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
532 fifosize => CFG_UART1_FIFO)
535 fifosize => CFG_UART1_FIFO)
533 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
536 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
534 apbuarti.rxd <= urxd1;
537 apbuarti.rxd <= urxd1;
535 apbuarti.extclk <= '0';
538 apbuarti.extclk <= '0';
536 utxd1 <= apbuarto.txd;
539 utxd1 <= apbuarto.txd;
537 apbuarti.ctsn <= '0';
540 apbuarti.ctsn <= '0';
538 END GENERATE;
541 END GENERATE;
539 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
542 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
540
543
541 -------------------------------------------------------------------------------
544 -------------------------------------------------------------------------------
542 -- AMBA BUS -------------------------------------------------------------------
545 -- AMBA BUS -------------------------------------------------------------------
543 -------------------------------------------------------------------------------
546 -------------------------------------------------------------------------------
544
547
545 -- APB --------------------------------------------------------------------
548 -- APB --------------------------------------------------------------------
546 apbi_ext <= apbi;
549 apbi_ext <= apbi;
547 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
550 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
548 max_16_apb : IF I + 5 < 16 GENERATE
551 max_16_apb : IF I + 5 < 16 GENERATE
549 apbo(I+5) <= apbo_ext(I+5);
552 apbo(I+5) <= apbo_ext(I+5);
550 END GENERATE max_16_apb;
553 END GENERATE max_16_apb;
551 END GENERATE all_apb;
554 END GENERATE all_apb;
552 -- AHB_Slave --------------------------------------------------------------
555 -- AHB_Slave --------------------------------------------------------------
553 ahbi_s_ext <= ahbsi;
556 ahbi_s_ext <= ahbsi;
554 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
557 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
555 max_16_ahbs : IF I + 3 < 16 GENERATE
558 max_16_ahbs : IF I + 3 < 16 GENERATE
556 ahbso(I+3) <= ahbo_s_ext(I+3);
559 ahbso(I+3) <= ahbo_s_ext(I+3);
557 END GENERATE max_16_ahbs;
560 END GENERATE max_16_ahbs;
558 END GENERATE all_ahbs;
561 END GENERATE all_ahbs;
559 -- AHB_Master -------------------------------------------------------------
562 -- AHB_Master -------------------------------------------------------------
560 ahbi_m_ext <= ahbmi;
563 ahbi_m_ext <= ahbmi;
561 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
564 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
562 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
565 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
563 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
566 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
564 END GENERATE max_16_ahbm;
567 END GENERATE max_16_ahbm;
565 END GENERATE all_ahbm;
568 END GENERATE all_ahbm;
566
569
567
570
568
571
569 END Behavioral;
572 END Behavioral;
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