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custom dma : update lock generation into LPP_DMA's FSM state (Just for test)
pellion -
r581:006d69890bba simu_with_Leon3
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
31 USE grlib.devices.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
45 GENERIC (
46 hindex : INTEGER := 2;
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
49 version : IN INTEGER := 0
50 );
50 );
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- FIFO Interface
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
62
63 -- Controls
63 -- Controls
64 send : IN STD_LOGIC;
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
68 );
69 END;
69 END;
70
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
72
73 CONSTANT HConfig : AHB_Config_Type := (
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82
82
83 SIGNAL data_window : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
85
85
86 SIGNAL bus_request : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
88
89 BEGIN
89 BEGIN
90
90
91 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
92 AHB_Master_Out.HCONFIG <= HConfig;
92 AHB_Master_Out.HCONFIG <= HConfig;
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 AHB_Master_Out.HINDEX <= hindex;
94 AHB_Master_Out.HINDEX <= hindex;
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 AHB_Master_Out.HWRITE <= '1';
98 AHB_Master_Out.HWRITE <= '1';
99
99
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
101
102 --AHB_Master_Out.HBUSREQ <= bus_request;
102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
103 --AHB_Master_Out.HLOCK <= data_window;
104
104
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
107 -- '0';
108
108
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
111
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115
115
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
118 --ren <= NOT beat;
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
123 state <= IDLE;
124 done <= '0';
124 done <= '0';
125 address_counter_reg <= (OTHERS => '0');
125 address_counter_reg <= (OTHERS => '0');
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
127 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
128 AHB_Master_Out.HLOCK <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 done <= '0';
130 done <= '0';
131 CASE state IS
131 CASE state IS
132 WHEN IDLE =>
132 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
133 AHB_Master_Out.HBUSREQ <= '0';
134 AHB_Master_Out.HLOCK <= '0';
134 AHB_Master_Out.HLOCK <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
136 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
137 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
141 state <= s_ARBITER;
142 END IF;
142 END IF;
143
143
144 WHEN s_ARBITER =>
144 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
145 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
146 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
148 address_counter_reg <= (OTHERS => '0');
149
149
150 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
150 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
152 state <= s_CTRL;
153 END IF;
153 END IF;
154
154
155 WHEN s_CTRL =>
155 WHEN s_CTRL =>
156 AHB_Master_Out.HBUSREQ <= '1';
156 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
157 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
161 state <= s_CTRL_DATA;
162 END IF;
162 END IF;
163
163
164 WHEN s_CTRL_DATA =>
164 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
165 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
166 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
170 END IF;
171
171
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
173 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
176 state <= s_DATA;
177 END IF;
177 END IF;
178
178
179 WHEN s_DATA =>
179 WHEN s_DATA =>
180 AHB_Master_Out.HBUSREQ <= '0';
180 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
181 --AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
183 IF AHB_Master_In.HREADY = '1' THEN
184 AHB_Master_Out.HLOCK <= '0';
184 state <= IDLE;
185 state <= IDLE;
185 done <= '1';
186 done <= '1';
186 END IF;
187 END IF;
187
188
188 WHEN OTHERS => NULL;
189 WHEN OTHERS => NULL;
189 END CASE;
190 END CASE;
190 END IF;
191 END IF;
191 END PROCESS;
192 END PROCESS;
192
193
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197
198
198 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
199 --PROCESS (clk, rstn)
200 --PROCESS (clk, rstn)
200 --BEGIN -- PROCESS
201 --BEGIN -- PROCESS
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- address_counter_reg <= (OTHERS => '0');
203 -- address_counter_reg <= (OTHERS => '0');
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- address_counter_reg <= address_counter;
205 -- address_counter_reg <= address_counter;
205 -- END IF;
206 -- END IF;
206 --END PROCESS;
207 --END PROCESS;
207
208
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 -- address_counter_reg;
210 -- address_counter_reg;
210 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
211
212
212
213
213 END Behavioral;
214 END Behavioral;
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