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Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B"

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r407:fe963db0333b JC
r662:f19abbf47ea7 SOLO_LFR_01-5B (LFR-EM) default
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vhdlsyn.txt
14 lines | 222 B | text/plain | TextLexer
pellion
temp
r407 lpp_matrix.vhd
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
r217 ALU_Driver.vhd
APB_Matrix.vhd
pellion
Synthesis File Updated
r229 ReUse_CTRLR.vhd
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
r217 Dispatch.vhd
DriveInputs.vhd
GetResult.vhd
MatriceSpectrale.vhd
Matrix.vhd
SpectralMatrix.vhd
Starter.vhd
TopMatrix_PDR.vhd
pellion
Synthesis File Updated
r229 TopSpecMatrix.vhd
Restored previous ALU version as ALU_V0 for IIR filter first version...
r226 Top_MatrixSpec.vhd