HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd

Few fixes....

Few fixes. Whole LFR simulation WIP.

pellion - - Load All Authors

File last commit:

r627:704290a32e3d simu_with_Leon3


                r682:c53e1b6b3045

default

Download file

             top_ad_conv_RHF1401_withFilter.vhd
        
                    233 lines
            
             | 7.6 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / lpp_ad_Conv / top_ad_conv_RHF1401_withFilter.vhd
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
      LIBRARY IEEE;

      USE IEEE.STD_LOGIC_1164.ALL;

      USE IEEE.numeric_std.ALL;

      LIBRARY lpp;

      USE lpp.lpp_ad_conv.ALL;

      USE lpp.general_purpose.SYNC_FF;

      ENTITY top_ad_conv_RHF1401_withFilter IS

        GENERIC(

          ChanelCount     : INTEGER := 8;

        pellion
    
LFR-EQM 2.1.83...

              r601
            
          ncycle_cnv_high : INTEGER := 13;

          ncycle_cnv      : INTEGER := 25;

        pellion
    
 - Update files to simulate with questasim...

              r499
            
          FILTER_ENABLED  : INTEGER := 16#FF#

          );

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        PORT (

          cnv_clk  : IN STD_LOGIC;            -- 24Mhz

          cnv_rstn : IN STD_LOGIC;

          cnv : OUT STD_LOGIC;

          clk        : IN  STD_LOGIC;         -- 25MHz

          rstn       : IN  STD_LOGIC;

          ADC_data   : IN  Samples14;

          ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);

          sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);

          sample_val : OUT STD_LOGIC

          );

      END top_ad_conv_RHF1401_withFilter;

      ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        -----------------------------------------------------------------------------

        -- CNV GEN

        -----------------------------------------------------------------------------

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        SIGNAL cnv_cycle_counter     : INTEGER RANGE 0 TO ncycle_cnv-1;

        SIGNAL cnv_s                 : STD_LOGIC;

        SIGNAL cnv_s_reg             : STD_LOGIC;

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        -----------------------------------------------------------------------------

        -- SYNC CNV

        -----------------------------------------------------------------------------

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        SIGNAL cnv_sync              : STD_LOGIC;

        SIGNAL cnv_sync_pre          : STD_LOGIC;

        SIGNAL cnv_sync_falling_edge : STD_LOGIC;

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        -----------------------------------------------------------------------------

        -- DATA Read and Data Output Enable

        -----------------------------------------------------------------------------

        CONSTANT MAX_CHANNEL_COUNTER   : INTEGER := (ChanelCount-1)*2 + 5;

        SIGNAL channel_counter         : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;

        SIGNAL channel_counter_r       : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;

        SIGNAL channel_counter_r2      : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;

        SIGNAL channel_counter_d1      : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;

        SIGNAL channel_sel_n   : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);

        SIGNAL sample_reg        : Samples14v(ChanelCount-1 DOWNTO 0);

        SIGNAL ADC_data_d1       : Samples14;

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        SIGNAL ADC_data_selected : Samples14;

        pellion
    
Update AD CONV for RHF1401 (LFR-EM) with filter

              r420
            
        SIGNAL ADC_data_result   : Samples15;

        pellion
    
1.1.88...

              r627
            
        CONSTANT SAMPLE_FREQ_DIV_FACTOR : INTEGER := 10;

        SIGNAL   sample_val_counter : INTEGER RANGE 0 TO SAMPLE_FREQ_DIV_FACTOR;

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        pellion
    
 - Update files to simulate with questasim...

              r499
            
        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
      BEGIN

        -----------------------------------------------------------------------------

        -- CNV GEN

        -----------------------------------------------------------------------------

        PROCESS (cnv_clk, cnv_rstn)

        BEGIN  -- PROCESS

          IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)

            cnv_cycle_counter <= 0;

            cnv_s             <= '0';

          ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge

            IF cnv_cycle_counter < ncycle_cnv-1 THEN

              cnv_cycle_counter <= cnv_cycle_counter + 1;

        pellion
    
LFR-EQM 2.1.83...

              r601
            
              IF cnv_cycle_counter < ncycle_cnv_high THEN

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
                cnv_s <= '1';

              ELSE

                cnv_s <= '0';

              END IF;

            ELSE

              cnv_s             <= '1';

              cnv_cycle_counter <= 0;

            END IF;

          END IF;

        END PROCESS;

        cnv <= cnv_s;

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        pellion
    
EQm-debug

              r565
            
        PROCESS (cnv_clk, cnv_rstn)

        BEGIN  -- PROCESS

          IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
            cnv_s_reg <= '0';

        pellion
    
EQm-debug

              r565
            
          ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
            cnv_s_reg <= cnv_s;

        pellion
    
EQm-debug

              r565
            
          END IF;

        END PROCESS;

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        -----------------------------------------------------------------------------

        -- SYNC CNV

        -----------------------------------------------------------------------------

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        SYNC_FF_cnv : SYNC_FF

          GENERIC MAP (

            NB_FF_OF_SYNC => 2)

          PORT MAP (

            clk    => clk,

            rstn   => rstn,

        pellion
    
EQm-debug

              r565
            
            A      => cnv_s_reg,

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
            A_sync => cnv_sync);

        pellion
    
LFR-EQM 2.1.83...

              r601
            
        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
            cnv_sync_pre <= '0';      

          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

            cnv_sync_pre <= cnv_sync;      

        pellion
    
LFR-EQM 2.1.83...

              r601
            
          END IF;

        END PROCESS;

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';

        pellion
    
LFR-EQM 2.1.83...

              r601
            
        -----------------------------------------------------------------------------

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        -- DATA Read and Data Output Enable

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        -----------------------------------------------------------------------------

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
            channel_counter <= MAX_CHANNEL_COUNTER;

            sample_val    <= '0';

        pellion
    
1.1.88...

              r627
            
            sample_val_counter <= 0;

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
            IF cnv_sync_falling_edge = '1' THEN

        pellion
    
LFR-EQM 2.1.83...

              r601
            
              channel_counter <= 0;

            ELSE

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
              IF channel_counter < MAX_CHANNEL_COUNTER THEN

        pellion
    
LFR-EQM 2.1.83...

              r601
            
                channel_counter <= channel_counter + 1;

              END IF;

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
            END IF;

        pellion
    
LFR-EQM 2.1.83...

              r601
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
            IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN

        pellion
    
1.1.88...

              r627
            
              IF sample_val_counter = SAMPLE_FREQ_DIV_FACTOR-1 THEN

                sample_val_counter <= 0;

                sample_val         <= '1';

              ELSE

                sample_val_counter <= sample_val_counter +1; 

                sample_val    <= '0';         

              END IF;        

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
            ELSE

              sample_val    <= '0';

            END IF;      

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
          END IF;

        END PROCESS;

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE

          channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1';

          PROCESS (clk, rstn)

          BEGIN  -- PROCESS

            IF rstn = '0' THEN                  -- asynchronous reset (active low)

              sample_reg(I) <= (OTHERS => '0');

            ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

              IF channel_counter_d1 = 2*I THEN

                IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN

                  sample_reg(I) <= ADC_data_result(14 DOWNTO 1);

                ELSE

                  sample_reg(I) <= ADC_data_d1;

                END IF;          

              END IF;      

            END IF;

          END PROCESS;

        pellion
    
LFR-EQM 2.1.82

              r599
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        END GENERATE all_channel;

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

            ADC_nOE            <= (OTHERS => '1');

            channel_counter_r  <= MAX_CHANNEL_COUNTER;

            channel_counter_r2 <= MAX_CHANNEL_COUNTER;

            channel_counter_d1 <= MAX_CHANNEL_COUNTER;

            ADC_data_d1        <= (OTHERS => '0');

          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

            ADC_nOE            <= channel_sel_n;

            channel_counter_r  <= channel_counter;

            channel_counter_r2 <= channel_counter_r;

            channel_counter_d1 <= channel_counter_r2;

            ADC_data_d1        <= ADC_data;

          END IF;

        END PROCESS;

        WITH channel_counter_d1 SELECT

        pellion
    
LFR-EQM 2.1.83...

              r601
            
          ADC_data_selected <= sample_reg(0) WHEN 0*2,

        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
                               sample_reg(1) WHEN 1*2,

                               sample_reg(2) WHEN 2*2,

                               sample_reg(3) WHEN 3*2,

                               sample_reg(4) WHEN 4*2,

                               sample_reg(5) WHEN 5*2,

                               sample_reg(6) WHEN 6*2,

                               sample_reg(7) WHEN 7*2,

                               sample_reg(8) WHEN OTHERS;

        pellion
    
Issue JIRA : RPWMEB-467...

              r616
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1)));

        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        sample <= sample_reg;

        pellion
    
LFR-EQM 2.1.83...

              r601
            
        pellion
    
LFR-EQM (edn file send to Altran)

              r618
            
        pellion
    
New RHF1401 ADC driver (with simple filter)

              r400
            
      END ar_top_ad_conv_RHF1401;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

pellion New RHF1401 ADC driver (with simple filter)	r400
		LIBRARY IEEE;
		USE IEEE.STD_LOGIC_1164.ALL;
		USE IEEE.numeric_std.ALL;
		LIBRARY lpp;
		USE lpp.lpp_ad_conv.ALL;
		USE lpp.general_purpose.SYNC_FF;

		ENTITY top_ad_conv_RHF1401_withFilter IS
		GENERIC(
		ChanelCount : INTEGER := 8;
pellion LFR-EQM 2.1.83...	r601	ncycle_cnv_high : INTEGER := 13;
		ncycle_cnv : INTEGER := 25;
pellion - Update files to simulate with questasim...	r499	FILTER_ENABLED : INTEGER := 16#FF#
		);
pellion New RHF1401 ADC driver (with simple filter)	r400	PORT (
		cnv_clk : IN STD_LOGIC; -- 24Mhz
		cnv_rstn : IN STD_LOGIC;

		cnv : OUT STD_LOGIC;

		clk : IN STD_LOGIC; -- 25MHz
		rstn : IN STD_LOGIC;
		ADC_data : IN Samples14;
		ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
		sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
		sample_val : OUT STD_LOGIC
		);
		END top_ad_conv_RHF1401_withFilter;

		ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
pellion LFR-EQM (edn file send to Altran)	r618
		-----------------------------------------------------------------------------
		-- CNV GEN
		-----------------------------------------------------------------------------
pellion Issue JIRA : RPWMEB-467...	r616	SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
		SIGNAL cnv_s : STD_LOGIC;
		SIGNAL cnv_s_reg : STD_LOGIC;
pellion LFR-EQM (edn file send to Altran)	r618
		-----------------------------------------------------------------------------
		-- SYNC CNV
		-----------------------------------------------------------------------------
pellion Issue JIRA : RPWMEB-467...	r616	SIGNAL cnv_sync : STD_LOGIC;
		SIGNAL cnv_sync_pre : STD_LOGIC;
		SIGNAL cnv_sync_falling_edge : STD_LOGIC;
pellion New RHF1401 ADC driver (with simple filter)	r400
pellion LFR-EQM (edn file send to Altran)	r618	-----------------------------------------------------------------------------
		-- DATA Read and Data Output Enable
		-----------------------------------------------------------------------------
		CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5;
		SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
		SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
		SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
		SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;

		SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);

		SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
		SIGNAL ADC_data_d1 : Samples14;
pellion New RHF1401 ADC driver (with simple filter)	r400	SIGNAL ADC_data_selected : Samples14;
pellion Update AD CONV for RHF1401 (LFR-EM) with filter	r420	SIGNAL ADC_data_result : Samples15;
pellion 1.1.88...	r627
		CONSTANT SAMPLE_FREQ_DIV_FACTOR : INTEGER := 10;
		SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_FREQ_DIV_FACTOR;
pellion LFR-EQM (edn file send to Altran)	r618
pellion - Update files to simulate with questasim...	r499
pellion Issue JIRA : RPWMEB-467...	r616	CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
pellion New RHF1401 ADC driver (with simple filter)	r400
		BEGIN


		-----------------------------------------------------------------------------
		-- CNV GEN
		-----------------------------------------------------------------------------
		PROCESS (cnv_clk, cnv_rstn)
		BEGIN -- PROCESS
		IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
		cnv_cycle_counter <= 0;
		cnv_s <= '0';
		ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
		IF cnv_cycle_counter < ncycle_cnv-1 THEN
		cnv_cycle_counter <= cnv_cycle_counter + 1;
pellion LFR-EQM 2.1.83...	r601	IF cnv_cycle_counter < ncycle_cnv_high THEN
pellion New RHF1401 ADC driver (with simple filter)	r400	cnv_s <= '1';
		ELSE
		cnv_s <= '0';
		END IF;
		ELSE
		cnv_s <= '1';
		cnv_cycle_counter <= 0;
		END IF;
		END IF;
		END PROCESS;

		cnv <= cnv_s;
pellion Issue JIRA : RPWMEB-467...	r616
pellion EQm-debug	r565	PROCESS (cnv_clk, cnv_rstn)
		BEGIN -- PROCESS
		IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
pellion Issue JIRA : RPWMEB-467...	r616	cnv_s_reg <= '0';
pellion EQm-debug	r565	ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
pellion Issue JIRA : RPWMEB-467...	r616	cnv_s_reg <= cnv_s;
pellion EQm-debug	r565	END IF;
		END PROCESS;
pellion New RHF1401 ADC driver (with simple filter)	r400

		-----------------------------------------------------------------------------
		-- SYNC CNV
		-----------------------------------------------------------------------------
pellion Issue JIRA : RPWMEB-467...	r616
pellion New RHF1401 ADC driver (with simple filter)	r400	SYNC_FF_cnv : SYNC_FF
		GENERIC MAP (
		NB_FF_OF_SYNC => 2)
		PORT MAP (
		clk => clk,
		rstn => rstn,
pellion EQm-debug	r565	A => cnv_s_reg,
pellion New RHF1401 ADC driver (with simple filter)	r400	A_sync => cnv_sync);

pellion LFR-EQM 2.1.83...	r601	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
pellion LFR-EQM (edn file send to Altran)	r618	cnv_sync_pre <= '0';
		ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		cnv_sync_pre <= cnv_sync;
pellion LFR-EQM 2.1.83...	r601	END IF;
		END PROCESS;
pellion Issue JIRA : RPWMEB-467...	r616
pellion LFR-EQM (edn file send to Altran)	r618	cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';

pellion LFR-EQM 2.1.83...	r601
		-----------------------------------------------------------------------------
pellion LFR-EQM (edn file send to Altran)	r618	-- DATA Read and Data Output Enable
pellion New RHF1401 ADC driver (with simple filter)	r400	-----------------------------------------------------------------------------
pellion LFR-EQM (edn file send to Altran)	r618
pellion New RHF1401 ADC driver (with simple filter)	r400	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
pellion LFR-EQM (edn file send to Altran)	r618	channel_counter <= MAX_CHANNEL_COUNTER;
		sample_val <= '0';
pellion 1.1.88...	r627	sample_val_counter <= 0;
pellion LFR-EQM (edn file send to Altran)	r618	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
pellion Issue JIRA : RPWMEB-467...	r616	IF cnv_sync_falling_edge = '1' THEN
pellion LFR-EQM 2.1.83...	r601	channel_counter <= 0;
		ELSE
pellion LFR-EQM (edn file send to Altran)	r618	IF channel_counter < MAX_CHANNEL_COUNTER THEN
pellion LFR-EQM 2.1.83...	r601	channel_counter <= channel_counter + 1;
		END IF;
pellion Issue JIRA : RPWMEB-467...	r616	END IF;
pellion LFR-EQM 2.1.83...	r601
pellion LFR-EQM (edn file send to Altran)	r618	IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN
pellion 1.1.88...	r627	IF sample_val_counter = SAMPLE_FREQ_DIV_FACTOR-1 THEN
		sample_val_counter <= 0;
		sample_val <= '1';
		ELSE
		sample_val_counter <= sample_val_counter +1;
		sample_val <= '0';
		END IF;
pellion LFR-EQM (edn file send to Altran)	r618	ELSE
		sample_val <= '0';
		END IF;
pellion New RHF1401 ADC driver (with simple filter)	r400	END IF;
		END PROCESS;

pellion LFR-EQM (edn file send to Altran)	r618	all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE
		channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1';

		PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
		sample_reg(I) <= (OTHERS => '0');
		ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		IF channel_counter_d1 = 2*I THEN
		IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
		sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
		ELSE
		sample_reg(I) <= ADC_data_d1;
		END IF;
		END IF;
		END IF;
		END PROCESS;
pellion LFR-EQM 2.1.82	r599
pellion LFR-EQM (edn file send to Altran)	r618	END GENERATE all_channel;
pellion Issue JIRA : RPWMEB-467...	r616
pellion LFR-EQM (edn file send to Altran)	r618	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
		ADC_nOE <= (OTHERS => '1');
		channel_counter_r <= MAX_CHANNEL_COUNTER;
		channel_counter_r2 <= MAX_CHANNEL_COUNTER;
		channel_counter_d1 <= MAX_CHANNEL_COUNTER;
		ADC_data_d1 <= (OTHERS => '0');
		ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		ADC_nOE <= channel_sel_n;
		channel_counter_r <= channel_counter;
		channel_counter_r2 <= channel_counter_r;
		channel_counter_d1 <= channel_counter_r2;
		ADC_data_d1 <= ADC_data;
		END IF;
		END PROCESS;

		WITH channel_counter_d1 SELECT
pellion LFR-EQM 2.1.83...	r601	ADC_data_selected <= sample_reg(0) WHEN 0*2,
pellion LFR-EQM (edn file send to Altran)	r618	sample_reg(1) WHEN 1*2,
		sample_reg(2) WHEN 2*2,
		sample_reg(3) WHEN 3*2,
		sample_reg(4) WHEN 4*2,
		sample_reg(5) WHEN 5*2,
		sample_reg(6) WHEN 6*2,
		sample_reg(7) WHEN 7*2,
		sample_reg(8) WHEN OTHERS;
pellion Issue JIRA : RPWMEB-467...	r616
pellion LFR-EQM (edn file send to Altran)	r618	ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1)));
pellion New RHF1401 ADC driver (with simple filter)	r400
pellion LFR-EQM (edn file send to Altran)	r618	sample <= sample_reg;
pellion LFR-EQM 2.1.83...	r601
pellion LFR-EQM (edn file send to Altran)	r618
pellion New RHF1401 ADC driver (with simple filter)	r400
		END ar_top_ad_conv_RHF1401;