HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/general_purpose/general_counter.vhd

Few fixes....

Few fixes. Whole LFR simulation WIP.

Alexis Jeandet - - Load All Authors

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        pellion
    
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              r330
            
      LIBRARY IEEE;

      USE IEEE.STD_LOGIC_1164.ALL;

        pellion
    
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              r547
            
      USE IEEE.NUMERIC_STD.ALL;

        pellion
    
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      ENTITY general_counter IS

        GENERIC (

          CYCLIC          : STD_LOGIC := '1';

        pellion
    
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          NB_BITS_COUNTER : INTEGER   := 9;

          RST_VALUE       : INTEGER   := 0

        pellion
    
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          );

        PORT (

          clk       : IN  STD_LOGIC;

          rstn      : IN  STD_LOGIC;

          --

        Alexis Jeandet
    
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

              r655
            
          MAX_VALUE : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);

        pellion
    
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          --

          set       : IN  STD_LOGIC;

          set_value : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);

          add1      : IN  STD_LOGIC;

          counter   : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)

          );

      END general_counter;

      ARCHITECTURE beh OF general_counter IS

        pellion
    
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        CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));

        SIGNAL   counter_s   : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);

        pellion
    
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      BEGIN  -- beh

        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

        pellion
    
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          IF rstn = '0' THEN                  -- asynchronous reset (active low)

            counter_s <= RST_VALUE_v;

          ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge

        pellion
    
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              r330
            
            IF set = '1' THEN

              counter_s <= set_value;

            ELSIF add1 = '1' THEN

              IF counter_s < MAX_VALUE THEN

        pellion
    
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              r547
            
                counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));

        pellion
    
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              r330
            
              ELSE

                IF CYCLIC = '1' THEN

                  counter_s <= (OTHERS => '0');

                END IF;

              END IF;

            END IF;

          END IF;

        END PROCESS;

        counter <= counter_s;

        pellion
    
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              r547
            
        pellion
    
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      END beh;

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pellion MINI LFR - WFP&MS - 0.1.6...	r330	LIBRARY IEEE;
		USE IEEE.STD_LOGIC_1164.ALL;
pellion minor update (cleaning file)	r547	USE IEEE.NUMERIC_STD.ALL;
pellion MINI LFR - WFP&MS - 0.1.6...	r330
		ENTITY general_counter IS

		GENERIC (
		CYCLIC : STD_LOGIC := '1';
pellion minor update (cleaning file)	r547	NB_BITS_COUNTER : INTEGER := 9;
		RST_VALUE : INTEGER := 0
pellion MINI LFR - WFP&MS - 0.1.6...	r330	);

		PORT (
		clk : IN STD_LOGIC;
		rstn : IN STD_LOGIC;
		--
Alexis Jeandet Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...	r655	MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
pellion MINI LFR - WFP&MS - 0.1.6...	r330	--
		set : IN STD_LOGIC;
		set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
		add1 : IN STD_LOGIC;
		counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
		);

		END general_counter;

		ARCHITECTURE beh OF general_counter IS
pellion minor update (cleaning file)	r547	CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
		SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
pellion MINI LFR - WFP&MS - 0.1.6...	r330
		BEGIN -- beh

		PROCESS (clk, rstn)
		BEGIN -- PROCESS
pellion minor update (cleaning file)	r547	IF rstn = '0' THEN -- asynchronous reset (active low)
		counter_s <= RST_VALUE_v;
		ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
pellion MINI LFR - WFP&MS - 0.1.6...	r330	IF set = '1' THEN
		counter_s <= set_value;
		ELSIF add1 = '1' THEN
		IF counter_s < MAX_VALUE THEN
pellion minor update (cleaning file)	r547	counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
pellion MINI LFR - WFP&MS - 0.1.6...	r330	ELSE
		IF CYCLIC = '1' THEN
		counter_s <= (OTHERS => '0');
		END IF;
		END IF;
		END IF;
		END IF;
		END PROCESS;

		counter <= counter_s;
pellion minor update (cleaning file)	r547
pellion MINI LFR - WFP&MS - 0.1.6...	r330	END beh;