HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_CIC_LFR/run_add_sub.do

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

pellion - - Load All Authors

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simu_with_Leon3

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             run_add_sub.do
        
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        pellion
    
Correction du CIC (probleme d'ecriture des datas des COMB 256)

              r500
            
      vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_pkg.vhd

      vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd

      vcom -quiet  -93  -work work tb_cic_lfr_add_sub.vhd

      vsim work.testbench

      log -r *

      do wave_add_sub.do

      run -all

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pellion Correction du CIC (probleme d'ecriture des datas des COMB 256)	r500	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd
		vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd

		vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd

		vsim work.testbench

		log -r *

		do wave_add_sub.do

		run -all