HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_RAM_CEL/run.do

Add SDC constraint files for MINI-LFR board....

Add SDC constraint files for MINI-LFR board. To include those constraints, you must into design's makefile the : SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc During the Libero flow, you must choice the MINI_LFR_synthesis.sdc file for the synthesis step, and the MINI_LFR_place_and_route.sdc file for the place and route step.

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        pellion
    
temp

              r406
            
      log -R *

      do wave.do

      run 10 ms

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