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Sync, Working on BeagleSynth design.
Sync, Working on BeagleSynth design.
Jeandet Alexis - - Load All Authors

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r263:9bf9890b50e7 alexis
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default.ucf
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Jeandet Alexis
Sync, Working on BeagleSynth design.
 r263
NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "CLK" LOC = "K20";
Jeandet Alexis
Started preliminary version of BeagleSynth board.
 r255
NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
Jeandet Alexis
Sync, Working on BeagleSynth design.
 r263 NET "RESET" LOC = "AB11";
Jeandet Alexis
Started preliminary version of BeagleSynth board.
 r255
Jeandet Alexis
Sync, Working on BeagleSynth design.
 r263 NET "DAC_nCLR" LOC = "R11";
NET "DAC_nCS" LOC = "T12";
NET "CAL_IN_SCK" LOC = "R13";
NET "DAC_SDI(0)" LOC = "P5";
NET "DAC_SDI(1)" LOC = "M5";
NET "DAC_SDI(2)" LOC = "C8";
NET "DAC_SDI(3)" LOC = "M6";
NET "DAC_SDI(4)" LOC = "K22";
NET "DAC_SDI(5)" LOC = "L22";
NET "DAC_SDI(6)" LOC = "G19";
NET "DAC_SDI(7)" LOC = "F20";
Jeandet Alexis
Started preliminary version of BeagleSynth board.
 r255
Jeandet Alexis
Sync, Working on BeagleSynth design.
 r263 NET "TDX" LOC = "V22";
NET "RXD" LOC = "U22";
NET "LED(0)" LOC = "AB9";
NET "LED(1)" LOC = "AB8";
NET "LED(2)" LOC = "AA8";
Jeandet Alexis
Started preliminary version of BeagleSynth board.
 r255
Jeandet Alexis
Sync, Working on BeagleSynth design.
 r263 NET "urxd1" LOC = "D3"; # Unused PIN
NET "utxd1" LOC = "C4"; # Unused PIN