top_ad_conv_RHF1401_withFilter.vhd
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r400 | |||
LIBRARY IEEE; | ||||
USE IEEE.STD_LOGIC_1164.ALL; | ||||
USE IEEE.numeric_std.ALL; | ||||
LIBRARY lpp; | ||||
USE lpp.lpp_ad_conv.ALL; | ||||
USE lpp.general_purpose.SYNC_FF; | ||||
ENTITY top_ad_conv_RHF1401_withFilter IS | ||||
GENERIC( | ||||
ChanelCount : INTEGER := 8; | ||||
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r601 | ncycle_cnv_high : INTEGER := 13; | ||
ncycle_cnv : INTEGER := 25; | ||||
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r499 | FILTER_ENABLED : INTEGER := 16#FF# | ||
); | ||||
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r400 | PORT ( | ||
cnv_clk : IN STD_LOGIC; -- 24Mhz | ||||
cnv_rstn : IN STD_LOGIC; | ||||
cnv : OUT STD_LOGIC; | ||||
clk : IN STD_LOGIC; -- 25MHz | ||||
rstn : IN STD_LOGIC; | ||||
ADC_data : IN Samples14; | ||||
ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | ||||
sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | ||||
sample_val : OUT STD_LOGIC | ||||
); | ||||
END top_ad_conv_RHF1401_withFilter; | ||||
ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS | ||||
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r618 | |||
----------------------------------------------------------------------------- | ||||
-- CNV GEN | ||||
----------------------------------------------------------------------------- | ||||
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r616 | SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1; | ||
SIGNAL cnv_s : STD_LOGIC; | ||||
SIGNAL cnv_s_reg : STD_LOGIC; | ||||
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r618 | |||
----------------------------------------------------------------------------- | ||||
-- SYNC CNV | ||||
----------------------------------------------------------------------------- | ||||
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r616 | SIGNAL cnv_sync : STD_LOGIC; | ||
SIGNAL cnv_sync_pre : STD_LOGIC; | ||||
SIGNAL cnv_sync_falling_edge : STD_LOGIC; | ||||
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r400 | |||
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r618 | ----------------------------------------------------------------------------- | ||
-- DATA Read and Data Output Enable | ||||
----------------------------------------------------------------------------- | ||||
CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5; | ||||
SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; | ||||
SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; | ||||
SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; | ||||
SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; | ||||
SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | ||||
SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); | ||||
SIGNAL ADC_data_d1 : Samples14; | ||||
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r400 | SIGNAL ADC_data_selected : Samples14; | ||
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r420 | SIGNAL ADC_data_result : Samples15; | ||
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r627 | |||
CONSTANT SAMPLE_FREQ_DIV_FACTOR : INTEGER := 10; | ||||
SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_FREQ_DIV_FACTOR; | ||||
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r618 | |||
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r499 | |||
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r616 | CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount)); | ||
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r400 | |||
BEGIN | ||||
----------------------------------------------------------------------------- | ||||
-- CNV GEN | ||||
----------------------------------------------------------------------------- | ||||
PROCESS (cnv_clk, cnv_rstn) | ||||
BEGIN -- PROCESS | ||||
IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | ||||
cnv_cycle_counter <= 0; | ||||
cnv_s <= '0'; | ||||
ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | ||||
IF cnv_cycle_counter < ncycle_cnv-1 THEN | ||||
cnv_cycle_counter <= cnv_cycle_counter + 1; | ||||
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r601 | IF cnv_cycle_counter < ncycle_cnv_high THEN | ||
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r400 | cnv_s <= '1'; | ||
ELSE | ||||
cnv_s <= '0'; | ||||
END IF; | ||||
ELSE | ||||
cnv_s <= '1'; | ||||
cnv_cycle_counter <= 0; | ||||
END IF; | ||||
END IF; | ||||
END PROCESS; | ||||
cnv <= cnv_s; | ||||
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r616 | |||
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r565 | PROCESS (cnv_clk, cnv_rstn) | ||
BEGIN -- PROCESS | ||||
IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | ||||
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r616 | cnv_s_reg <= '0'; | ||
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r565 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | ||
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r616 | cnv_s_reg <= cnv_s; | ||
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r565 | END IF; | ||
END PROCESS; | ||||
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r400 | |||
----------------------------------------------------------------------------- | ||||
-- SYNC CNV | ||||
----------------------------------------------------------------------------- | ||||
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r616 | |||
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r400 | SYNC_FF_cnv : SYNC_FF | ||
GENERIC MAP ( | ||||
NB_FF_OF_SYNC => 2) | ||||
PORT MAP ( | ||||
clk => clk, | ||||
rstn => rstn, | ||||
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r565 | A => cnv_s_reg, | ||
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r400 | A_sync => cnv_sync); | ||
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r601 | PROCESS (clk, rstn) | ||
BEGIN -- PROCESS | ||||
IF rstn = '0' THEN -- asynchronous reset (active low) | ||||
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r618 | cnv_sync_pre <= '0'; | ||
ELSIF clk'event AND clk = '1' THEN -- rising clock edge | ||||
cnv_sync_pre <= cnv_sync; | ||||
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r601 | END IF; | ||
END PROCESS; | ||||
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r616 | |||
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r618 | cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0'; | ||
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r601 | |||
----------------------------------------------------------------------------- | ||||
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r618 | -- DATA Read and Data Output Enable | ||
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r400 | ----------------------------------------------------------------------------- | ||
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r618 | |||
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r400 | PROCESS (clk, rstn) | ||
BEGIN -- PROCESS | ||||
IF rstn = '0' THEN -- asynchronous reset (active low) | ||||
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r618 | channel_counter <= MAX_CHANNEL_COUNTER; | ||
sample_val <= '0'; | ||||
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r627 | sample_val_counter <= 0; | ||
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r618 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | ||
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r616 | IF cnv_sync_falling_edge = '1' THEN | ||
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r601 | channel_counter <= 0; | ||
ELSE | ||||
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r618 | IF channel_counter < MAX_CHANNEL_COUNTER THEN | ||
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r601 | channel_counter <= channel_counter + 1; | ||
END IF; | ||||
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r616 | END IF; | ||
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r601 | |||
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r618 | IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN | ||
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r627 | IF sample_val_counter = SAMPLE_FREQ_DIV_FACTOR-1 THEN | ||
sample_val_counter <= 0; | ||||
sample_val <= '1'; | ||||
ELSE | ||||
sample_val_counter <= sample_val_counter +1; | ||||
sample_val <= '0'; | ||||
END IF; | ||||
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r618 | ELSE | ||
sample_val <= '0'; | ||||
END IF; | ||||
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r400 | END IF; | ||
END PROCESS; | ||||
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r618 | all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE | ||
channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1'; | ||||
PROCESS (clk, rstn) | ||||
BEGIN -- PROCESS | ||||
IF rstn = '0' THEN -- asynchronous reset (active low) | ||||
sample_reg(I) <= (OTHERS => '0'); | ||||
ELSIF clk'event AND clk = '1' THEN -- rising clock edge | ||||
IF channel_counter_d1 = 2*I THEN | ||||
IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN | ||||
sample_reg(I) <= ADC_data_result(14 DOWNTO 1); | ||||
ELSE | ||||
sample_reg(I) <= ADC_data_d1; | ||||
END IF; | ||||
END IF; | ||||
END IF; | ||||
END PROCESS; | ||||
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r599 | |||
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r618 | END GENERATE all_channel; | ||
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r616 | |||
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r618 | PROCESS (clk, rstn) | ||
BEGIN -- PROCESS | ||||
IF rstn = '0' THEN -- asynchronous reset (active low) | ||||
ADC_nOE <= (OTHERS => '1'); | ||||
channel_counter_r <= MAX_CHANNEL_COUNTER; | ||||
channel_counter_r2 <= MAX_CHANNEL_COUNTER; | ||||
channel_counter_d1 <= MAX_CHANNEL_COUNTER; | ||||
ADC_data_d1 <= (OTHERS => '0'); | ||||
ELSIF clk'event AND clk = '1' THEN -- rising clock edge | ||||
ADC_nOE <= channel_sel_n; | ||||
channel_counter_r <= channel_counter; | ||||
channel_counter_r2 <= channel_counter_r; | ||||
channel_counter_d1 <= channel_counter_r2; | ||||
ADC_data_d1 <= ADC_data; | ||||
END IF; | ||||
END PROCESS; | ||||
WITH channel_counter_d1 SELECT | ||||
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r601 | ADC_data_selected <= sample_reg(0) WHEN 0*2, | ||
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r618 | sample_reg(1) WHEN 1*2, | ||
sample_reg(2) WHEN 2*2, | ||||
sample_reg(3) WHEN 3*2, | ||||
sample_reg(4) WHEN 4*2, | ||||
sample_reg(5) WHEN 5*2, | ||||
sample_reg(6) WHEN 6*2, | ||||
sample_reg(7) WHEN 7*2, | ||||
sample_reg(8) WHEN OTHERS; | ||||
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r616 | |||
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r618 | ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1))); | ||
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r400 | |||
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r618 | sample <= sample_reg; | ||
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r601 | |||
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r618 | |||
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r400 | |||
END ar_top_ad_conv_RHF1401; | ||||