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Correction de la FSM qui regule les données entrant dans la FFT
Correction de la FSM qui regule les données entrant dans la FFT
martin - - Load All Authors

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r99:fb73d940a921 martin
r557:7faec0eb9fbb (MINI-LFR) WFP_MS-0-1-67 (LFR-EM) WFP_MS_1-1-67 JC
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APB_UART.vhd
144 lines | 5.0 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lpp_uart / APB_UART.vhd
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Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
martin
debug lpp_uart and comment lpp_cna
 r40 ------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
------------------------------------------------------------------------------
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library lpp;
use lpp.lpp_amba.all;
Alexis
Fixed some files
 r37 use lpp.apb_devices_list.all;
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 use lpp.lpp_uart.all;
alexis
Improved doxygen html output, improved documentation on some VHDL and C files.
 r67 --! This is an APB UART you should use it with a processor as UART and drive it with its register over AMBA bus.
--! \author Martin Morlot martin.morlot@lpp.polytechnique.fr
martin
debug lpp_uart and comment lpp_cna
 r40
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 entity APB_UART is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
abits : integer := 8;
Data_sz : integer := 8);
port (
alexis
Improved doxygen html output, improved documentation on some VHDL and C files.
 r67 clk : in std_logic; --! System clock
rst : in std_logic; --! System reset
apbi : in apb_slv_in_type; --! APB input signals see grlib.amba package
apbo : out apb_slv_out_type; --! APB input signals see grlib.amba package
TXD : out std_logic; --! UART Transmission pin
RXD : in std_logic --! UART Reception pin
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 );
end APB_UART;
architecture ar_APB_UART of APB_UART is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
signal NwData : std_logic;
signal ACK : std_logic;
signal Capture : std_logic;
signal Send : std_logic;
signal Sended : std_logic;
type UART_ctrlr_Reg is record
martin
debug lpp_uart and comment lpp_cna
 r40 UART_Cfg : std_logic_vector(2 downto 0);
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 UART_Wdata : std_logic_vector(7 downto 0);
UART_Rdata : std_logic_vector(7 downto 0);
UART_BTrig : std_logic_vector(11 downto 0);
end record;
signal Rec : UART_ctrlr_Reg;
martin
GRLIB changes
 r29 signal Rdata : std_logic_vector(31 downto 0);
martin
debug lpp_uart and comment lpp_cna
 r40 signal temp_ND : std_logic;
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19
begin
Capture <= Rec.UART_Cfg(0);
martin
debug lpp_uart and comment lpp_cna
 r40 Rec.UART_Cfg(1) <= Sended;
Rec.UART_Cfg(2) <= NwData;
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19
martin
fixed bug on UART
 r62 COM0 : UART
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 generic map (Data_sz)
port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
process(rst,clk)
begin
if(rst='0')then
Rec.UART_Wdata <= (others => '0');
martin
Update and debug UART
 r99 Send <= '0';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19
martin
debug lpp_uart and comment lpp_cna
 r40 elsif(clk'event and clk='1')then
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19
--APB Write OP
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
Alexis
Improved IIR filter configuration
 r35 case apbi.paddr(7 downto 2) is
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when "000000" =>
martin
debug lpp_uart and comment lpp_cna
 r40 Rec.UART_Cfg(0) <= apbi.pwdata(0);
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when "000001" =>
martin
Update and debug UART
 r99 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
Send <= '1';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when others =>
null;
end case;
martin
Update and debug UART
 r99 elsif(Sended = '0')then
Send <= '0';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 end if;
--APB READ OP
martin
GRLIB changes
 r29 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
Alexis
Improved IIR filter configuration
 r35 case apbi.paddr(7 downto 2) is
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when "000000" =>
martin
debug lpp_uart and comment lpp_cna
 r40 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
Rdata(19 downto 12) <= X"EE";
Rdata(31 downto 20) <= Rec.UART_BTrig;
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when "000001" =>
martin
debug lpp_uart and comment lpp_cna
 r40 Rdata(31 downto 8) <= X"EEEEEE";
martin
GRLIB changes
 r29 Rdata(7 downto 0) <= Rec.UART_Wdata;
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when "000010" =>
martin
debug lpp_uart and comment lpp_cna
 r40 Rdata(31 downto 8) <= X"EEEEEE";
martin
GRLIB changes
 r29 Rdata(7 downto 0) <= Rec.UART_Rdata;
martin
Update and debug UART
 r99 ACK <= '1';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 when others =>
martin
GRLIB changes
 r29 Rdata <= (others => '0');
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 end case;
martin
Update and debug UART
 r99 else
ACK <= '0';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 end if;
end if;
apbo.pconfig <= pconfig;
end process;
martin
GRLIB changes
 r29 apbo.prdata <= Rdata when apbi.penable = '1';
Alexis
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
 r19 end ar_APB_UART;