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Correction de la FSM qui regule les données entrant dans la FFT
Correction de la FSM qui regule les données entrant dans la FFT
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r557:7faec0eb9fbb (MINI-LFR) WFP_MS-0-1-67 (LFR-EM) WFP_MS_1-1-67 JC
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Dispatch.vhd
88 lines | 2.8 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lpp_matrix / Dispatch.vhd
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martin
Débug de la FIFO...
 r103 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity Dispatch is
generic(
Data_SZ : integer := 32);
port(
clk : in std_logic;
reset : in std_logic;
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update CAL 1/2
 r236 Ack : in std_logic;
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 r103 Data : in std_logic_vector(Data_SZ-1 downto 0);
Write : in std_logic;
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UP
 r175 Valid : in std_logic;
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 r103 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
FifoWrite : out std_logic_vector(1 downto 0);
Error : out std_logic
);
end entity;
architecture ar_Dispatch of Dispatch is
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 r109 type etat is (eX,e0,e1,e2);
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 r103 signal ect : etat;
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update CAL 1/2
 r236 signal Pong : std_logic;
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 r109
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 r103 begin
process (clk,reset)
begin
if(reset='0')then
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update CAL 1/2
 r236 Pong <= '0';
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 r109 Error <= '0';
ect <= e0;
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 r103
elsif(clk' event and clk='1')then
case ect is
when e0 =>
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UP
 r175 if(Valid = '1')then
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update CAL 1/2
 r236 Pong <= not Pong;
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 r103 ect <= e1;
end if;
when e1 =>
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update CAL 1/2
 r236 if(Ack = '0')then
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 r103 Error <= '1';
ect <= e1;
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 r109 else
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 r103 Error <= '0';
ect <= e0;
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 r109 end if;
when others =>
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update CAL 1/2
 r236 null;
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 r103
end case;
end if;
end process;
FifoData <= Data & Data;
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update CAL 1/2
 r236 FifoWrite <= '1' & not Write when Pong='0' else not Write & '1';
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 r103
end architecture;