TimerDelay.vhd
73 lines
| 1.7 KiB
| text/x-vhdl
|
VhdlLexer
martin
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r80 | -- TimerDelay.vhd | |
| library IEEE; | |||
| use IEEE.numeric_std.all; | |||
| use IEEE.std_logic_1164.all; | |||
| entity TimerDelay is | |||
| port( | |||
| clk : in std_logic; | |||
| raz : in std_logic; | |||
| Start : in std_logic; | |||
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r86 | OKfin : in std_logic; | |
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r80 | Fin : out std_logic; | |
| Cpt : in std_logic_vector(25 downto 0) | |||
| ); | |||
| end TimerDelay; | |||
| architecture ar_TimerDelay of TimerDelay is | |||
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r86 | type state is (stX,st1,st2); | |
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r80 | signal ect : state; | |
| constant MAX : integer := 67_108_863; | |||
| signal delay : integer range 0 to MAX; | |||
| signal compt : integer range 0 to MAX; | |||
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r86 | --signal Start_reg : std_logic; | |
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r80 | ||
| begin | |||
| delay <= to_integer(unsigned(Cpt)); | |||
| process(clk,raz) | |||
| begin | |||
| if(raz='0')then | |||
| Fin <= '1'; | |||
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r86 | --Start_reg <= '0'; | |
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r80 | ect <= stX; | |
| elsif(clk'event and clk='1')then | |||
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r86 | --Start_reg <= Start; | |
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r80 | ||
| case ect is | |||
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r86 | when stX => | |
| if(Start = '1')then | |||
| --OKst <= '1'; | |||
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r80 | ect <= st1; | |
| end if; | |||
| when st1 => | |||
| if(compt = delay)then | |||
| compt <= 0; | |||
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r86 | --OKst <= '0'; | |
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r80 | Fin <= '1'; | |
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r86 | ect <= st2; | |
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r80 | else | |
| compt <= compt + 1; | |||
| ect <= st1; | |||
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r86 | end if; | |
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r80 | ||
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r86 | when st2 => | |
| if(OKfin = '1')then | |||
| Fin <= '0'; | |||
| ect <= stX; | |||
| end if; | |||
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r80 | end case; | |
| end if; | |||
| end process; | |||
| end ar_TimerDelay; |