mig.xco
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r129 | ############################################################## | |||
# | ||||
# Xilinx Core Generator version 14.2 | ||||
# Date: Mon Apr 8 17:56:57 2013 | ||||
# | ||||
############################################################## | ||||
# | ||||
# This file contains the customisation parameters for a | ||||
# Xilinx CORE Generator IP GUI. It is strongly recommended | ||||
# that you do not manually alter this file as it may cause | ||||
# unexpected and unsupported behavior. | ||||
# | ||||
############################################################## | ||||
# | ||||
# Generated from component: xilinx.com:ip:mig:3.92 | ||||
# | ||||
############################################################## | ||||
# | ||||
# BEGIN Project Options | ||||
SET addpads = false | ||||
SET asysymbol = true | ||||
SET busformat = BusFormatAngleBracketNotRipped | ||||
SET createndf = false | ||||
SET designentry = VHDL | ||||
SET device = xc6slx45 | ||||
SET devicefamily = spartan6 | ||||
SET flowvendor = Other | ||||
SET formalverification = false | ||||
SET foundationsym = false | ||||
SET implementationfiletype = Ngc | ||||
SET package = fgg484 | ||||
SET removerpms = false | ||||
SET simulationfiles = Behavioral | ||||
SET speedgrade = -3 | ||||
SET verilogsim = false | ||||
SET vhdlsim = true | ||||
# END Project Options | ||||
# BEGIN Select | ||||
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92 | ||||
# END Select | ||||
# BEGIN Parameters | ||||
CSET component_name=mig_38 | ||||
CSET xml_input_file=./mig_38/user_design/mig.prj | ||||
# END Parameters | ||||
# BEGIN Extra information | ||||
MISC pkg_timestamp=2012-07-21T06:31:03Z | ||||
# END Extra information | ||||
GENERATE | ||||
# CRC: 62df7c4e | ||||