Serialize.vhd
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| text/x-vhdl
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VhdlLexer
martin
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r40 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------ | ||||
-- Author : Martin Morlot | ||||
-- Mail : martin.morlot@lpp.polytechnique.fr | ||||
------------------------------------------------------------------------------ | ||||
library IEEE; | ||||
use IEEE.numeric_std.all; | ||||
use IEEE.std_logic_1164.all; | ||||
--! Programme qui permet de s�rialiser un vecteur | ||||
entity Serialize is | ||||
port( | ||||
clk,raz : in std_logic; --! Horloge et Reset du composant | ||||
sclk : in std_logic; --! Horloge Systeme | ||||
vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e | ||||
send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente | ||||
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r261 | sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e | ||
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r40 | Data : out std_logic --! Donn�e num�rique s�rialis� | ||
); | ||||
end Serialize; | ||||
architecture ar_Serialize of Serialize is | ||||
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r274 | type etat is (chargemT,serialize); | ||
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r40 | signal ect : etat; | ||
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r17 | signal vector_int : std_logic_vector(16 downto 0); | ||
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r274 | --signal vectin_reg : std_logic_vector(15 downto 0); | ||
--signal load : std_logic; | ||||
signal send_reg : std_logic; | ||||
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r40 | signal N : integer range 0 to 16; | ||
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r17 | signal CPT_ended : std_logic:='0'; | ||
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r40 | |||
begin | ||||
process(clk,raz) | ||||
begin | ||||
if(raz='0')then | ||||
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r274 | ect <= chargemT; | ||
-- vectin_reg <= (others=> '0'); | ||||
-- load <= '0'; | ||||
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r261 | sended <= '1'; | ||
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r40 | |||
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r274 | elsif(clk'event and clk='1')then | ||
-- vectin_reg <= vectin; | ||||
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r40 | |||
case ect is | ||||
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r274 | when chargemT => | ||
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r17 | if (send='1') then | ||
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r261 | sended <= '0'; | ||
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r274 | -- load <= '1'; | ||
ect <= serialize; | ||||
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r40 | end if; | ||
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r17 | when serialize => | ||
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r274 | -- load <= '0'; | ||
if(N=14)then | ||||
sended <= '1'; | ||||
end if; | ||||
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r40 | if(CPT_ended='1')then | ||
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r274 | ect <= chargemT; | ||
-- sended <= '1'; | ||||
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r17 | end if; | ||
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r40 | |||
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r274 | -- when attente => | ||
-- if(send='0')then | ||||
-- ect <= chargemT; | ||||
-- end if; | ||||
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r40 | end case; | ||
end if; | ||||
end process; | ||||
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r274 | process(sclk,raz) | ||
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r40 | begin | ||
if (raz='0')then | ||||
vector_int <= (others=> '0'); | ||||
N <= 16; | ||||
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r274 | -- elsif(send='1')then | ||
-- vector_int <= vectin & '0'; | ||||
-- N <= 0; | ||||
elsif(sclk'event and sclk='1')then | ||||
send_reg <= send; | ||||
if(send_reg='1' and send='0')then | ||||
vector_int <= vectin & '0'; | ||||
elsif(send='1')then | ||||
N <= 0; | ||||
elsif (CPT_ended='0') then | ||||
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r40 | vector_int <= vector_int(15 downto 0) & '0'; | ||
N <= N+1; | ||||
end if; | ||||
end if; | ||||
end process; | ||||
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r17 | CPT_ended <= '1' when N = 16 else '0'; | ||
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r40 | |||
with ect select | ||||
Data <= vector_int(16) when serialize, | ||||
'0' when others; | ||||
end ar_Serialize; | ||||