HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lfr_time_management/lfr_time_management.vhd

Étiquette (LFR-EM) WFP_MS-0-1-9 ajoutée à la révision

pellion - - Load All Authors

File last commit:

r336:d05a1ff29f0e (MINI-LFR) WFP_MS-0-1-9 JC


                r339:56090c0add39

Download file

             lfr_time_management.vhd
        
                    174 lines
            
             | 5.7 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / lfr_time_management / lfr_time_management.vhd
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        paul
    
lfr_time_management added to the repository

              r153
            
      ----------------------------------------------------------------------------------

      -- Company: 

      -- Engineer: 

      -- 

      -- Create Date:    11:14:05 07/02/2012 

      -- Design Name: 

      -- Module Name:    lfr_time_management - Behavioral 

      -- Project Name: 

      -- Target Devices: 

      -- Tool versions: 

      -- Description: 

      --

      -- Dependencies: 

      --

      -- Revision: 

      -- Revision 0.01 - File Created

      -- Additional Comments: 

      --

      ----------------------------------------------------------------------------------

        pellion
    
temp

              r186
            
      LIBRARY IEEE;

      USE IEEE.STD_LOGIC_1164.ALL;

      USE IEEE.NUMERIC_STD.ALL;

      LIBRARY lpp;

        pellion
    
update time_managment

              r227
            
      USE lpp.lpp_lfr_time_management.ALL;

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
temp

              r186
            
      ENTITY lfr_time_management IS

        GENERIC (

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
          FIRST_DIVISION   : INTEGER := 374;

          NB_SECOND_DESYNC : INTEGER := 60);

        pellion
    
temp

              r186
            
        PORT (

        pellion
    
update time_managment

              r227
            
          clk  : IN STD_LOGIC;

          rstn : IN STD_LOGIC;

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
          tick           : IN STD_LOGIC;      -- transition signal information

        pellion
    
update time_managment

              r227
            
          new_coarsetime : IN STD_LOGIC;      -- transition signal information

        pellion
    
Update APB_TIME_MANAGEMENT :...

              r336
            
          coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);

        pellion
    
update time_managment

              r227
            
          fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

          fine_time_new   : OUT STD_LOGIC;

          coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

          coarse_time_new : OUT STD_LOGIC

        pellion
    
temp

              r186
            
          );

      END lfr_time_management;

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
temp

              r186
            
      ARCHITECTURE Behavioral OF lfr_time_management IS

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
        SIGNAL FT_max : STD_LOGIC;

        SIGNAL FT_half : STD_LOGIC;

        SIGNAL FT_wait : STD_LOGIC;

        TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);

        SIGNAL state : state_fsm_time_management;

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
        SIGNAL fsm_desync   : STD_LOGIC;

        SIGNAL fsm_transition : STD_LOGIC;

        pellion
    
WaveFormPicker Update...

              r232
            
        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
        SIGNAL set_TCU : STD_LOGIC;

        SIGNAL CT_add1 : STD_LOGIC;

        SIGNAL new_coarsetime_reg : STD_LOGIC;

        pellion
    
temp

              r186
            
      BEGIN

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
        -----------------------------------------------------------------------------

        -- 

        -----------------------------------------------------------------------------

        pellion
    
update time_managment

              r227
            
        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
            new_coarsetime_reg <= '0';

          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

        pellion
    
WaveFormPicker Update...

              r232
            
            IF new_coarsetime = '1' THEN

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
              new_coarsetime_reg <= '1';

            ELSIF tick = '1' THEN

              new_coarsetime_reg <= '0';

            END IF;      

          END IF;

        END PROCESS;

        -----------------------------------------------------------------------------

        -- FINE_TIME

        -----------------------------------------------------------------------------

        fine_time_counter_1: fine_time_counter

          GENERIC MAP (

            WAITING_TIME => X"0040",

            FIRST_DIVISION => FIRST_DIVISION)

          PORT MAP (

            clk            => clk,

            rstn           => rstn,

            tick           => tick,

            fsm_transition => fsm_transition,  -- todo

            FT_max         => FT_max,  

            FT_half        => FT_half, 

            FT_wait        => FT_wait, 

            fine_time      => fine_time, 

            fine_time_new  => fine_time_new);

        -----------------------------------------------------------------------------

        -- COARSE_TIME

        -----------------------------------------------------------------------------

        coarse_time_counter_1: coarse_time_counter

          GENERIC MAP(

            NB_SECOND_DESYNC => NB_SECOND_DESYNC )

          PORT MAP (

            clk           => clk,

            rstn          => rstn,

            tick          => tick,

            set_TCU       => set_TCU,         -- todo

        pellion
    
Update APB_TIME_MANAGEMENT :...

              r336
            
            new_TCU       => new_coarsetime_reg,

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
            set_TCU_value => coarsetime_reg,  -- todo

            CT_add1       => CT_add1,         -- todo

            fsm_desync    => fsm_desync,      -- todo

            FT_max        => FT_max,

            coarse_time   => coarse_time,

            coarse_time_new   => coarse_time_new);

        -----------------------------------------------------------------------------

        -- FSM

        -----------------------------------------------------------------------------

        fsm_desync     <= '1' WHEN state = DESYNC     ELSE '0';

        fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';

        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

            state <= DESYNC;

          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

            --CT_add1 <= '0';

            set_TCU <= '0';

            CASE state IS

              WHEN DESYNC =>

                IF tick = '1' THEN

                  state <= SYNC;

                  set_TCU <= new_coarsetime_reg;

                  --IF new_coarsetime = '0' AND FT_half = '1' THEN

                  --  CT_add1 <= '1';

                  --END IF;

                --ELSIF FT_max = '1' THEN

                --  CT_add1 <= '1';

        pellion
    
temp

              r186
            
                END IF;

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
              WHEN TRANSITION => 

                IF tick = '1' THEN

                  state         <= SYNC;

                  set_TCU       <= new_coarsetime_reg;

                  --IF new_coarsetime = '0' THEN

                  --  CT_add1 <= '1';

                  --END IF;

                ELSIF FT_wait = '1' THEN

                  --CT_add1 <= '1';

                  state         <= DESYNC;

                END IF;

              WHEN SYNC =>

                IF tick = '1' THEN

                  set_TCU       <= new_coarsetime_reg;

                  --IF new_coarsetime = '0' THEN

                  --  CT_add1 <= '1';

                  --END IF;

                ELSIF FT_max = '1' THEN

                  state         <= TRANSITION;

                END IF;

              WHEN OTHERS => NULL;

            END CASE;

        pellion
    
temp

              r186
            
          END IF;

        END PROCESS;

        pellion
    
New lfr_time_management (lib/lpp/lfr_time_management)...

              r329
            
        CT_add1 <= '1' WHEN state = SYNC   AND tick = '1' AND new_coarsetime_reg = '0' ELSE

                   '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE

                   '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE

                   '1' WHEN state = TRANSITION AND  tick = '1' AND new_coarsetime_reg = '0' ELSE

                   '1' WHEN state = TRANSITION AND  tick = '0' AND FT_wait = '1' ELSE             

                   '0';

        pellion
    
temp

              r186
            
      END Behavioral;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

paul lfr_time_management added to the repository	r153	----------------------------------------------------------------------------------
		-- Company:
		-- Engineer:
		--
		-- Create Date: 11:14:05 07/02/2012
		-- Design Name:
		-- Module Name: lfr_time_management - Behavioral
		-- Project Name:
		-- Target Devices:
		-- Tool versions:
		-- Description:
		--
		-- Dependencies:
		--
		-- Revision:
		-- Revision 0.01 - File Created
		-- Additional Comments:
		--
		----------------------------------------------------------------------------------
pellion temp	r186	LIBRARY IEEE;
		USE IEEE.STD_LOGIC_1164.ALL;
		USE IEEE.NUMERIC_STD.ALL;
		LIBRARY lpp;
pellion update time_managment	r227	USE lpp.lpp_lfr_time_management.ALL;
paul lfr_time_management added to the repository	r153
pellion temp	r186	ENTITY lfr_time_management IS
		GENERIC (
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	FIRST_DIVISION : INTEGER := 374;
		NB_SECOND_DESYNC : INTEGER := 60);
pellion temp	r186	PORT (
pellion update time_managment	r227	clk : IN STD_LOGIC;
		rstn : IN STD_LOGIC;

pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	tick : IN STD_LOGIC; -- transition signal information

pellion update time_managment	r227	new_coarsetime : IN STD_LOGIC; -- transition signal information
pellion Update APB_TIME_MANAGEMENT :...	r336	coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
pellion update time_managment	r227
		fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		fine_time_new : OUT STD_LOGIC;
		coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		coarse_time_new : OUT STD_LOGIC
pellion temp	r186	);
		END lfr_time_management;
paul lfr_time_management added to the repository	r153
pellion temp	r186	ARCHITECTURE Behavioral OF lfr_time_management IS
paul lfr_time_management added to the repository	r153
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	SIGNAL FT_max : STD_LOGIC;
		SIGNAL FT_half : STD_LOGIC;
		SIGNAL FT_wait : STD_LOGIC;

		TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
		SIGNAL state : state_fsm_time_management;
paul lfr_time_management added to the repository	r153
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	SIGNAL fsm_desync : STD_LOGIC;
		SIGNAL fsm_transition : STD_LOGIC;
pellion WaveFormPicker Update...	r232
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	SIGNAL set_TCU : STD_LOGIC;
		SIGNAL CT_add1 : STD_LOGIC;

		SIGNAL new_coarsetime_reg : STD_LOGIC;

pellion temp	r186	BEGIN
paul lfr_time_management added to the repository	r153
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	-----------------------------------------------------------------------------
		--
		-----------------------------------------------------------------------------
pellion update time_managment	r227	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	new_coarsetime_reg <= '0';
		ELSIF clk'event AND clk = '1' THEN -- rising clock edge
pellion WaveFormPicker Update...	r232	IF new_coarsetime = '1' THEN
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	new_coarsetime_reg <= '1';
		ELSIF tick = '1' THEN
		new_coarsetime_reg <= '0';
		END IF;
		END IF;
		END PROCESS;

		-----------------------------------------------------------------------------
		-- FINE_TIME
		-----------------------------------------------------------------------------
		fine_time_counter_1: fine_time_counter
		GENERIC MAP (
		WAITING_TIME => X"0040",
		FIRST_DIVISION => FIRST_DIVISION)
		PORT MAP (
		clk => clk,
		rstn => rstn,
		tick => tick,
		fsm_transition => fsm_transition, -- todo
		FT_max => FT_max,
		FT_half => FT_half,
		FT_wait => FT_wait,
		fine_time => fine_time,
		fine_time_new => fine_time_new);

		-----------------------------------------------------------------------------
		-- COARSE_TIME
		-----------------------------------------------------------------------------
		coarse_time_counter_1: coarse_time_counter
		GENERIC MAP(
		NB_SECOND_DESYNC => NB_SECOND_DESYNC )
		PORT MAP (
		clk => clk,
		rstn => rstn,
		tick => tick,
		set_TCU => set_TCU, -- todo
pellion Update APB_TIME_MANAGEMENT :...	r336	new_TCU => new_coarsetime_reg,
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	set_TCU_value => coarsetime_reg, -- todo
		CT_add1 => CT_add1, -- todo
		fsm_desync => fsm_desync, -- todo
		FT_max => FT_max,
		coarse_time => coarse_time,
		coarse_time_new => coarse_time_new);

		-----------------------------------------------------------------------------
		-- FSM
		-----------------------------------------------------------------------------
		fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
		fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';

		PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
		state <= DESYNC;
		ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		--CT_add1 <= '0';
		set_TCU <= '0';
		CASE state IS
		WHEN DESYNC =>
		IF tick = '1' THEN
		state <= SYNC;
		set_TCU <= new_coarsetime_reg;
		--IF new_coarsetime = '0' AND FT_half = '1' THEN
		-- CT_add1 <= '1';
		--END IF;
		--ELSIF FT_max = '1' THEN
		-- CT_add1 <= '1';
pellion temp	r186	END IF;
pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329	WHEN TRANSITION =>
		IF tick = '1' THEN
		state <= SYNC;
		set_TCU <= new_coarsetime_reg;
		--IF new_coarsetime = '0' THEN
		-- CT_add1 <= '1';
		--END IF;
		ELSIF FT_wait = '1' THEN
		--CT_add1 <= '1';
		state <= DESYNC;
		END IF;
		WHEN SYNC =>
		IF tick = '1' THEN
		set_TCU <= new_coarsetime_reg;
		--IF new_coarsetime = '0' THEN
		-- CT_add1 <= '1';
		--END IF;
		ELSIF FT_max = '1' THEN
		state <= TRANSITION;
		END IF;
		WHEN OTHERS => NULL;
		END CASE;
pellion temp	r186	END IF;
		END PROCESS;

pellion New lfr_time_management (lib/lpp/lfr_time_management)...	r329
		CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
		'1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
		'1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
		'1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
		'1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
		'0';
pellion temp	r186	END Behavioral;