DacDriver.vhd
72 lines
| 2.9 KiB
| text/x-vhdl
|
VhdlLexer
martin
|
r242 | ------------------------------------------------------------------------------ | |
-- This file is a part of the LPP VHDL IP LIBRARY | |||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
-- | |||
-- This program is free software; you can redistribute it and/or modify | |||
-- it under the terms of the GNU General Public License as published by | |||
-- the Free Software Foundation; either version 3 of the License, or | |||
-- (at your option) any later version. | |||
-- | |||
-- This program is distributed in the hope that it will be useful, | |||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
-- GNU General Public License for more details. | |||
-- | |||
-- You should have received a copy of the GNU General Public License | |||
-- along with this program; if not, write to the Free Software | |||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
------------------------------------------------------------------------------ | |||
-- Author : Martin Morlot | |||
-- Mail : martin.morlot@lpp.polytechnique.fr | |||
------------------------------------------------------------------------------ | |||
library IEEE; | |||
use IEEE.std_logic_1164.all; | |||
use IEEE.numeric_std.all; | |||
martin
|
r274 | library lpp; | |
martin
|
r242 | use lpp.lpp_cna.all; | |
--! Programme du Convertisseur Num�rique/Analogique | |||
entity DacDriver is | |||
martin
|
r274 | --generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz | |
martin
|
r242 | port( | |
clk : in std_logic; --! Horloge du composant | |||
rst : in std_logic; --! Reset general du composant | |||
martin
|
r274 | SysClk : in std_logic; | |
martin
|
r242 | enable : in std_logic; --! Autorise ou non l'utilisation du composant | |
martin
|
r274 | Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits | |
martin
|
r242 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
SCLK : out std_logic; --! Horloge systeme du convertisseur | |||
martin
|
r262 | Readn : out std_logic; | |
martin
|
r274 | -- Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e | |
martin
|
r242 | Data : out std_logic --! Donn�e num�rique s�rialis� | |
); | |||
end entity; | |||
architecture ar_DacDriver of DacDriver is | |||
martin
|
r274 | --signal s_SCLK : std_logic; | |
martin
|
r262 | signal Send : std_logic; | |
martin
|
r274 | signal Sended : std_logic; | |
martin
|
r242 | ||
begin | |||
martin
|
r274 | --SystemCLK : entity work.Clock_Divider | |
-- generic map (cpt_serial) | |||
-- port map (clk,rst,s_SCLK); | |||
martin
|
r242 | ||
Signal_sync : Gene_SYNC | |||
martin
|
r274 | port map (SysClk,rst,clk,enable,Sended,Send,Readn,SYNC); | |
martin
|
r242 | ||
Serial : serialize | |||
martin
|
r274 | port map (clk,rst,clk,Data_IN,Send,Sended,Data); | |
martin
|
r242 | ||
martin
|
r274 | --RenGEN : entity work.ReadFifo_GEN | |
-- port map (clk,rst,Send,Readn); | |||
martin
|
r242 | ||
martin
|
r274 | SCLK <= clk; | |
--Ready <= s_Rdy; | |||
martin
|
r242 | ||
end architecture; |