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Remove arbitration in front of FFT based on Pong Status...
Remove arbitration in front of FFT based on Pong Status Add arbitration in front of FFT based on falling edge of fft_ready and sample_load
pellion - - Load All Authors

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r384:328a814d7018 (MINI-LFR) WFP_MS-0-1-20 JC
r384:328a814d7018 (MINI-LFR) WFP_MS-0-1-20 JC
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lpp_lfr_ms.vhd
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pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
pellion
Dispatch into library the MS files
 r363
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 LIBRARY lpp;
USE lpp.lpp_memory.ALL;
pellion
Dispatch into library the MS files
 r363 USE lpp.iir_filter.ALL;
USE lpp.spectral_matrix_package.ALL;
USE lpp.lpp_dma_pkg.ALL;
USE lpp.lpp_Header.ALL;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 USE lpp.lpp_matrix.ALL;
pellion
Dispatch into library the MS files
 r363 USE lpp.lpp_matrix.ALL;
USE lpp.lpp_lfr_pkg.ALL;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 USE lpp.lpp_fft.ALL;
USE lpp.fft_components.ALL;
ENTITY lpp_lfr_ms IS
GENERIC (
Mem_use : INTEGER := use_RAM
);
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
---------------------------------------------------------------------------
-- DATA INPUT
---------------------------------------------------------------------------
-- TIME
pellion
Dispatch into library the MS files
 r363 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 --
sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
--
sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
--
pellion
Dispatch into library the MS files
 r363 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
---------------------------------------------------------------------------
-- DMA
---------------------------------------------------------------------------
dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
dma_valid : OUT STD_LOGIC;
dma_valid_burst : OUT STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 dma_ren : IN STD_LOGIC;
dma_done : IN STD_LOGIC;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-- Reg out
pellion
Ready for test :)
 r365 ready_matrix_f0 : OUT STD_LOGIC;
ready_matrix_f1 : OUT STD_LOGIC;
ready_matrix_f2 : OUT STD_LOGIC;
error_bad_component_error : OUT STD_LOGIC;
error_buffer_full : OUT STD_LOGIC;
error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
pellion
(LFR-EM) WFP_MS-1-1-16
 r377 --
observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-- Reg In
pellion
Ready for test :)
 r365 status_ready_matrix_f0 : IN STD_LOGIC;
status_ready_matrix_f1 : IN STD_LOGIC;
status_ready_matrix_f2 : IN STD_LOGIC;
pellion
Dispatch into library the MS files
 r363
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 config_active_interruption_onNewMatrix : IN STD_LOGIC;
config_active_interruption_onError : IN STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
pellion
Ready for test :)
 r365 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
pellion
Dispatch into library the MS files
 r363
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 );
END;
ARCHITECTURE Behavioral OF lpp_lfr_ms IS
pellion
Dispatch into library the MS files
 r363
SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 SIGNAL error_wen_f0 : STD_LOGIC;
SIGNAL error_wen_f1 : STD_LOGIC;
SIGNAL error_wen_f2 : STD_LOGIC;
SIGNAL one_sample_f1_full : STD_LOGIC;
SIGNAL one_sample_f1_wen : STD_LOGIC;
SIGNAL one_sample_f2_full : STD_LOGIC;
SIGNAL one_sample_f2_wen : STD_LOGIC;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 -- FSM / SWITCH SELECT CHANNEL
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
SIGNAL state_fsm_select_channel : fsm_select_channel;
SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 -- FSM LOAD FFT
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
SIGNAL state_fsm_load_FFT : fsm_load_FFT;
SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sample_load : STD_LOGIC;
SIGNAL sample_valid : STD_LOGIC;
SIGNAL sample_valid_r : STD_LOGIC;
SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 -- FFT
-----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 SIGNAL fft_read : STD_LOGIC;
SIGNAL fft_pong : STD_LOGIC;
SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL fft_data_valid : STD_LOGIC;
SIGNAL fft_ready : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
pellion
MS + WFP : synthese ok...
 r364 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
pellion
Ready for test :)
 r365 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL current_fifo_empty : STD_LOGIC;
SIGNAL current_fifo_locked : STD_LOGIC;
SIGNAL current_fifo_full : STD_LOGIC;
SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 SIGNAL SM_correlation_start : STD_LOGIC;
SIGNAL SM_correlation_auto : STD_LOGIC;
SIGNAL SM_correlation_done : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
pellion
MS + WFP : synthese ok...
 r364 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
pellion
Ready for test :)
 r365 SIGNAL SM_correlation_begin : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 SIGNAL current_matrix_write : STD_LOGIC;
SIGNAL current_matrix_wait_empty : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 SIGNAL fifo_0_ready : STD_LOGIC;
SIGNAL fifo_1_ready : STD_LOGIC;
SIGNAL fifo_ongoing : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
-----------------------------------------------------------------------------
SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
-----------------------------------------------------------------------------
-- TIME REG & INFOs
-----------------------------------------------------------------------------
SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 --SIGNAL time_update_f0_A : STD_LOGIC;
--SIGNAL time_update_f0_B : STD_LOGIC;
--SIGNAL time_update_f1 : STD_LOGIC;
--SIGNAL time_update_f2 : STD_LOGIC;
pellion
Dispatch into library the MS files
 r363 --
SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
pellion
Ready for test :)
 r365
SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
pellion
Dispatch into library the MS files
 r363 SIGNAL status_component_fifo_0_end : STD_LOGIC;
SIGNAL status_component_fifo_1_end : STD_LOGIC;
-----------------------------------------------------------------------------
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 SIGNAL fft_ongoing_counter : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL fft_ready_reg : STD_LOGIC;
SIGNAL fft_ready_rising_down : STD_LOGIC;
SIGNAL sample_load_reg : STD_LOGIC;
SIGNAL sample_load_rising_down : STD_LOGIC;
pellion
Add an arbitration in front of FFT based on Pong Status
 r380
pellion
Dispatch into library the MS files
 r363 BEGIN
pellion
Ready for test :)
 r365 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 switch_f0_inst : spectral_matrix_switch_f0
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 PORT MAP (
pellion
Dispatch into library the MS files
 r363 clk => clk,
rstn => rstn,
sample_wen => sample_f0_wen,
fifo_A_empty => sample_f0_A_empty,
fifo_A_full => sample_f0_A_full,
fifo_A_wen => sample_f0_A_wen,
fifo_B_empty => sample_f0_B_empty,
fifo_B_full => sample_f0_B_full,
fifo_B_wen => sample_f0_B_wen,
error_wen => error_wen_f0); -- TODO
-----------------------------------------------------------------------------
-- FIFO IN
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 lppFIFOxN_f0_a : lppFIFOxN
GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 16,
Addr_sz => 8,
FifoCnt => 5)
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
pellion
Dispatch into library the MS files
 r363 ReUse => (OTHERS => '0'),
pellion
Ready for test :)
 r365 wen => sample_f0_A_wen,
wdata => sample_f0_wdata,
ren => sample_f0_A_ren,
rdata => sample_f0_A_rdata,
empty => sample_f0_A_empty,
full => sample_f0_A_full,
pellion
Dispatch into library the MS files
 r363 almost_full => OPEN);
lppFIFOxN_f0_b : lppFIFOxN
GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 16,
Addr_sz => 8,
FifoCnt => 5)
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
pellion
Dispatch into library the MS files
 r363 ReUse => (OTHERS => '0'),
pellion
Ready for test :)
 r365 wen => sample_f0_B_wen,
wdata => sample_f0_wdata,
ren => sample_f0_B_ren,
rdata => sample_f0_B_rdata,
empty => sample_f0_B_empty,
full => sample_f0_B_full,
pellion
Dispatch into library the MS files
 r363 almost_full => OPEN);
lppFIFOxN_f1 : lppFIFOxN
GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 16,
Addr_sz => 8,
FifoCnt => 5)
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
pellion
Dispatch into library the MS files
 r363 ReUse => (OTHERS => '0'),
pellion
Ready for test :)
 r365 wen => sample_f1_wen,
wdata => sample_f1_wdata,
ren => sample_f1_ren,
rdata => sample_f1_rdata,
empty => sample_f1_empty,
full => sample_f1_full,
pellion
Dispatch into library the MS files
 r363 almost_full => sample_f1_almost_full);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
PROCESS (clk, rstn)
BEGIN -- PROCESS
IF rstn = '0' THEN -- asynchronous reset (active low)
one_sample_f1_full <= '0';
error_wen_f1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
IF sample_f1_full = "00000" THEN
one_sample_f1_full <= '0';
ELSE
one_sample_f1_full <= '1';
END IF;
error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
END IF;
END PROCESS;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 lppFIFOxN_f2 : lppFIFOxN
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 16,
Addr_sz => 8,
FifoCnt => 5)
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
pellion
Dispatch into library the MS files
 r363 ReUse => (OTHERS => '0'),
pellion
Ready for test :)
 r365 wen => sample_f2_wen,
wdata => sample_f2_wdata,
ren => sample_f2_ren,
rdata => sample_f2_rdata,
empty => sample_f2_empty,
full => sample_f2_full,
pellion
Dispatch into library the MS files
 r363 almost_full => OPEN);
one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
PROCESS (clk, rstn)
BEGIN -- PROCESS
IF rstn = '0' THEN -- asynchronous reset (active low)
one_sample_f2_full <= '0';
error_wen_f2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
IF sample_f2_full = "00000" THEN
one_sample_f2_full <= '0';
ELSE
one_sample_f2_full <= '1';
END IF;
error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- FSM SELECT CHANNEL
-----------------------------------------------------------------------------
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
state_fsm_select_channel <= IDLE;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state_fsm_select_channel IS
WHEN IDLE =>
IF sample_f1_full = "11111" THEN
state_fsm_select_channel <= SWITCH_F1;
ELSIF sample_f1_almost_full = "00000" THEN
IF sample_f0_A_full = "11111" THEN
state_fsm_select_channel <= SWITCH_F0_A;
ELSIF sample_f0_B_full = "11111" THEN
state_fsm_select_channel <= SWITCH_F0_B;
ELSIF sample_f2_full = "11111" THEN
state_fsm_select_channel <= SWITCH_F2;
END IF;
END IF;
WHEN SWITCH_F0_A =>
IF sample_f0_A_empty = "11111" THEN
state_fsm_select_channel <= IDLE;
END IF;
WHEN SWITCH_F0_B =>
IF sample_f0_B_empty = "11111" THEN
state_fsm_select_channel <= IDLE;
END IF;
WHEN SWITCH_F1 =>
IF sample_f1_empty = "11111" THEN
state_fsm_select_channel <= IDLE;
END IF;
WHEN SWITCH_F2 =>
IF sample_f2_empty = "11111" THEN
state_fsm_select_channel <= IDLE;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
pre_state_fsm_select_channel <= IDLE;
ELSIF clk'EVENT AND clk = '1' THEN
pre_state_fsm_select_channel <= state_fsm_select_channel;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- SWITCH SELECT CHANNEL
-----------------------------------------------------------------------------
sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
(OTHERS => '1');
sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
(OTHERS => '0');
sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 -- FSM LOAD FFT
-----------------------------------------------------------------------------
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = "10" ELSE
sample_ren_s WHEN sample_load = '1' ELSE
pellion
Update arbitration in front of FFT based on Pong Status
 r382 (OTHERS => '1');
pellion
Dispatch into library the MS files
 r363
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= IDLE;
pellion
Ready for test :)
 r365 status_MS_input <= (OTHERS => '0');
pellion
Dispatch into library the MS files
 r363 --next_state_fsm_load_FFT <= IDLE;
--sample_valid <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE state_fsm_load_FFT IS
WHEN IDLE =>
--sample_valid <= '0';
sample_ren_s <= (OTHERS => '1');
IF sample_full = "11111" AND sample_load = '1' THEN
state_fsm_load_FFT <= FIFO_1;
pellion
Ready for test :)
 r365 status_MS_input <= status_channel;
pellion
Dispatch into library the MS files
 r363 END IF;
WHEN FIFO_1 =>
sample_ren_s <= "1111" & NOT(sample_load);
IF sample_empty(0) = '1' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= FIFO_2;
END IF;
WHEN FIFO_2 =>
sample_ren_s <= "111" & NOT(sample_load) & '1';
IF sample_empty(1) = '1' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= FIFO_3;
END IF;
WHEN FIFO_3 =>
sample_ren_s <= "11" & NOT(sample_load) & "11";
IF sample_empty(2) = '1' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= FIFO_4;
END IF;
WHEN FIFO_4 =>
sample_ren_s <= '1' & NOT(sample_load) & "111";
IF sample_empty(3) = '1' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= FIFO_5;
END IF;
WHEN FIFO_5 =>
sample_ren_s <= NOT(sample_load) & "1111";
IF sample_empty(4) = '1' THEN
sample_ren_s <= (OTHERS => '1');
state_fsm_load_FFT <= IDLE;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
sample_valid_r <= '0';
next_state_fsm_load_FFT <= IDLE;
ELSIF clk'EVENT AND clk = '1' THEN
next_state_fsm_load_FFT <= state_fsm_load_FFT;
IF sample_ren_s = "11111" THEN
sample_valid_r <= '0';
ELSE
sample_valid_r <= '1';
END IF;
END IF;
END PROCESS;
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 sample_valid <= '0' WHEN fft_ongoing_counter = "10" ELSE sample_valid_r AND sample_load;
pellion
Dispatch into library the MS files
 r363
sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
-----------------------------------------------------------------------------
-- FFT
-----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
MS + WFP : synthese ok...
 r364 clk => clk,
rstn => rstn,
sample_valid => sample_valid,
fft_read => fft_read,
sample_data => sample_data,
sample_load => sample_load,
fft_pong => fft_pong,
fft_data_im => fft_data_im,
fft_data_re => fft_data_re,
fft_data_valid => fft_data_valid,
fft_ready => fft_ready);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 observation_vector_0(11 DOWNTO 0) <= "00" & --11 10
fft_ongoing_counter & --9 8
sample_load_rising_down & --7
fft_ready_rising_down & --6
fft_ready & --5
fft_data_valid & --4
fft_pong & --3
sample_load & --2
fft_read & --1
sample_valid; --0
pellion
(LFR-EM) WFP_MS-1-1-16
 r377
pellion
Add an arbitration in front of FFT based on Pong Status
 r380 -----------------------------------------------------------------------------
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
sample_load_rising_down <= sample_load_reg AND NOT sample_load;
pellion
Add an arbitration in front of FFT based on Pong Status
 r380 PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 fft_ready_reg <= '0';
pellion
Update arbitration in front of FFT based on Pong Status
 r382 sample_load_reg <= '0';
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384
fft_ongoing_counter <= "00";
pellion
Add an arbitration in front of FFT based on Pong Status
 r380 ELSIF clk'event AND clk = '1' THEN
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 fft_ready_reg <= fft_ready;
sample_load_reg <= sample_load;
IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
CASE fft_ongoing_counter IS
WHEN "01" => fft_ongoing_counter <= "00";
WHEN "10" => fft_ongoing_counter <= "01";
WHEN OTHERS => NULL;
END CASE;
ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
CASE fft_ongoing_counter IS
WHEN "00" => fft_ongoing_counter <= "01";
WHEN "01" => fft_ongoing_counter <= "10";
WHEN OTHERS => NULL;
END CASE;
pellion
Add an arbitration in front of FFT based on Pong Status
 r380 END IF;
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384
pellion
Add an arbitration in front of FFT based on Pong Status
 r380 END IF;
END PROCESS;
pellion
(LFR-EM) WFP_MS-1-1-16
 r377
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
state_fsm_load_MS_memory <= IDLE;
pellion
Ready for test :)
 r365 current_fifo_load <= "00001";
ELSIF clk'EVENT AND clk = '1' THEN
pellion
Dispatch into library the MS files
 r363 CASE state_fsm_load_MS_memory IS
WHEN IDLE =>
IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
state_fsm_load_MS_memory <= LOAD_FIFO;
END IF;
WHEN LOAD_FIFO =>
IF current_fifo_full = '1' THEN
state_fsm_load_MS_memory <= TRASH_FFT;
END IF;
WHEN TRASH_FFT =>
IF fft_ready = '0' THEN
state_fsm_load_MS_memory <= IDLE;
pellion
Ready for test :)
 r365 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
END IF;
pellion
Dispatch into library the MS files
 r363 WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
pellion
Ready for test :)
 r365 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
pellion
Dispatch into library the MS files
 r363 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
pellion
Ready for test :)
 r365 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
pellion
Dispatch into library the MS files
 r363 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
pellion
Ready for test :)
 r365 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
AND state_fsm_load_MS_memory = LOAD_FIFO
AND current_fifo_load(I) = '1'
pellion
Dispatch into library the MS files
 r363 ELSE '1';
END GENERATE all_fifo;
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
MEM_IN_SM_wen <= (OTHERS => '1');
pellion
Ready for test :)
 r365 ELSIF clk'EVENT AND clk = '1' THEN
MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
pellion
Dispatch into library the MS files
 r363 END IF;
END PROCESS;
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
(fft_data_im & fft_data_re) &
(fft_data_im & fft_data_re) &
(fft_data_im & fft_data_re) &
(fft_data_im & fft_data_re);
pellion
(LFR-EM) WFP_MS-1-1-16
 r377 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363
-----------------------------------------------------------------------------
Mem_In_SpectralMatrix : lppFIFOxN
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 32, --16,
Addr_sz => 7, --8
FifoCnt => 5)
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
pellion
Dispatch into library the MS files
 r363 rstn => rstn,
ReUse => MEM_IN_SM_ReUse,
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 wen => MEM_IN_SM_wen,
wdata => MEM_IN_SM_wData,
pellion
Ready for test :)
 r365
ren => MEM_IN_SM_ren,
rdata => MEM_IN_SM_rData,
full => MEM_IN_SM_Full,
empty => MEM_IN_SM_Empty,
pellion
MS + WFP : synthese ok...
 r364 almost_full => OPEN);
pellion
Dispatch into library the MS files
 r363
-----------------------------------------------------------------------------
pellion
MINI-LFR 0.1.16
 r379
pellion
Update arbitration in front of FFT based on Pong Status
 r382 observation_vector_1(11 DOWNTO 0) <= '0' &
SM_correlation_done & --4
SM_correlation_auto & --3
SM_correlation_start &
pellion
MINI-LFR 0.1.16
 r379 SM_correlation_start & --7
status_MS_input(1 DOWNTO 0)& --6..5
MEM_IN_SM_locked(4 DOWNTO 0); --4..0
-----------------------------------------------------------------------------
pellion
Ready for test :)
 r365 MS_control_1 : MS_control
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
pellion
Dispatch into library the MS files
 r363
current_status_ms => status_MS_input,
pellion
Ready for test :)
 r365
fifo_in_lock => MEM_IN_SM_locked,
fifo_in_data => MEM_IN_SM_rdata,
fifo_in_full => MEM_IN_SM_Full,
fifo_in_empty => MEM_IN_SM_Empty,
fifo_in_ren => MEM_IN_SM_ren,
fifo_in_reuse => MEM_IN_SM_ReUse,
fifo_out_data => SM_in_data,
fifo_out_ren => SM_in_ren,
fifo_out_empty => SM_in_empty,
pellion
Dispatch into library the MS files
 r363
current_status_component => status_component,
correlation_start => SM_correlation_start,
correlation_auto => SM_correlation_auto,
correlation_done => SM_correlation_done);
pellion
Ready for test :)
 r365 MS_calculation_1 : MS_calculation
pellion
Dispatch into library the MS files
 r363 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
rstn => rstn,
fifo_in_data => SM_in_data,
fifo_in_ren => SM_in_ren,
fifo_in_empty => SM_in_empty,
fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
pellion
Dispatch into library the MS files
 r363 correlation_start => SM_correlation_start,
correlation_auto => SM_correlation_auto,
correlation_begin => SM_correlation_begin,
correlation_done => SM_correlation_done);
pellion
Ready for test :)
 r365
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 PROCESS (clk, rstn)
BEGIN -- PROCESS
IF rstn = '0' THEN -- asynchronous reset (active low)
pellion
Ready for test :)
 r365 current_matrix_write <= '0';
current_matrix_wait_empty <= '1';
status_component_fifo_0 <= (OTHERS => '0');
status_component_fifo_1 <= (OTHERS => '0');
pellion
Dispatch into library the MS files
 r363 status_component_fifo_0_end <= '0';
status_component_fifo_1_end <= '0';
pellion
Ready for test :)
 r365 SM_correlation_done_reg1 <= '0';
SM_correlation_done_reg2 <= '0';
SM_correlation_done_reg3 <= '0';
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
SM_correlation_done_reg1 <= SM_correlation_done;
SM_correlation_done_reg2 <= SM_correlation_done_reg1;
SM_correlation_done_reg3 <= SM_correlation_done_reg2;
pellion
Dispatch into library the MS files
 r363 status_component_fifo_0_end <= '0';
status_component_fifo_1_end <= '0';
IF SM_correlation_begin = '1' THEN
IF current_matrix_write = '0' THEN
pellion
Ready for test :)
 r365 status_component_fifo_0 <= status_component;
pellion
Dispatch into library the MS files
 r363 ELSE
pellion
Ready for test :)
 r365 status_component_fifo_1 <= status_component;
pellion
Dispatch into library the MS files
 r363 END IF;
END IF;
pellion
Ready for test :)
 r365
pellion
MS + WFP : synthese ok...
 r364 IF SM_correlation_done_reg3 = '1' THEN
pellion
Dispatch into library the MS files
 r363 IF current_matrix_write = '0' THEN
pellion
Ready for test :)
 r365 status_component_fifo_0_end <= '1';
pellion
Dispatch into library the MS files
 r363 ELSE
pellion
Ready for test :)
 r365 status_component_fifo_1_end <= '1';
pellion
Dispatch into library the MS files
 r363 END IF;
current_matrix_wait_empty <= '1';
current_matrix_write <= NOT current_matrix_write;
END IF;
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 IF current_matrix_wait_empty <= '1' THEN
IF current_matrix_write = '0' THEN
current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
ELSE
current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
END IF;
END IF;
END IF;
END PROCESS;
pellion
Ready for test :)
 r365 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
'1' WHEN SM_correlation_done_reg1 = '1' ELSE
'1' WHEN SM_correlation_done_reg2 = '1' ELSE
'1' WHEN SM_correlation_done_reg3 = '1' ELSE
pellion
Dispatch into library the MS files
 r363 '1' WHEN current_matrix_wait_empty = '1' ELSE
pellion
Ready for test :)
 r365 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
pellion
Dispatch into library the MS files
 r363 MEM_OUT_SM_Full(1);
MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
pellion
Ready for test :)
 r365 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 Mem_Out_SpectralMatrix : lppFIFOxN
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 GENERIC MAP (
pellion
Ready for test :)
 r365 tech => 0,
Mem_use => Mem_use,
Data_sz => 32,
Addr_sz => 8,
FifoCnt => 2)
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 PORT MAP (
pellion
Ready for test :)
 r365 clk => clk,
pellion
Dispatch into library the MS files
 r363 rstn => rstn,
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 ReUse => (OTHERS => '0'),
pellion
Dispatch into library the MS files
 r363
wen => MEM_OUT_SM_Write,
wdata => MEM_OUT_SM_Data_in,
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 ren => MEM_OUT_SM_Read,
rdata => MEM_OUT_SM_Data_out,
pellion
Ready for test :)
 r365 full => MEM_OUT_SM_Full,
empty => MEM_OUT_SM_Empty,
pellion
Dispatch into library the MS files
 r363 almost_full => OPEN);
pellion
Ready for test :)
 r365
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 -----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 -- MEM_OUT_SM_Read <= "00";
PROCESS (clk, rstn)
pellion
Ready for test :)
 r365 BEGIN
IF rstn = '0' THEN
pellion
Dispatch into library the MS files
 r363 fifo_0_ready <= '0';
fifo_1_ready <= '0';
fifo_ongoing <= '0';
pellion
Ready for test :)
 r365 ELSIF clk'EVENT AND clk = '1' THEN
pellion
Dispatch into library the MS files
 r363 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
pellion
Ready for test :)
 r365 fifo_ongoing <= '1';
pellion
Dispatch into library the MS files
 r363 fifo_0_ready <= '0';
ELSIF status_component_fifo_0_end = '1' THEN
pellion
Ready for test :)
 r365 fifo_0_ready <= '1';
pellion
Dispatch into library the MS files
 r363 END IF;
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
fifo_ongoing <= '0';
fifo_1_ready <= '0';
ELSIF status_component_fifo_1_end = '1' THEN
pellion
Ready for test :)
 r365 fifo_1_ready <= '1';
pellion
Dispatch into library the MS files
 r363 END IF;
END IF;
END PROCESS;
pellion
Ready for test :)
 r365
pellion
Dispatch into library the MS files
 r363 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
'1' WHEN fifo_0_ready = '0' ELSE
FSM_DMA_fifo_ren;
MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
'1' WHEN fifo_1_ready = '0' ELSE
FSM_DMA_fifo_ren;
pellion
Ready for test :)
 r365 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
pellion
Dispatch into library the MS files
 r363 '1';
pellion
Ready for test :)
 r365 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
status_component_fifo_1;
pellion
Dispatch into library the MS files
 r363
pellion
Ready for test :)
 r365 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
MEM_OUT_SM_Data_out(63 DOWNTO 32);
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
-----------------------------------------------------------------------------
pellion
Dispatch into library the MS files
 r363 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 PORT MAP (
pellion
Dispatch into library the MS files
 r363 HCLK => clk,
HRESETn => rstn,
pellion
Ready for test :)
 r365 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
pellion
Dispatch into library the MS files
 r363 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
fifo_data => FSM_DMA_fifo_data,
fifo_empty => FSM_DMA_fifo_empty,
fifo_ren => FSM_DMA_fifo_ren,
dma_addr => dma_addr,
dma_data => dma_data,
dma_valid => dma_valid,
dma_valid_burst => dma_valid_burst,
dma_ren => dma_ren,
dma_done => dma_done,
pellion
Ready for test :)
 r365 ready_matrix_f0 => ready_matrix_f0,
ready_matrix_f1 => ready_matrix_f1,
ready_matrix_f2 => ready_matrix_f2,
error_bad_component_error => error_bad_component_error,
error_buffer_full => error_buffer_full,
debug_reg => debug_reg,
status_ready_matrix_f0 => status_ready_matrix_f0,
status_ready_matrix_f1 => status_ready_matrix_f1,
status_ready_matrix_f2 => status_ready_matrix_f2,
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
config_active_interruption_onError => config_active_interruption_onError,
pellion
Ready for test :)
 r365
addr_matrix_f0 => addr_matrix_f0,
addr_matrix_f1 => addr_matrix_f1,
addr_matrix_f2 => addr_matrix_f2,
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363 matrix_time_f0 => matrix_time_f0,
pellion
Ready for test :)
 r365 matrix_time_f1 => matrix_time_f1,
matrix_time_f2 => matrix_time_f2
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328 );
pellion
Dispatch into library the MS files
 r363 -----------------------------------------------------------------------------
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Dispatch into library the MS files
 r363
-----------------------------------------------------------------------------
-- TIME MANAGMENT
-----------------------------------------------------------------------------
all_time <= coarse_time & fine_time;
--
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
pellion
MINI_LFR-WFP_MS-0.1.5.pdb
 r328
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 all_time_reg: FOR I IN 0 TO 3 GENERATE
pellion
Dispatch into library the MS files
 r363
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
f_empty_reg(I) <= '1';
ELSIF clk'event AND clk = '1' THEN
f_empty_reg(I) <= f_empty(I);
END IF;
END PROCESS;
pellion
Dispatch into library the MS files
 r363
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
pellion
Dispatch into library the MS files
 r363
pellion
Update MS TIME_APB_REG and Fsm_DMA
 r375 s_m_t_m_f0_A : spectral_matrix_time_managment
PORT MAP (
clk => clk,
rstn => rstn,
time_in => all_time,
update_1 => time_update_f(I),
time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
);
END GENERATE all_time_reg;
time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
pellion
Dispatch into library the MS files
 r363
-----------------------------------------------------------------------------
pellion
Remove arbitration in front of FFT based on Pong Status...
 r384 END Behavioral;