##// END OF EJS Templates
Étiquette (MINI-LFR) WFP_MS-0-1-67 ajoutée à la révision 7faec0eb9fbb
Étiquette (MINI-LFR) WFP_MS-0-1-67 ajoutée à la révision 7faec0eb9fbb

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r550:8c147122ecd4 (MINI-LFR) WFP_MS-0-1-64 (LFR-EM) WFP_MS_1-1-64 JC
r559:1388b2e7c598 JC
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Makefile
52 lines | 1.5 KiB | text/x-makefile | MakefileLexer
pellion
TOP_LFR with MS and WFP
r305 VHDLIB=../..
SCRIPTSDIR=$(VHDLIB)/scripts/
GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
TOP=MINI_LFR_top
BOARD=MINI-LFR
include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=high
XSTOPT=
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
pellion
Simu MINI-LFR_WFP_MS ...
r458 VHDLSYNFILES= MINI_LFR_top.vhd
VHDLSIMFILES= testbench.vhd
SIMTOP=testbench
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TOP_LFR with MS and WFP
r305 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
pellion
Add SDC constraint files for MINI-LFR board....
r419 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
pellion
(MINI-LFR) WFP_MS-0.1-51
r516 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
pellion
Add SDC constraint files for MINI-LFR board....
r419 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
pellion
TOP_LFR with MS and WFP
r305 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
TECHLIBS = proasic3e
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
tmtc openchip hynix ihp gleichmann micron usbhc
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
./amba_lcd_16x2_ctrlr \
./general_purpose/lpp_AMR \
./general_purpose/lpp_balise \
./general_purpose/lpp_delay \
./lpp_bootloader \
./lpp_uart \
./lpp_usb \
pellion
Save
r399 ./dsp/lpp_fft_rtax \
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TOP_LFR with MS and WFP
r305 ./lpp_sim/CY7C1061DV33 \
FILESKIP =i2cmst.vhd \
APB_MULTI_DIODE.vhd \
APB_SIMPLE_DIODE.vhd \
Top_MatrixSpec.vhd \
pellion
Simu MINI-LFR_WFP_MS ...
r458 APB_FFT.vhd \
pellion
LFR-em
r460 CoreFFT_simu.vhd \
pellion
LFR-EM and MINI-LFR x.1.64
r550 lpp_lfr_apbreg_simu.vhd
pellion
TOP_LFR with MS and WFP
r305
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
################## project specific targets ##########################