HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lfr_time_management/lfr_time_management.vhd

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WaveFormPicker : Correction de la communication SharedFIFO - LPP_DMA - ajout de registres de tete a la shared FIFO - modification de la generation du read

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             lfr_time_management.vhd
        
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        paul
    
lfr_time_management added to the repository

              r153
            
      ----------------------------------------------------------------------------------

      -- Company: 

      -- Engineer: 

      -- 

      -- Create Date:    11:14:05 07/02/2012 

      -- Design Name: 

      -- Module Name:    lfr_time_management - Behavioral 

      -- Project Name: 

      -- Target Devices: 

      -- Tool versions: 

      -- Description: 

      --

      -- Dependencies: 

      --

      -- Revision: 

      -- Revision 0.01 - File Created

      -- Additional Comments: 

      --

      ----------------------------------------------------------------------------------

        pellion
    
temp

              r186
            
      LIBRARY IEEE;

      USE IEEE.STD_LOGIC_1164.ALL;

      USE IEEE.NUMERIC_STD.ALL;

      LIBRARY lpp;

        pellion
    
update time_managment

              r227
            
      USE lpp.lpp_lfr_time_management.ALL;

        paul
    
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              r153
            
        pellion
    
temp

              r186
            
      ENTITY lfr_time_management IS

        GENERIC (

        pellion
    
update time_managment

              r227
            
          nb_time_code_missing_limit : INTEGER := 60

        pellion
    
temp

              r186
            
          );

        PORT (

        pellion
    
update time_managment

              r227
            
          clk  : IN STD_LOGIC;

          rstn : IN STD_LOGIC;

          new_timecode   : IN STD_LOGIC;      -- transition signal information

          new_coarsetime : IN STD_LOGIC;      -- transition signal information

          coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

          fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

          fine_time_new   : OUT STD_LOGIC;

          coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

          coarse_time_new : OUT STD_LOGIC

        pellion
    
temp

              r186
            
          );

      END lfr_time_management;

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
temp

              r186
            
      ARCHITECTURE Behavioral OF lfr_time_management IS

        paul
    
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        pellion
    
update time_managment

              r227
            
        SIGNAL counter_clear : STD_LOGIC;

        SIGNAL counter_full  : STD_LOGIC;

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
update time_managment

              r227
            
        SIGNAL nb_time_code_missing : INTEGER;

        SIGNAL coarse_time_s        : INTEGER;

        pellion
    
WaveFormPicker Update...

              r232
            
        SIGNAL new_coarsetime_s : STD_LOGIC;

        pellion
    
update time_managment

              r227
            
        pellion
    
temp

              r186
            
      BEGIN

        pellion
    
update time_managment

              r227
            
        lpp_counter_1 : lpp_counter

          GENERIC MAP (

            nb_wait_period => 750,

            nb_bit_of_data => 16)

          PORT MAP (

            clk   => clk,

            rstn  => rstn,

            clear => counter_clear,

            full  => counter_full,

            data  => fine_time,

            new_data => fine_time_new);

        paul
    
lfr_time_management added to the repository

              r153
            
        pellion
    
update time_managment

              r227
            
        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

            nb_time_code_missing <= 0;

            counter_clear        <= '0';

            coarse_time_s <= 0;

            coarse_time_new <= '0';

          ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge

        pellion
    
WaveFormPicker Update...

              r232
            
            IF new_coarsetime = '1' THEN

              new_coarsetime_s <= '1';

            ELSIF new_timecode = '1' THEN

              new_coarsetime_s <= '0';        

            END IF;

        pellion
    
update time_managment

              r227
            
            IF new_timecode = '1' THEN

              coarse_time_new <= '1';

        pellion
    
WaveFormPicker Update...

              r232
            
              IF new_coarsetime_s = '1' THEN

        pellion
    
update time_managment

              r227
            
                coarse_time_s <= to_integer(unsigned(coarsetime_reg));

              ELSE

                coarse_time_s <= coarse_time_s + 1;

              END IF;

              nb_time_code_missing <= 0;

              counter_clear        <= '1';

            ELSE

              coarse_time_new <= '0';

              counter_clear <= '0';

              IF counter_full = '1' THEN

                coarse_time_new <= '1';

                coarse_time_s <= coarse_time_s + 1;

                IF nb_time_code_missing = nb_time_code_missing_limit THEN

                  nb_time_code_missing <= nb_time_code_missing_limit;

        pellion
    
temp

              r186
            
                ELSE

        pellion
    
update time_managment

              r227
            
                  nb_time_code_missing <= nb_time_code_missing + 1;

        pellion
    
temp

              r186
            
                END IF;

        pellion
    
update time_managment

              r227
            
              END IF;

            END IF;

        pellion
    
temp

              r186
            
          END IF;

        END PROCESS;

        pellion
    
update time_managment

              r227
            
        coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));

        coarse_time(31)          <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';

        pellion
    
temp

              r186
            
      END Behavioral;

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paul lfr_time_management added to the repository	r153	----------------------------------------------------------------------------------
		-- Company:
		-- Engineer:
		--
		-- Create Date: 11:14:05 07/02/2012
		-- Design Name:
		-- Module Name: lfr_time_management - Behavioral
		-- Project Name:
		-- Target Devices:
		-- Tool versions:
		-- Description:
		--
		-- Dependencies:
		--
		-- Revision:
		-- Revision 0.01 - File Created
		-- Additional Comments:
		--
		----------------------------------------------------------------------------------
pellion temp	r186	LIBRARY IEEE;
		USE IEEE.STD_LOGIC_1164.ALL;
		USE IEEE.NUMERIC_STD.ALL;
		LIBRARY lpp;
pellion update time_managment	r227	USE lpp.lpp_lfr_time_management.ALL;
paul lfr_time_management added to the repository	r153
pellion temp	r186	ENTITY lfr_time_management IS
		GENERIC (
pellion update time_managment	r227	nb_time_code_missing_limit : INTEGER := 60
pellion temp	r186	);
		PORT (
pellion update time_managment	r227	clk : IN STD_LOGIC;
		rstn : IN STD_LOGIC;

		new_timecode : IN STD_LOGIC; -- transition signal information
		new_coarsetime : IN STD_LOGIC; -- transition signal information
		coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

		fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		fine_time_new : OUT STD_LOGIC;
		coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		coarse_time_new : OUT STD_LOGIC
pellion temp	r186	);
		END lfr_time_management;
paul lfr_time_management added to the repository	r153
pellion temp	r186	ARCHITECTURE Behavioral OF lfr_time_management IS
paul lfr_time_management added to the repository	r153
pellion update time_managment	r227	SIGNAL counter_clear : STD_LOGIC;
		SIGNAL counter_full : STD_LOGIC;
paul lfr_time_management added to the repository	r153
pellion update time_managment	r227	SIGNAL nb_time_code_missing : INTEGER;
		SIGNAL coarse_time_s : INTEGER;
pellion WaveFormPicker Update...	r232
		SIGNAL new_coarsetime_s : STD_LOGIC;
pellion update time_managment	r227
pellion temp	r186	BEGIN
pellion update time_managment	r227
		lpp_counter_1 : lpp_counter
		GENERIC MAP (
		nb_wait_period => 750,
		nb_bit_of_data => 16)
		PORT MAP (
		clk => clk,
		rstn => rstn,
		clear => counter_clear,
		full => counter_full,
		data => fine_time,
		new_data => fine_time_new);
paul lfr_time_management added to the repository	r153
pellion update time_managment	r227	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
		nb_time_code_missing <= 0;
		counter_clear <= '0';
		coarse_time_s <= 0;
		coarse_time_new <= '0';
		ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
pellion WaveFormPicker Update...	r232	IF new_coarsetime = '1' THEN
		new_coarsetime_s <= '1';
		ELSIF new_timecode = '1' THEN
		new_coarsetime_s <= '0';
		END IF;

pellion update time_managment	r227	IF new_timecode = '1' THEN
		coarse_time_new <= '1';
pellion WaveFormPicker Update...	r232	IF new_coarsetime_s = '1' THEN
pellion update time_managment	r227	coarse_time_s <= to_integer(unsigned(coarsetime_reg));
		ELSE
		coarse_time_s <= coarse_time_s + 1;
		END IF;
		nb_time_code_missing <= 0;
		counter_clear <= '1';
		ELSE
		coarse_time_new <= '0';
		counter_clear <= '0';
		IF counter_full = '1' THEN
		coarse_time_new <= '1';
		coarse_time_s <= coarse_time_s + 1;
		IF nb_time_code_missing = nb_time_code_missing_limit THEN
		nb_time_code_missing <= nb_time_code_missing_limit;
pellion temp	r186	ELSE
pellion update time_managment	r227	nb_time_code_missing <= nb_time_code_missing + 1;
pellion temp	r186	END IF;
pellion update time_managment	r227	END IF;
		END IF;
pellion temp	r186	END IF;
		END PROCESS;

pellion update time_managment	r227	coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
		coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';

pellion temp	r186	END Behavioral;