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1 import numpy as np
2
3 from test_fft.register_addresses_fft_test import *
4
5 from __main__ import RMAPPlugin0
6
7 def print_custom( value ):
8 print value
9 RMAPPlugin0.ProcessPendingEvents()
10
11 def read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM ):
12 currentComp_re = np.zeros( nbFrequencyBins )
13 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
14 mask_REN = mask_REN_FIFO_0
15 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
16 mask_REN = mask_REN_FIFO_1
17 else:
18 print_custom( "ERR *** read_SM_Re *** unexpected address_MEM_OUT_SM" )
19 for frequencyBin in range(nbFrequencyBins):
20 # read Re
21 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
22 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
23 currentComp_re[frequencyBin] = val[0]
24 RMAPPlugin0.ProcessPendingEvents()
25 return currentComp_re
26
27 def read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM ):
28 currentComp_re = np.zeros( nbFrequencyBins )
29 currentComp_im = np.zeros( nbFrequencyBins )
30 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
31 mask_REN = mask_REN_FIFO_0
32 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
33 mask_REN = mask_REN_FIFO_1
34 else:
35 print_custom( "ERR *** read_SM_Re_Im *** unexpected address_MEM_OUT_SM" )
36 for frequencyBin in range(nbFrequencyBins):
37 # read Re
38 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
39 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
40 currentComp_re[frequencyBin] = val[0]
41 # read Im
42 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
43 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
44 currentComp_im[frequencyBin] = val[0]
45 RMAPPlugin0.ProcessPendingEvents()
46 return (currentComp_re, currentComp_im)
47
48 def is_MEM_OUT_SM_Empty( ):
49 ret = 0
50 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
51 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
52 if MEM_OUT_SM_Empty == 0x3:
53 ret = 1
54 return ret
55
56 def is_MEM_OUT_SM_Full( ):
57 ret = 0
58 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
59 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
60 if MEM_OUT_SM_Full != 0x0:
61 ret = 1
62 return ret
63
64 def is_MEM_OUT_SM_Full_FIFO_0( ):
65 ret = 0
66 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
67 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000004) >> 2
68 if MEM_OUT_SM_Full == 0x01:
69 ret = 1
70 return ret
71
72 def is_MEM_OUT_SM_Full_FIFO_1( ):
73 ret = 0
74 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
75 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000008) >> 3
76 if MEM_OUT_SM_Full == 0x01:
77 ret = 1
78 return ret
79
80 def wait_for_FIFO_0_Full():
81 counter = 0
82 while ( is_MEM_OUT_SM_Full_FIFO_0() == 0 ):
83 print_custom( "FIFO_0 not full " + str(counter) )
84 counter = counter + 1
85 if counter == 10:
86 break
87
88 def wait_for_FIFO_1_Full():
89 counter = 0
90 while ( is_MEM_OUT_SM_Full_FIFO_1() == 0 ):
91 print_custom( "FIFO_1 not full " + str(counter))
92 counter = counter + 1
93 if counter == 10:
94 break
95
96 def wait_for_FIFO_Full( fifo ):
97 if fifo == 0:
98 wait_for_FIFO_0_Full()
99 elif fifo == 1:
100 wait_for_FIFO_1_Full()
101 else:
102 print_custom( "ERR *** wait_for_FIFO_Full *** unexpted value for parameter [fifo]" )
103
104 def wait_for_FIFO_0_or_1_Full():
105 counter = 0
106 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
107 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
108 while ( MEM_OUT_SM_Full == 0 ):
109 print_custom( "FIFO 0 or 1 not full " + str(counter))
110 counter = counter + 1
111 if counter == 10:
112 break
113 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
114 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
115 RMAPPlugin0.ProcessPendingEvents()
116
117 def print_reg_sm( ):
118 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
119 out_ren = (sm_reg[0] & 0x00000003)
120 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
121 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
122 MEM_OUT_SM_Full_s= (sm_reg[0] & 0x00000040) >> 6
123 print "sm_reg = " + bin( sm_reg[0] & 0x7f ) \
124 + ", out_ren = " + bin( out_ren ) \
125 + ", MEM_OUT_SM_Full = " + bin( MEM_OUT_SM_Full ) \
126 + ", MEM_OUT_SM_Empty = " + bin( MEM_OUT_SM_Empty ) \
127 + ", MEM_OUT_SM_Full_s = " + bin( MEM_OUT_SM_Full_s )
128 RMAPPlugin0.ProcessPendingEvents() No newline at end of file
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@@ -1,416 +1,451
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@@ -1,138 +1,95
1 1 import numpy as np
2 2
3 3 from test_fft.register_addresses_fft_test import *
4 4
5 5 from __main__ import RMAPPlugin0
6 6
7 7 def getWaveFromRecord( cwf, bufferSize, offset, column ):
8 8 yVector = cwf[(0+offset):(bufferSize+offset), column]
9 9 return yVector
10 10
11 11 def sineWave( bufferSize, nbPeriod, amplitude):
12 12 deltaX = nbPeriod * 2 * np.pi / bufferSize
13 13 xVector = np.arange( bufferSize ) * deltaX
14 14 yVector = np.int16( amplitude * np.sin( xVector ) )
15 15 return yVector
16 16
17 17 def continuous( bufferSize, value ):
18 18 tmpVector = np.empty( bufferSize )
19 19 tmpVector.fill( value )
20 20 yVector = np.int16( tmpVector )
21 21 return yVector
22 22
23 23 def step( bufferSize, value ):
24 24 tmpVector = np.zeros( bufferSize )
25 25 for k in range( bufferSize / 2 ):
26 26 tmpVector[ bufferSize / 2 + k ] = value
27 27 yVector = np.int16( tmpVector )
28 28 return yVector
29 29
30 30 def dirac( bufferSize, value ):
31 31 tmpVector = np.zeros( bufferSize )
32 32 tmpVector[0] = value
33 33 yVector = np.int16( tmpVector )
34 34 return yVector
35 35
36 36 def generateDataToWrite( bufferSize, wfrm0, wfrm1 ):
37 37 dataVector = []
38 38 for k in range(bufferSize):
39 39 dataVector.append(
40 40 ( (np.int16(wfrm1[k]) & 0xffff ) << 16)
41 41 | (np.int16(wfrm0[k]) & 0xffff )
42 42 )
43 43 return dataVector
44 44
45 45 def print_reg_fft( ):
46 46 fft_reg = RMAPPlugin0.Read( address_CTRL, 1)
47 47 out_ren = (fft_reg[0] & 0x0000001f)
48 48 out_reuse = (fft_reg[0] & 0x000003e0) >> 5
49 49 out_locked = (fft_reg[0] & 0x00007c00) >> 10
50 50 MEM_IN_SM_Full = (fft_reg[0] & 0x000f8000) >> 15
51 51 MEM_IN_SM_Empty = (fft_reg[0] & 0x01f00000) >> 20
52 52 print "out_ren = " + bin( out_ren ) \
53 53 + ", out_reuse = " + bin( out_reuse ) \
54 54 + ", out_locked = " + bin( out_locked ) \
55 55 + ", MEM_IN_SM_Full = " + bin( MEM_IN_SM_Full ) \
56 56 + ", MEM_IN_SM_Empty = " + bin( MEM_IN_SM_Empty )
57 57 RMAPPlugin0.ProcessPendingEvents()
58 58
59 59 def print_custom( value ):
60 60 print value
61 61 RMAPPlugin0.ProcessPendingEvents()
62 62
63 63 def is_MEM_IN_SM_Emty( ):
64 64 ret = 0
65 65 fft_reg = RMAPPlugin0.Read( address_CTRL, 1)
66 66 MEM_IN_SM_Empty = (fft_reg[0] & 0x01f00000) >> 20
67 67 if MEM_IN_SM_Empty == 0x1f:
68 68 ret = 1
69 69 return ret
70 70
71 def print_reg_sm( ):
72 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
73 out_ren = (sm_reg[0] & 0x00000003)
74 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
75 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
76 print "sm_reg = " + bin( sm_reg[0] & 0x3f ) \
77 + ", out_ren = " + bin( out_ren ) \
78 + ", MEM_OUT_SM_Full = " + bin( MEM_OUT_SM_Full ) \
79 + ", MEM_OUT_SM_Empty = " + bin( MEM_OUT_SM_Empty )
80 RMAPPlugin0.ProcessPendingEvents()
81
82 def is_MEM_OUT_SM_Empty( ):
83 ret = 0
84 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
85 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
86 if MEM_OUT_SM_Empty == 0x3:
87 ret = 1
88 return ret
89
90 def is_MEM_OUT_SM_Full( ):
91 ret = 0
92 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
93 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
94 if MEM_OUT_SM_Full != 0x0:
95 ret = 1
96 return ret
97
98 def is_MEM_OUT_SM_Full_FIFO_0( ):
99 ret = 0
100 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
101 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000004) >> 3
102 if MEM_OUT_SM_Full == 0x01:
103 ret = 1
104 return ret
105
106 def is_MEM_OUT_SM_Full_FIFO_1( ):
107 ret = 0
108 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
109 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000008) >> 3
110 if MEM_OUT_SM_Full == 0x01:
111 ret = 1
112 return ret
113
114 71 def out_locked_AND_out_reuse_AND_out_ren( ):
115 72 # reuse => 0111 1111 1111 1111
116 73 RMAPPlugin0.Write( address_CTRL, [0x00007fff] )
117 74
118 75 def convertToSigned16Bits( dataToConvert ):
119 76 dataInInt16 = np.int16( dataToConvert )
120 77 if dataInInt16 < 32768:
121 78 val = dataInInt16
122 79 else:
123 80 val = dataInInt16 - 65536
124 81 return val
125 82
126 83 def convertVectorToSigned16Bits( bufferSize, dataBuffer ):
127 84 dataBufferConverted = np.zeros( bufferSize )
128 85 for k in range( bufferSize ):
129 86 dataBufferConverted[k] = convertToSigned16Bits( dataBuffer[k] )
130 87 return dataBufferConverted
131 88
132 89 def convertToSigned8Bits( dataToConvert ):
133 90 dataInInt16 = np.int8( dataToConvert )
134 91 if dataInInt16 < 8:
135 92 val = dataInInt16
136 93 else:
137 94 val = dataInInt16 - 16
138 95 return val
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@@ -1,36 +1,39
1 1 # FIFO F0
2 2 address_FIFO_F0_1_0 = 0x80000f00
3 3 address_FIFO_F0_3_2 = 0x80000f04
4 4 address_FIFO_F0_4 = 0x80000f08
5 5 address_FIFO_F0_WEN = 0x80000f0c
6 6 # FIFO F1
7 7 address_FIFO_F1_1_0 = 0x80000f10
8 8 address_FIFO_F1_3_2 = 0x80000f14
9 9 address_FIFO_F1_4 = 0x80000f18
10 10 address_FIFO_F1_WEN = 0x80000f1c
11 11 # FIFO F2
12 12 address_FIFO_F2_1_0 = 0x80000f20
13 13 address_FIFO_F2_3_2 = 0x80000f24
14 14 address_FIFO_F2_4 = 0x80000f28
15 15 address_FIFO_F2_WEN = 0x80000f2c
16 16
17 17 address_MEM_IN_SM_0 = 0x80000f30
18 18 address_MEM_IN_SM_1 = 0x80000f34
19 19 address_MEM_IN_SM_2 = 0x80000f38
20 20 address_MEM_IN_SM_3 = 0x80000f3c
21 21 address_MEM_IN_SM_4 = 0x80000f40
22 22
23 23 address_CTRL = 0x80000f44
24 24
25 25 address_MEM_OUT_SM_0= 0x80000f30
26 26 address_MEM_OUT_SM_1= 0x80000f34
27 27
28 mask_REN_FIFO_0 = 0xfffffffe # 1110
29 mask_REN_FIFO_1 = 0xfffffffd # 1101
30
28 31 address_CTRL_SM = 0x80000f38
29 32
30 33 #
31 34 columnV = 1
32 35 columnE1 = 2
33 36 columnE2 = 3
34 37 columnB1 = 4
35 38 columnB2 = 5
36 39 columnB3 = 6 No newline at end of file
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@@ -1,150 +1,190
1 1 import os
2 2 os.system('clear') # on linux / os x
3 3
4 4 import numpy as np
5 5 import matplotlib.pyplot as plt
6 6
7 7 from test_fft.register_addresses_fft_test import *
8 8 from test_fft.fft_test_functions import *
9 from test_fft.test_sm_functions import *
9 10
10 11 print_custom( '*' )
11 12 print_custom( '*' )
12 13 print_custom( '*' )
13 14 print_custom( '*' )
14 15 print_custom( '*' )
15 16
16 17 ######################
17 18 # GET DATA FROM RECORD
18 19 #storageDirectory = '/home/paul/data/2014_06_24/'
19 20 #day = '2014_6_24-'
20 21 #hour = '9_0_3'
21 22 #suffix = '.data'
22 23
23 24 #typeOfData = '_SBM1_CWF_'
24 25 #cwf_f1 = np.genfromtxt( storageDirectory + day + hour + typeOfData + 'F1' + suffix,
25 26 # skip_header = 1)
26 27 cwf_f1 = np.zeros( 1000 )
27 28
28 29 #################
29 30 # BUILD WAVEFORMS
30 31 nbSamples = 256
31 nbComponentsPerMatrix = 25
32 nbComponentsPerMatrix = 15
32 33 nbFrequencyBins = 128
33 34 #wfrm0 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnV )
34 35 #wfrm1 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnE1 )
35 36 #wfrm2 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnE2 )
36 37 #wfrm3 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnB1 )
37 38 #wfrm4 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnB2 )
38 39 wfrm0 = sineWave( 256, 10, 1000 )
39 wfrm1 = sineWave( 256, 20, 1000 )
40 wfrm2 = sineWave( 256, 30, 1000 )
41 wfrm3 = sineWave( 256, 40, 1000 )
40 wfrm1 = sineWave( 256, 10, 1000 )
41 wfrm2 = sineWave( 256, 20, 1000 )
42 wfrm3 = sineWave( 256, 20, 1000 )
42 43 wfrm4 = sineWave( 256, 50, 1000 )
43 44
44 45 ################
45 46 # BUILD THE DATA
46 47 dataToWrite0 = generateDataToWrite( nbSamples, wfrm0, wfrm1 )
47 48 dataToWrite1 = generateDataToWrite( nbSamples, wfrm2, wfrm3 )
48 49 dataToWrite2 = generateDataToWrite( nbSamples, wfrm4, np.zeros( nbSamples ) )
49 50
50 51 ########################
51 52 # WRITE WAVEFORM IN FIFO
52 53 print_custom( "1) write waveforms in FIFOs: " + str(len(dataToWrite0)) + " samples" )
53 54 print_reg_sm( )
54 55
55 56 for k in range(nbSamples):
56 57 RMAPPlugin0.Write( address_FIFO_F2_1_0, [dataToWrite0[k]] )
57 58 RMAPPlugin0.Write( address_FIFO_F2_3_2, [dataToWrite1[k]] )
58 59 RMAPPlugin0.Write( address_FIFO_F2_4, [dataToWrite2[k]] )
59 60 # write only the FIFO F2
60 61 RMAPPlugin0.Write( address_FIFO_F2_WEN, [0xffffffe0] )
61 62
62 63 print_custom( "1) data written in FIFOs" )
63 64
64 print_reg_sm( )
65
66 # wait for SM_OUT_Full
67 while ( is_MEM_OUT_SM_Full() ) == 0:
68 print_custom( "SM not full" )
69
70 print_reg_sm( )
71
72 65 ################
73 66 # SM FIRST READ
74 67 print_custom( "======= SM FIRST READ" )
75 68
76 69 components = []
77 70
71 wait_for_FIFO_0_or_1_Full()
72
78 73 if is_MEM_OUT_SM_Full_FIFO_0():
79 print_custom( "FIFO_0 is full" )
80 address_MEM_OUT_SM = address_MEM_OUT_SM_0
74 address_MEM_OUT_SM = address_MEM_OUT_SM_1
75 fifo_to_wait_for = 0
81 76 elif is_MEM_OUT_SM_Full_FIFO_1():
82 print_custom( "FIFO_1 is full")
83 address_MEM_OUT_SM = address_MEM_OUT_SM_1
84 else:
85 print_custom( "/!\ no MEM_OUT_SM FIFO full /!\ " )
77 address_MEM_OUT_SM = address_MEM_OUT_SM_0
78 fifo_to_wait_for = 1
86 79
87 80 for component in range(nbComponentsPerMatrix):
88 print_custom( "component = " + str( component ) )
89 currentComp = np.zeros( nbFrequencyBins )
90 for frequencyBin in range(nbFrequencyBins):
91 # read enable => 0000 0000 0000 0000
92 if is_MEM_OUT_SM_Empty( ) == 1:
93 print_custom( "component = " + str( component ) \
94 + " bin = " + str( frequencyBin ) )
95 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
96 RMAPPlugin0.Write( address_CTRL_SM, [0x00000000] )
97 currentComp[frequencyBin] = val[0]
98 RMAPPlugin0.ProcessPendingEvents()
99 components.append( currentComp )
81 print_custom( "==== component = " + str( component )
82 + ", read @" + hex(address_MEM_OUT_SM & 0xffffffff) )
83 print_reg_sm( )
84 currentComp_re = np.zeros( nbFrequencyBins )
85 currentComp_im = np.zeros( nbFrequencyBins )
86 if (component == 0) | (component == 12):
87 wait_for_FIFO_Full( fifo_to_wait_for )
88 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
89 components.append( currentComp_re )
90 elif (component == 5) | (component == 9):
91 wait_for_FIFO_Full( fifo_to_wait_for )
92 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
93 components.append( currentComp_re )
94 elif (component == 1) | (component == 3) | (component == 7):
95 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
96 components.append( currentComp_re )
97 components.append( currentComp_im )
98 wait_for_FIFO_Full( fifo_to_wait_for )
99 elif (component == 2) | (component == 6) | (component == 10):
100 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
101 components.append( currentComp_re )
102 components.append( currentComp_im )
103 wait_for_FIFO_Full( fifo_to_wait_for )
104 elif (component == 4) | (component == 8):
105 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
106 components.append( currentComp_re )
107 components.append( currentComp_im )
108 elif (component == 11) | (component == 13):
109 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
110 components.append( currentComp_re )
111 components.append( currentComp_im )
112 elif (component == 14):
113 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
114 components.append( currentComp_re )
115 else:
116 print_custom( "unexpected value for component" )
117 # change FIFO
118 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
119 address_MEM_OUT_SM = address_MEM_OUT_SM_1
120 fifo_to_wait_for = 0
121 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
122 address_MEM_OUT_SM = address_MEM_OUT_SM_0
123 fifo_to_wait_for = 1
124
125 print_custom( "======= READ COMPLETE" )
126
127 print_reg_sm( )
100 128
101 129 # PLOT SM
102 130
103 131 plt.figure( 1 )
104 132 plt.subplot(231)
105 133 plt.plot(wfrm0, 'b')
106 134 plt.subplot(232)
107 135 plt.plot(wfrm1, 'g')
108 136 plt.plot(wfrm1, '.')
109 137 plt.subplot(233)
110 138 plt.plot(wfrm2, 'r')
111 139 plt.plot(wfrm2, '.')
112 140 plt.subplot(234)
113 141 plt.plot(wfrm3, 'c')
114 142 plt.subplot(235)
115 143 plt.plot(wfrm4, 'm')
116 144
117 145 plt.figure( 2 )
146
118 147 plt.subplot(231)
119 plt.plot(components[0][:])
120 plt.plot(components[1][:])
121 plt.plot(components[2][:])
122 plt.plot(components[3][:])
148 plt.plot(components[0], label='0')
149 plt.plot(components[1], label='1')
150 plt.plot(components[2], label='2')
151 plt.plot(components[3], label='3')
152 plt.legend(loc='upper right')
153
123 154 plt.subplot(232)
124 plt.plot(components[4][:])
125 plt.plot(components[5][:])
126 plt.plot(components[6][:])
127 plt.plot(components[7][:])
155 plt.plot(components[4], label='4')
156 plt.plot(components[5], label='5')
157 plt.plot(components[6], label='6')
158 plt.plot(components[7], label='7')
159 plt.legend(loc='upper right')
160
128 161 plt.subplot(233)
129 plt.plot(components[8][:])
130 plt.plot(components[9][:])
131 plt.plot(components[10][:])
132 plt.plot(components[11][:])
162 plt.plot(components[8], label='8')
163 plt.plot(components[9], label='9')
164 plt.plot(components[10], label='10')
165 plt.plot(components[11], label='11')
166 plt.legend(loc='upper right')
167
133 168 plt.subplot(234)
134 plt.plot(components[12][:])
135 plt.plot(components[13][:])
136 plt.plot(components[14][:])
137 plt.plot(components[15][:])
169 plt.plot(components[12], label='12')
170 plt.plot(components[13], label='13')
171 plt.plot(components[14], label='14')
172 plt.plot(components[15], label='15')
173 plt.legend(loc='upper right')
174
138 175 plt.subplot(235)
139 plt.plot(components[16][:])
140 plt.plot(components[17][:])
141 plt.plot(components[18][:])
142 plt.plot(components[19][:])
176 plt.plot(components[16], label='16')
177 plt.plot(components[17], label='17')
178 plt.plot(components[18], label='18')
179 plt.plot(components[19], label='19')
180 plt.legend(loc='upper right')
181
143 182 plt.subplot(236)
144 plt.plot(components[20][:])
145 plt.plot(components[21][:])
146 plt.plot(components[22][:])
147 plt.plot(components[23][:])
148 plt.plot(components[24][:])
183 plt.plot(components[20], label='20')
184 plt.plot(components[21], label='21')
185 plt.plot(components[22], label='22')
186 plt.plot(components[23], label='23')
187 plt.plot(components[24], label='24')
188 plt.legend(loc='upper right')
149 189
150 190 plt.show() No newline at end of file
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