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FPGA Pinout » History » Version 9

Jean-Christophe Pellion, 27/11/2013 09:58 AM

1 1 Alexis Jeandet
h1. Pinout
2
3 8 Jean-Christophe Pellion
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4 1 Alexis Jeandet
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6
h2. Clocks
7
8
|_.Net      |_.Direction          |_.FPGA pin     |
9
|clk_50     |Input                |F7             |
10
|clk_49     |Input                |K14            |
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h2. Push Buttons
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14
|_.Net      |_.Direction          |_.FPGA pin     |
15
|BP0        |Input                |L1             |
16
|BP1        |Input                |R1             |
17
|BP2/reset  |Input                |T2             |
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19
h2. Leds
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|_.Net      |_.Direction          |_.FPGA pin     |
22
|LED0       |output               |V6             |
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|LED1       |output               |V5             |
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|LED2       |output               |T4             |
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h2. Uarts
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29
|_.Net      |_.Direction          |_.FPGA pin     |
30 2 Alexis Jeandet
|\3=.UART1 |
31 3 Jean-Christophe Pellion
|TXD1       |input                |N17            |
32 2 Alexis Jeandet
|RXD1       |output               |N18            |
33
|nCTS1      |output               |P18            |
34 3 Jean-Christophe Pellion
|nRTS1      |input                |P17            |
35 2 Alexis Jeandet
|\3=.UART2 |
36 4 Jean-Christophe Pellion
|TXD2       |input                |P13            |
37 2 Alexis Jeandet
|RXD2       |output               |T18            |
38
|nCTS2      |output               |V17            |
39 4 Jean-Christophe Pellion
|nDTR2      |input                |L15            |
40
|nRTS2      |input                |M15            |
41 1 Alexis Jeandet
|nDCD2      |output               |N15            |
42 4 Jean-Christophe Pellion
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h2. Ext Connector
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|_.Net      |_.Direction          |_.FPGA pin     |
46
|IO0        |input/output         |E4             |
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|IO1        |input/output         |D3             |
48
|IO2        |input/output         |C2             |
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|IO3        |input/output         |D1             |
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|IO4        |input/output         |F2             |
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|IO5        |input/output         |F3             |
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|IO6        |input/output         |G2             |
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|IO7        |input/output         |H3             |
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|IO8        |input/output         |H4             |
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|IO9        |input/output         |J2             |
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|IO10       |input/output         |P1             |
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|IO11       |input/output         |N1             |
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h2. SpaceWire
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|_.Net      |_.Direction          |_.FPGA pin     |
62
|SPW_EN     |output               |R12            |
63
|\3=.SpaceWire Nominal |
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|SWP_NOM_DIN       |input                |R10            |
65
|SWP_NOM_SIN       |input                |R13            |
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|SWP_NOM_DOUT      |output               |T13            |
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|SWP_NOM_SOUT      |output               |T10            |
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|\3=.SpaceWire Redundant |
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|SWP_RED_DIN       |input                |U18            |
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|SWP_RED_SIN       |input                |T12            |
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|SWP_RED_DOUT      |output               |U10            |
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|SWP_RED_SOUT      |output               |P16            |
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h2. ADC
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|_.Net           |_.Direction          |_.FPGA pin     |
77
|ADC_nCS         |output               |K1             |
78
|ADC_CLK         |output               |T1             |
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|ADC_SDO(0 to 7) |output               |V4  (0)            
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                                        V3                  
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                                        V2                  
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                                        U1
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                                        J1
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                                        H1
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                                        F1
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                                        E1  (7)        |
87 6 Jean-Christophe Pellion
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h2. SRAM
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|_.Net           |_.Direction          |_.FPGA pin     |
91
|SRAM_nWE         |output      | C13  |
92
|SRAM_CE          |output      | J14  |
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|SRAM_nOE         |output      | B9   | 
94
|SRAM_nBE(0 to 3) |output      | H15 (0) 
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                                 C12
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                                 A10
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                                 A9  (3)|
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|SRAM_A(0 to 19)  |output      | C11 (0) 
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                                 C10  
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                                 C9   
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                                 C8   
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                                 C7   
103
                                 A5   
104
                                 A6   
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                                 B6   
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                                 B7   
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                                 A8   
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                                 B10   
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                                 A11   
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                                 B12   
111
                                 A13   
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                                 B13   
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                                 C18   
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                                 C17   
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                                 B18   
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                                 C16   
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                                 D15 (19)| 
118 9 Jean-Christophe Pellion
|SRAM_DQ(0 to 31)  |input/output |D16 (0)   
119 6 Jean-Christophe Pellion
                                 D18   
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                                 E15   
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                                 E18   
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                                 F15   
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                                 F18   
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                                 G15   
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                                 G17   
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                                 K15   
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                                 J18   
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                                 J15
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                                 H18
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                                 C3 
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                                 D4 
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                                 D5 
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                                 C6 
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                                 D14
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                                 A15
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                                 C15
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                                 B17
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                                 A17
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                                 B16
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                                 A16
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                                 A14
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                                 A4   
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                                 A3   
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                                 A2   
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                                 B1   
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                                 C1   
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                                 B2   
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                                 B3   
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                                 C4 (31)|
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