Project

General

Profile

Actions

FPGA Pinout » History » Revision 3

« Previous | Revision 3/9 (diff) | Next »
Jean-Christophe Pellion, 26/11/2013 04:35 PM


Pinout

Clocks

Net Direction FPGA pin
clk_50 Input F7
clk_49 Input K14

Push Buttons

Net Direction FPGA pin
BP0 Input L1
BP1 Input R1
BP2/reset Input T2

Leds

Net Direction FPGA pin
LED0 output V6
LED1 output V5
LED2 output T4

Uarts

Net Direction FPGA pin
UART1
TXD1 input N17
RXD1 output N18
nCTS1 output P18
nRTS1 input P17
UART2
TXD2 input P13
RXD2 output T18
nCTS2 output V17
nDTR2 input L15
nRTS2 input M15
nDCD2 output N15

Updated by Jean-Christophe Pellion almost 11 years ago · 3 revisions

Also available in: PDF HTML TXT