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Alexis Jeandet, 21/11/2013 08:14 PM

Pinout¶

Clocks¶

Net	Direction	FPGA pin
clk_50	Input	F7
clk_49	Input	K14

Push Buttons¶

Net	Direction	FPGA pin
BP0	Input	L1
BP1	Input	R1
BP2/reset	Input	T2

Leds¶

Net	Direction	FPGA pin
LED0	output	V6
LED1	output	V5
LED2	output	T4

Uarts¶

Net	Direction	FPGA pin
UART1
TXD1	output	N17
RXD1	output	N18
nCTS1	output	P18
nRTS1	output	P17
UART2
TXD2	output	P13
RXD2	output	T18
nCTS2	output	V17
nDTR2	output	L15
nRTS2	output	M15
nDCD2	output	N15

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Updated by Alexis Jeandet about 11 years ago · 2 revisions

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