FPGA Pinout » History » Version 6
Jean-Christophe Pellion, 26/11/2013 05:25 PM
| 1 | 1 | Alexis Jeandet | h1. Pinout |
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| 2 | |||
| 3 | |||
| 4 | |||
| 5 | h2. Clocks |
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| 6 | |||
| 7 | |_.Net |_.Direction |_.FPGA pin | |
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| 8 | |clk_50 |Input |F7 | |
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| 9 | |clk_49 |Input |K14 | |
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| 10 | |||
| 11 | h2. Push Buttons |
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| 12 | |||
| 13 | |_.Net |_.Direction |_.FPGA pin | |
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| 14 | |BP0 |Input |L1 | |
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| 15 | |BP1 |Input |R1 | |
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| 16 | |BP2/reset |Input |T2 | |
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| 17 | |||
| 18 | h2. Leds |
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| 19 | |||
| 20 | |_.Net |_.Direction |_.FPGA pin | |
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| 21 | |LED0 |output |V6 | |
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| 22 | |LED1 |output |V5 | |
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| 23 | |LED2 |output |T4 | |
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| 24 | |||
| 25 | |||
| 26 | h2. Uarts |
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| 27 | |||
| 28 | |_.Net |_.Direction |_.FPGA pin | |
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| 29 | 2 | Alexis Jeandet | |\3=.UART1 | |
| 30 | 3 | Jean-Christophe Pellion | |TXD1 |input |N17 | |
| 31 | 2 | Alexis Jeandet | |RXD1 |output |N18 | |
| 32 | |nCTS1 |output |P18 | |
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| 33 | 3 | Jean-Christophe Pellion | |nRTS1 |input |P17 | |
| 34 | 2 | Alexis Jeandet | |\3=.UART2 | |
| 35 | 4 | Jean-Christophe Pellion | |TXD2 |input |P13 | |
| 36 | 2 | Alexis Jeandet | |RXD2 |output |T18 | |
| 37 | |nCTS2 |output |V17 | |
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| 38 | 4 | Jean-Christophe Pellion | |nDTR2 |input |L15 | |
| 39 | |nRTS2 |input |M15 | |
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| 40 | 1 | Alexis Jeandet | |nDCD2 |output |N15 | |
| 41 | 4 | Jean-Christophe Pellion | |
| 42 | h2. Ext Connector |
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| 43 | |||
| 44 | |_.Net |_.Direction |_.FPGA pin | |
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| 45 | |IO0 |input/output |E4 | |
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| 46 | |IO1 |input/output |D3 | |
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| 47 | |IO2 |input/output |C2 | |
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| 48 | |IO3 |input/output |D1 | |
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| 49 | |IO4 |input/output |F2 | |
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| 50 | |IO5 |input/output |F3 | |
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| 51 | |IO6 |input/output |G2 | |
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| 52 | |IO7 |input/output |H3 | |
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| 53 | |IO8 |input/output |H4 | |
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| 54 | |IO9 |input/output |J2 | |
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| 55 | |IO10 |input/output |P1 | |
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| 56 | |IO11 |input/output |N1 | |
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| 57 | |||
| 58 | h2. SpaceWire |
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| 59 | |||
| 60 | |_.Net |_.Direction |_.FPGA pin | |
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| 61 | |SPW_EN |output |R12 | |
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| 62 | |\3=.SpaceWire Nominal | |
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| 63 | |SWP_NOM_DIN |input |R10 | |
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| 64 | |SWP_NOM_SIN |input |R13 | |
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| 65 | |SWP_NOM_DOUT |output |T13 | |
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| 66 | |SWP_NOM_SOUT |output |T10 | |
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| 67 | |\3=.SpaceWire Redundant | |
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| 68 | |SWP_RED_DIN |input |U18 | |
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| 69 | |SWP_RED_SIN |input |T12 | |
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| 70 | |SWP_RED_DOUT |output |U10 | |
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| 71 | |SWP_RED_SOUT |output |P16 | |
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| 72 | |||
| 73 | h2. ADC |
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| 74 | |||
| 75 | 5 | Jean-Christophe Pellion | |_.Net |_.Direction |_.FPGA pin | |
| 76 | |ADC_nCS |output |K1 | |
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| 77 | |ADC_CLK |output |T1 | |
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| 78 | |ADC_SDO(0 to 7) |output |V4 (0) |
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| 79 | V3 |
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| 80 | V2 |
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| 81 | U1 |
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| 82 | J1 |
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| 83 | H1 |
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| 84 | F1 |
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| 85 | E1 (7) | |
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| 86 | 6 | Jean-Christophe Pellion | |
| 87 | h2. SRAM |
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| 88 | |||
| 89 | |_.Net |_.Direction |_.FPGA pin | |
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| 90 | |SRAM_nWE |output | C13 | |
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| 91 | |SRAM_CE |output | J14 | |
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| 92 | |SRAM_nOE |output | B9 | |
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| 93 | |SRAM_nBE(0 to 3) |output | H15 (0) |
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| 94 | C12 |
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| 95 | A10 |
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| 96 | A9 (3)| |
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| 97 | |SRAM_A(0 to 19) |output | C11 (0) |
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| 98 | C10 |
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| 99 | C9 |
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| 100 | C8 |
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| 101 | C7 |
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| 102 | A5 |
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| 103 | A6 |
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| 104 | B6 |
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| 105 | B7 |
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| 106 | A8 |
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| 107 | B10 |
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| 108 | A11 |
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| 109 | B12 |
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| 110 | A13 |
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| 111 | B13 |
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| 112 | C18 |
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| 113 | C17 |
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| 114 | B18 |
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| 115 | C16 |
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| 116 | D15 (19)| |
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| 117 | |SRAM_DQ0 to 31) |input-output |D16 (0) |
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| 118 | D18 |
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| 119 | E15 |
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| 120 | E18 |
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| 121 | F15 |
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| 122 | F18 |
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| 123 | G15 |
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| 124 | G17 |
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| 125 | K15 |
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| 126 | J18 |
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| 127 | J15 |
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| 128 | H18 |
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| 129 | C3 |
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| 130 | D4 |
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| 131 | D5 |
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| 132 | C6 |
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| 133 | D14 |
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| 134 | A15 |
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| 135 | C15 |
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| 136 | B17 |
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| 137 | A17 |
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| 138 | B16 |
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| 139 | A16 |
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| 140 | A14 |
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| 141 | A4 |
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| 142 | A3 |
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| 143 | A2 |
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| 144 | B1 |
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| 145 | C1 |
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| 146 | B2 |
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| 147 | B3 |
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| 148 | C4 (31)| |
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| 149 |