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FPGA Pinout » History » Version 5

Jean-Christophe Pellion, 26/11/2013 05:01 PM

1 1 Alexis Jeandet
h1. Pinout
2
3
4
5
h2. Clocks
6
7
|_.Net      |_.Direction          |_.FPGA pin     |
8
|clk_50     |Input                |F7             |
9
|clk_49     |Input                |K14            |
10
11
h2. Push Buttons
12
13
|_.Net      |_.Direction          |_.FPGA pin     |
14
|BP0        |Input                |L1             |
15
|BP1        |Input                |R1             |
16
|BP2/reset  |Input                |T2             |
17
18
h2. Leds
19
20
|_.Net      |_.Direction          |_.FPGA pin     |
21
|LED0       |output               |V6             |
22
|LED1       |output               |V5             |
23
|LED2       |output               |T4             |
24
25
26
h2. Uarts
27
28
|_.Net      |_.Direction          |_.FPGA pin     |
29 2 Alexis Jeandet
|\3=.UART1 |
30 3 Jean-Christophe Pellion
|TXD1       |input                |N17            |
31 2 Alexis Jeandet
|RXD1       |output               |N18            |
32
|nCTS1      |output               |P18            |
33 3 Jean-Christophe Pellion
|nRTS1      |input                |P17            |
34 2 Alexis Jeandet
|\3=.UART2 |
35 4 Jean-Christophe Pellion
|TXD2       |input                |P13            |
36 2 Alexis Jeandet
|RXD2       |output               |T18            |
37
|nCTS2      |output               |V17            |
38 4 Jean-Christophe Pellion
|nDTR2      |input                |L15            |
39
|nRTS2      |input                |M15            |
40 1 Alexis Jeandet
|nDCD2      |output               |N15            |
41 4 Jean-Christophe Pellion
42
h2. Ext Connector
43
44
|_.Net      |_.Direction          |_.FPGA pin     |
45
|IO0        |input/output         |E4             |
46
|IO1        |input/output         |D3             |
47
|IO2        |input/output         |C2             |
48
|IO3        |input/output         |D1             |
49
|IO4        |input/output         |F2             |
50
|IO5        |input/output         |F3             |
51
|IO6        |input/output         |G2             |
52
|IO7        |input/output         |H3             |
53
|IO8        |input/output         |H4             |
54
|IO9        |input/output         |J2             |
55
|IO10       |input/output         |P1             |
56
|IO11       |input/output         |N1             |
57
58
h2. SpaceWire
59
60
|_.Net      |_.Direction          |_.FPGA pin     |
61
|SPW_EN     |output               |R12            |
62
|\3=.SpaceWire Nominal |
63
|SWP_NOM_DIN       |input                |R10            |
64
|SWP_NOM_SIN       |input                |R13            |
65
|SWP_NOM_DOUT      |output               |T13            |
66
|SWP_NOM_SOUT      |output               |T10            |
67
|\3=.SpaceWire Redundant |
68
|SWP_RED_DIN       |input                |U18            |
69
|SWP_RED_SIN       |input                |T12            |
70
|SWP_RED_DOUT      |output               |U10            |
71
|SWP_RED_SOUT      |output               |P16            |
72
73
h2. ADC
74
75 5 Jean-Christophe Pellion
|_.Net           |_.Direction          |_.FPGA pin     |
76
|ADC_nCS         |output               |K1             |
77
|ADC_CLK         |output               |T1             |
78
|ADC_SDO(0 to 7) |output               |V4  (0)            
79
                                        V3                  
80
                                        V2                  
81
                                        U1
82
                                        J1
83
                                        H1
84
                                        F1
85
                                        E1  (7)        |