FPGA Pinout » History » Version 3
Jean-Christophe Pellion, 26/11/2013 04:35 PM
| 1 | 1 | Alexis Jeandet | h1. Pinout |
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| 2 | |||
| 3 | |||
| 4 | |||
| 5 | h2. Clocks |
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| 6 | |||
| 7 | |_.Net |_.Direction |_.FPGA pin | |
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| 8 | |clk_50 |Input |F7 | |
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| 9 | |clk_49 |Input |K14 | |
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| 10 | |||
| 11 | h2. Push Buttons |
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| 12 | |||
| 13 | |_.Net |_.Direction |_.FPGA pin | |
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| 14 | |BP0 |Input |L1 | |
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| 15 | |BP1 |Input |R1 | |
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| 16 | |BP2/reset |Input |T2 | |
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| 17 | |||
| 18 | h2. Leds |
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| 19 | |||
| 20 | |_.Net |_.Direction |_.FPGA pin | |
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| 21 | |LED0 |output |V6 | |
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| 22 | |LED1 |output |V5 | |
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| 23 | |LED2 |output |T4 | |
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| 24 | |||
| 25 | |||
| 26 | h2. Uarts |
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| 27 | |||
| 28 | |_.Net |_.Direction |_.FPGA pin | |
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| 29 | 2 | Alexis Jeandet | |\3=.UART1 | |
| 30 | 3 | Jean-Christophe Pellion | |TXD1 |input |N17 | |
| 31 | 2 | Alexis Jeandet | |RXD1 |output |N18 | |
| 32 | |nCTS1 |output |P18 | |
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| 33 | 3 | Jean-Christophe Pellion | |nRTS1 |input |P17 | |
| 34 | 2 | Alexis Jeandet | |\3=.UART2 | |
| 35 | 3 | Jean-Christophe Pellion | |TXD2 |input |P13 | |
| 36 | 2 | Alexis Jeandet | |RXD2 |output |T18 | |
| 37 | |nCTS2 |output |V17 | |
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| 38 | 3 | Jean-Christophe Pellion | |nDTR2 |input |L15 | |
| 39 | |nRTS2 |input |M15 | |
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| 40 | 2 | Alexis Jeandet | |nDCD2 |output |N15 | |