Project

General

Profile

Actions
Copy link

Feature #242

closed

créer des fichiers de contrainte d'horloge pour MINI-LFR et EM

Added by paul leroy over 10 years ago. Updated over 10 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Jean-Christophe Pellion
Target version:
-
Start date:
22/09/2014
Due date:
% Done:

100%

Estimated time:

Description

Créer des fichiers de contraintes d'horloge pour éviter la saisie manuelle des contraintes dans l'interface de Designer
clk_50
clk_49
clk_50_s
clk24
clk_25

  • contrainte pour le SpaceWire
Actions
Copy link
 #1

Updated by Jean-Christophe Pellion over 10 years ago

  • Status changed from New to Closed
  • % Done changed from 0 to 100

Add SDC constraint files for MINI-LFR board (r419).
To include those constraints in a project, you must add into design's makefile :
SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc

During the Libero flow,
you must choice the MINI_LFR_synthesis.sdc file for the synthesis step,
and the MINI_LFR_place_and_route.sdc file for the place and route step.

Actions
Copy link

Also available in: Atom PDF