Feature #242
closed
créer des fichiers de contrainte d'horloge pour MINI-LFR et EM
Added by paul leroy about 10 years ago.
Updated about 10 years ago.
Description
Créer des fichiers de contraintes d'horloge pour éviter la saisie manuelle des contraintes dans l'interface de Designer
clk_50
clk_49
clk_50_s
clk24
clk_25
- contrainte pour le SpaceWire
- Status changed from New to Closed
- % Done changed from 0 to 100
Add SDC constraint files for MINI-LFR board (r419).
To include those constraints in a project, you must add into design's makefile :
SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
During the Libero flow,
you must choice the MINI_LFR_synthesis.sdc file for the synthesis step,
and the MINI_LFR_place_and_route.sdc file for the place and route step.
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