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2014-09-25T15:45:28Z
Redmine
VHDLib - Feature #242: créer des fichiers de contrainte d'horloge pour MINI-LFR et EM
https://hephaistos.lpp.polytechnique.fr/redmine/issues/242?journal_id=621
2014-09-25T15:45:28Z
Jean-Christophe Pellion
<ul><li><strong>Status</strong> changed from <i>New</i> to <i>Closed</i></li><li><strong>% Done</strong> changed from <i>0</i> to <i>100</i></li></ul><p>Add SDC constraint files for MINI-LFR board (r419).<br>
To include those constraints in a project, you must add into design's makefile :<br>
SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc<br>
SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc</p>
<p>During the Libero flow,<br>
you must choice the MINI_LFR_synthesis.sdc file for the synthesis step,<br>
and the MINI_LFR_place_and_route.sdc file for the place and route step.</p>