##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » libuc2
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/libuc2

sync
jeandet@pc-de-jeandet3.LAB-LPP.LOCAL -
r23:4b077f397f1c default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -27,10 +27,8 void cpu_init()
27 SCB->VTOR = FLASH_BASE;
27 SCB->VTOR = FLASH_BASE;
28 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
28 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
29 PWR->CR |= PWR_CR_PMODE;
29 PWR->CR |= PWR_CR_PMODE;
30 currentCpuFreq=setCpuFreq(currentCpuFreq);
30 bsp_init();
31 bsp_init();
31 printf("Configure PLL to reach %uHz\n\r",(unsigned int)currentCpuFreq);
32 currentCpuFreq=setCpuFreq(currentCpuFreq);
33 bsp_uart_init();
34 RCC_ClocksTypeDef RCC_ClocksStatus;
32 RCC_ClocksTypeDef RCC_ClocksStatus;
35 RCC_GetClocksFreq(&RCC_ClocksStatus);
33 RCC_GetClocksFreq(&RCC_ClocksStatus);
36 printf("PLL Configured got:\n\r SYS=%uHz\n\r CPU=%uHz\n\r APB1=%uHz\n\r APB2=%uHz\n\r",(unsigned int)RCC_ClocksStatus.SYSCLK_Frequency,(unsigned int)RCC_ClocksStatus.HCLK_Frequency,(unsigned int)RCC_ClocksStatus.PCLK1_Frequency,(unsigned int)RCC_ClocksStatus.PCLK2_Frequency);
34 printf("PLL Configured got:\n\r SYS=%uHz\n\r CPU=%uHz\n\r APB1=%uHz\n\r APB2=%uHz\n\r",(unsigned int)RCC_ClocksStatus.SYSCLK_Frequency,(unsigned int)RCC_ClocksStatus.HCLK_Frequency,(unsigned int)RCC_ClocksStatus.PCLK1_Frequency,(unsigned int)RCC_ClocksStatus.PCLK2_Frequency);
Show file before | Show file after | Hide comments
@@ -64,7 +64,6 i2c_t i2copen(int count)
64 i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL)
64 i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL)
65 {
65 {
66 i2c_t dev = i2copen(count);
66 i2c_t dev = i2copen(count);
67 printf("dev = %d\n\r",dev);
68 if(dev!=-1)
67 if(dev!=-1)
69 {
68 {
70 i2cenable(count);
69 i2cenable(count);
@@ -75,6 +74,8 i2c_t i2copenandconfig(int count,uint32_
75 i2csetpins(dev,SDA,SCL);
74 i2csetpins(dev,SDA,SCL);
76 i2csetspeed(dev,speed);
75 i2csetspeed(dev,speed);
77 i2cenable(count);
76 i2cenable(count);
77 _dev_->CR1|=1<<15;
78 _dev_->CR1&=~(1<<15);
78 }
79 }
79 return dev;
80 return dev;
80 }
81 }
@@ -162,27 +163,34 int i2csetspeed(i2c_t dev,uint32_t speed
162 int32_t APB1Freq=getAPB1Freq()/1000000;
163 int32_t APB1Freq=getAPB1Freq()/1000000;
163 if((APB1Freq>1)&&(APB1Freq<43))
164 if((APB1Freq>1)&&(APB1Freq<43))
164 {
165 {
165 int enabled=((_dev_->CR1&1)==1);
166 i2cdisable(dev);
166 i2cdisable(dev);
167 _dev_->CR2 &= ~(0x1f);
167 uint16_t tmpreg=_dev_->CR2;
168 _dev_->CR2 |= APB1Freq;
168 tmpreg &= ~(0x1f);
169 tmpreg |= APB1Freq;
170 _dev_->CR2=tmpreg;
171 tmpreg=_dev_->TRISE;
172 tmpreg &= ~(0x3f);
173 tmpreg |= APB1Freq+1;
174 _dev_->TRISE = tmpreg;
175 tmpreg=_dev_->CCR;
176 APB1Freq=getAPB1Freq();
169 if(speed>100000) //100kHz= standard mode, 400kHz= fast mode
177 if(speed>100000) //100kHz= standard mode, 400kHz= fast mode
170 {
178 {
171 if(speed<=400000)
179 if(speed<=400000)
172 {
180 {
173 _dev_->CCR |= 1<<15;
181 tmpreg |= 1<<15;
174 _dev_->CCR &= ~(1<<14);
182 tmpreg &= ~(1<<14);
175 _dev_->CCR &= ~(0xfff);
183 tmpreg &= ~(0xfff);
176 _dev_->CCR |= 0xfff & (APB1Freq/(3*speed));
184 tmpreg |= 0xfff & (APB1Freq/(3*speed));
177 }
185 }
178 }
186 }
179 else
187 else
180 {
188 {
181 _dev_->CCR &= ~(1<<15);
189 tmpreg &= ~(1<<15);
182 _dev_->CCR &= ~(0xfff);
190 tmpreg &= ~(0xfff);
183 _dev_->CCR |= 0xfff & (APB1Freq/(2*speed));
191 tmpreg |= 0xfff & (APB1Freq/(2*speed));
184 }
192 }
185 if(enabled)i2cenable(dev);
193 _dev_->CCR=tmpreg;
186 return 0;
194 return 0;
187 }
195 }
188 }
196 }
General Comments 0
You need to be logged in to leave comments. Login now