# HG changeset patch
# User jeandet@pc-de-jeandet3.LAB-LPP.LOCAL
# Date 2012-11-13 08:05:11
# Node ID 4b077f397f1c639895d570e67e88282910ef0f01
# Parent  3d19a50d01c6712f965944a63f21418ddf1c0b44

sync

diff --git a/lib/src/stm32f4/CPU/stm32f4xxxG/cpuinit.c b/lib/src/stm32f4/CPU/stm32f4xxxG/cpuinit.c
--- a/lib/src/stm32f4/CPU/stm32f4xxxG/cpuinit.c
+++ b/lib/src/stm32f4/CPU/stm32f4xxxG/cpuinit.c
@@ -27,10 +27,8 @@ void cpu_init()
     SCB->VTOR = FLASH_BASE;
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
     PWR->CR |= PWR_CR_PMODE;
+    currentCpuFreq=setCpuFreq(currentCpuFreq);
     bsp_init();
-    printf("Configure PLL to reach %uHz\n\r",(unsigned int)currentCpuFreq);
-    currentCpuFreq=setCpuFreq(currentCpuFreq);
-    bsp_uart_init();
     RCC_ClocksTypeDef RCC_ClocksStatus;
     RCC_GetClocksFreq(&RCC_ClocksStatus);
     printf("PLL Configured got:\n\r SYS=%uHz\n\r CPU=%uHz\n\r APB1=%uHz\n\r APB2=%uHz\n\r",(unsigned int)RCC_ClocksStatus.SYSCLK_Frequency,(unsigned int)RCC_ClocksStatus.HCLK_Frequency,(unsigned int)RCC_ClocksStatus.PCLK1_Frequency,(unsigned int)RCC_ClocksStatus.PCLK2_Frequency);
diff --git a/lib/src/stm32f4/I2C/i2c.c b/lib/src/stm32f4/I2C/i2c.c
--- a/lib/src/stm32f4/I2C/i2c.c
+++ b/lib/src/stm32f4/I2C/i2c.c
@@ -64,7 +64,6 @@ i2c_t i2copen(int count)
 i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL)
 {
     i2c_t dev = i2copen(count);
-    printf("dev = %d\n\r",dev);
     if(dev!=-1)
     {
          i2cenable(count);
@@ -75,6 +74,8 @@ i2c_t i2copenandconfig(int count,uint32_
         i2csetpins(dev,SDA,SCL);
         i2csetspeed(dev,speed);
         i2cenable(count);
+        _dev_->CR1|=1<<15;
+        _dev_->CR1&=~(1<<15);
     }
     return dev;
 }
@@ -162,27 +163,34 @@ int i2csetspeed(i2c_t dev,uint32_t speed
         int32_t APB1Freq=getAPB1Freq()/1000000;
         if((APB1Freq>1)&&(APB1Freq<43))
         {
-            int enabled=((_dev_->CR1&1)==1);
             i2cdisable(dev);
-            _dev_->CR2 &= ~(0x1f);
-            _dev_->CR2 |= APB1Freq;
+            uint16_t tmpreg=_dev_->CR2;
+            tmpreg &= ~(0x1f);
+            tmpreg |= APB1Freq;
+            _dev_->CR2=tmpreg;
+            tmpreg=_dev_->TRISE;
+            tmpreg &= ~(0x3f);
+            tmpreg |= APB1Freq+1;
+            _dev_->TRISE = tmpreg;
+            tmpreg=_dev_->CCR;
+            APB1Freq=getAPB1Freq();
             if(speed>100000) //100kHz= standard mode, 400kHz= fast mode
             {
                 if(speed<=400000)
                 {
-                    _dev_->CCR |= 1<<15;
-                    _dev_->CCR &= ~(1<<14);
-                    _dev_->CCR &= ~(0xfff);
-                    _dev_->CCR |= 0xfff & (APB1Freq/(3*speed));
+                    tmpreg |= 1<<15;
+                    tmpreg &= ~(1<<14);
+                    tmpreg &= ~(0xfff);
+                    tmpreg |= 0xfff & (APB1Freq/(3*speed));
                 }
             }
             else
             {
-                    _dev_->CCR &= ~(1<<15);
-                    _dev_->CCR &= ~(0xfff);
-                    _dev_->CCR |= 0xfff & (APB1Freq/(2*speed));
+                    tmpreg &= ~(1<<15);
+                    tmpreg &= ~(0xfff);
+                    tmpreg |= 0xfff & (APB1Freq/(2*speed));
             }
-            if(enabled)i2cenable(dev);
+            _dev_->CCR=tmpreg;
             return 0;
         }
     }