@@ -0,0 +1,87 | |||||
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1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the libuc, microcontroler library | |||
|
3 | -- Copyright (C) 2011, Alexis Jeandet | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@gmail.com | |||
|
21 | -------------------------------------------------------------------------------*/ | |||
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22 | #ifndef CS43L22_H | |||
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23 | #define CS43L22_H | |||
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24 | ||||
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25 | #include <i2c.h> | |||
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26 | #include <uhandle.h> | |||
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27 | ||||
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28 | typedef struct CS43L22_t | |||
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29 | { | |||
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30 | i2c_t i2cdev; | |||
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31 | uint8_t devAddress; | |||
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32 | }CS43L22_t; | |||
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33 | ||||
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34 | extern int cs43l22open(CS43L22_t* dev,uint8_t address); | |||
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35 | ||||
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36 | ||||
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37 | ||||
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38 | ||||
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39 | ||||
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40 | #define CS43L22_MAP_ID 1 | |||
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41 | #define CS43L22_MAP_Power_Ctl_1 2 | |||
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42 | #define CS43L22_MAP_Power_Ctl_2 4 | |||
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43 | #define CS43L22_MAP_Clocking_Ctl 5 | |||
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44 | #define CS43L22_MAP_Interface_Ctl_1 6 | |||
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45 | #define CS43L22_MAP_Interface_Ctl_2 7 | |||
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46 | #define CS43L22_MAP_Passthrough_A 8 | |||
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47 | #define CS43L22_MAP_Passthrough_B 9 | |||
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48 | #define CS43L22_MAP_Analog_ZC_SR 0xA | |||
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49 | #define CS43L22_MAP_Passthrough 0xC | |||
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50 | #define CS43L22_MAP_Playback_Ctl_1 0xD | |||
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51 | #define CS43L22_MAP_Misc_Ctl 0xE | |||
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52 | #define CS43L22_MAP_Playback_Ctl_2 0xF | |||
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53 | #define CS43L22_MAP_Passthrough_A 0x14 | |||
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54 | #define CS43L22_MAP_Passthrough_B 0x15 | |||
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55 | #define CS43L22_MAP_PCMA_Vol 0x1A | |||
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56 | #define CS43L22_MAP_PCMB_Vol 0x1B | |||
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57 | #define CS43L22_MAP_BEEP_Freq 0x1C | |||
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58 | #define CS43L22_MAP_BEEP_Vol 0x1d | |||
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59 | #define CS43L22_MAP_BEEP_Tone_Cfg 0x1E | |||
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60 | #define CS43L22_MAP_Tone_Ctl 0x1F | |||
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61 | #define CS43L22_MAP_Master_A_Vol 0x20 | |||
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62 | #define CS43L22_MAP_Master_B_Vol 0x21 | |||
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63 | #define CS43L22_MAP_Headphone_A_Vol 0x22 | |||
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64 | #define CS43L22_MAP_Headphone_B_Vol 0x23 | |||
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65 | #define CS43L22_MAP_Speaker_A_Vol 0x24 | |||
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66 | #define CS43L22_MAP_Speaker_B_Vol 0x25 | |||
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67 | #define CS43L22_MAP_Channel_Mixer 0x26 | |||
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68 | #define CS43L22_MAP_Limit_Ctl_1 0x27 | |||
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69 | #define CS43L22_MAP_Limit Ctl_2 0x28 | |||
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70 | #define CS43L22_MAP_Limiter_Attack 0x29 | |||
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71 | #define CS43L22_MAP_Overflow_&_Clock_Status 0x2E | |||
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72 | #define CS43L22_MAP_Battery_Compensation 0x2F | |||
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73 | #define CS43L22_MAP_VP_Battery_Level 0x30 | |||
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74 | #define CS43L22_MAP_Speaker_Status 0x31 | |||
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75 | #define CS43L22_MAP_Temperature_Monitor_Control 0x32 | |||
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76 | #define CS43L22_MAP_Thermal_Foldback 0x33 | |||
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77 | #define CS43L22_MAP_Charge_Pump_Frequency 0x34 | |||
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78 | ||||
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79 | ||||
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80 | #endif | |||
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81 | ||||
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82 | ||||
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83 | ||||
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84 | ||||
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85 | ||||
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86 | ||||
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87 |
@@ -0,0 +1,31 | |||||
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1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the libuc, microcontroler library | |||
|
3 | -- Copyright (C) 2012, Alexis Jeandet | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@gmail.com | |||
|
21 | -------------------------------------------------------------------------------*/ | |||
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22 | ||||
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23 | ||||
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24 | ||||
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25 | ||||
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26 | ||||
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27 | ||||
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28 | ||||
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29 | ||||
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30 | ||||
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31 |
@@ -0,0 +1,11 | |||||
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1 | TEMPLATE = lib | |||
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2 | CONFIG += console | |||
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3 | CONFIG -= qt | |||
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4 | TARGET = CS43L22 | |||
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5 | include($$(libuc2)/rules/stm32f4-arm-none-eabi-gcc/rules.pri) | |||
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6 | ||||
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7 | SOURCES += \ | |||
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8 | CS43L22.c | |||
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9 | ||||
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10 | HEADERS += \ | |||
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11 | $$(libuc2)/lib/includes/CS43L22.h |
@@ -0,0 +1,339 | |||||
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1 | /**************************************************************************//** | |||
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2 | * @file core_cm3.c | |||
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3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File | |||
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4 | * @version V2.00 | |||
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5 | * @date 13. September 2010 | |||
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6 | * | |||
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7 | * @note | |||
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8 | * Copyright (C) 2009-2010 ARM Limited. All rights reserved. | |||
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9 | * | |||
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10 | * @par | |||
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11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M | |||
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12 | * processor based microcontrollers. This file can be freely distributed | |||
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13 | * within development tools that are supporting such ARM based processors. | |||
|
14 | * | |||
|
15 | * @par | |||
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16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED | |||
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17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF | |||
|
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. | |||
|
19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR | |||
|
20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. | |||
|
21 | * | |||
|
22 | ******************************************************************************/ | |||
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23 | ||||
|
24 | #include <stdint.h> | |||
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25 | ||||
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26 | /* define compiler specific symbols */ | |||
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27 | #if defined ( __CC_ARM ) | |||
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28 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ | |||
|
29 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ | |||
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30 | ||||
|
31 | #elif defined ( __ICCARM__ ) | |||
|
32 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ | |||
|
33 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ | |||
|
34 | ||||
|
35 | #elif defined ( __GNUC__ ) | |||
|
36 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ | |||
|
37 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ | |||
|
38 | ||||
|
39 | #elif defined ( __TASKING__ ) | |||
|
40 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ | |||
|
41 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ | |||
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42 | ||||
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43 | #endif | |||
|
44 | ||||
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45 | ||||
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46 | /* ########################## Core Instruction Access ######################### */ | |||
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47 | ||||
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48 | #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ | |||
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49 | ||||
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50 | /** \brief Reverse byte order (16 bit) | |||
|
51 | ||||
|
52 | This function reverses the byte order in two unsigned short values. | |||
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53 | ||||
|
54 | \param [in] value Value to reverse | |||
|
55 | \return Reversed value | |||
|
56 | */ | |||
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57 | #if (__ARMCC_VERSION < 400677) | |||
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58 | __ASM uint32_t __REV16(uint32_t value) | |||
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59 | { | |||
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60 | rev16 r0, r0 | |||
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61 | bx lr | |||
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62 | } | |||
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63 | #endif /* __ARMCC_VERSION */ | |||
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64 | ||||
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65 | ||||
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66 | /** \brief Reverse byte order in signed short value | |||
|
67 | ||||
|
68 | This function reverses the byte order in a signed short value with sign extension to integer. | |||
|
69 | ||||
|
70 | \param [in] value Value to reverse | |||
|
71 | \return Reversed value | |||
|
72 | */ | |||
|
73 | #if (__ARMCC_VERSION < 400677) | |||
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74 | __ASM int32_t __REVSH(int32_t value) | |||
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75 | { | |||
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76 | revsh r0, r0 | |||
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77 | bx lr | |||
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78 | } | |||
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79 | #endif /* __ARMCC_VERSION */ | |||
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80 | ||||
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81 | ||||
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82 | /** \brief Remove the exclusive lock | |||
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83 | ||||
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84 | This function removes the exclusive lock which is created by LDREX. | |||
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85 | ||||
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86 | */ | |||
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87 | #if (__ARMCC_VERSION < 400000) | |||
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88 | __ASM void __CLREX(void) | |||
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89 | { | |||
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90 | clrex | |||
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91 | } | |||
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92 | #endif /* __ARMCC_VERSION */ | |||
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93 | ||||
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94 | ||||
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95 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ | |||
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96 | /* obsolete */ | |||
|
97 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ | |||
|
98 | /* obsolete */ | |||
|
99 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ | |||
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100 | /* obsolete */ | |||
|
101 | #endif | |||
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102 | ||||
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103 | ||||
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104 | /* ########################### Core Function Access ########################### */ | |||
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105 | ||||
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106 | #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ | |||
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107 | ||||
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108 | /** \brief Get Control Register | |||
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109 | ||||
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110 | This function returns the content of the Control Register. | |||
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111 | ||||
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112 | \return Control Register value | |||
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113 | */ | |||
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114 | #if (__ARMCC_VERSION < 400000) | |||
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115 | __ASM uint32_t __get_CONTROL(void) | |||
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116 | { | |||
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117 | mrs r0, control | |||
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118 | bx lr | |||
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119 | } | |||
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120 | #endif /* __ARMCC_VERSION */ | |||
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121 | ||||
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122 | ||||
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123 | /** \brief Set Control Register | |||
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124 | ||||
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125 | This function writes the given value to the Control Register. | |||
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126 | ||||
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127 | \param [in] control Control Register value to set | |||
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128 | */ | |||
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129 | #if (__ARMCC_VERSION < 400000) | |||
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130 | __ASM void __set_CONTROL(uint32_t control) | |||
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131 | { | |||
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132 | msr control, r0 | |||
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133 | bx lr | |||
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134 | } | |||
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135 | #endif /* __ARMCC_VERSION */ | |||
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136 | ||||
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137 | ||||
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138 | /** \brief Get ISPR Register | |||
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139 | ||||
|
140 | This function returns the content of the ISPR Register. | |||
|
141 | ||||
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142 | \return ISPR Register value | |||
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143 | */ | |||
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144 | #if (__ARMCC_VERSION < 400000) | |||
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145 | __ASM uint32_t __get_IPSR(void) | |||
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146 | { | |||
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147 | mrs r0, ipsr | |||
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148 | bx lr | |||
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149 | } | |||
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150 | #endif /* __ARMCC_VERSION */ | |||
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151 | ||||
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152 | ||||
|
153 | /** \brief Get APSR Register | |||
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154 | ||||
|
155 | This function returns the content of the APSR Register. | |||
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156 | ||||
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157 | \return APSR Register value | |||
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158 | */ | |||
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159 | #if (__ARMCC_VERSION < 400000) | |||
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160 | __ASM uint32_t __get_APSR(void) | |||
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161 | { | |||
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162 | mrs r0, apsr | |||
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163 | bx lr | |||
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164 | } | |||
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165 | #endif /* __ARMCC_VERSION */ | |||
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166 | ||||
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167 | ||||
|
168 | /** \brief Get xPSR Register | |||
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169 | ||||
|
170 | This function returns the content of the xPSR Register. | |||
|
171 | ||||
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172 | \return xPSR Register value | |||
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173 | */ | |||
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174 | #if (__ARMCC_VERSION < 400000) | |||
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175 | __ASM uint32_t __get_xPSR(void) | |||
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176 | { | |||
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177 | mrs r0, xpsr | |||
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178 | bx lr | |||
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179 | } | |||
|
180 | #endif /* __ARMCC_VERSION */ | |||
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181 | ||||
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182 | ||||
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183 | /** \brief Get Process Stack Pointer | |||
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184 | ||||
|
185 | This function returns the current value of the Process Stack Pointer (PSP). | |||
|
186 | ||||
|
187 | \return PSP Register value | |||
|
188 | */ | |||
|
189 | #if (__ARMCC_VERSION < 400000) | |||
|
190 | __ASM uint32_t __get_PSP(void) | |||
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191 | { | |||
|
192 | mrs r0, psp | |||
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193 | bx lr | |||
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194 | } | |||
|
195 | #endif /* __ARMCC_VERSION */ | |||
|
196 | ||||
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197 | ||||
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198 | /** \brief Set Process Stack Pointer | |||
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199 | ||||
|
200 | This function assigns the given value to the Process Stack Pointer (PSP). | |||
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201 | ||||
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202 | \param [in] topOfProcStack Process Stack Pointer value to set | |||
|
203 | */ | |||
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204 | #if (__ARMCC_VERSION < 400000) | |||
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205 | __ASM void __set_PSP(uint32_t topOfProcStack) | |||
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206 | { | |||
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207 | msr psp, r0 | |||
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208 | bx lr | |||
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209 | } | |||
|
210 | #endif /* __ARMCC_VERSION */ | |||
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211 | ||||
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212 | ||||
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213 | /** \brief Get Main Stack Pointer | |||
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214 | ||||
|
215 | This function returns the current value of the Main Stack Pointer (MSP). | |||
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216 | ||||
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217 | \return MSP Register value | |||
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218 | */ | |||
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219 | #if (__ARMCC_VERSION < 400000) | |||
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220 | __ASM uint32_t __get_MSP(void) | |||
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221 | { | |||
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222 | mrs r0, msp | |||
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223 | bx lr | |||
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224 | } | |||
|
225 | #endif /* __ARMCC_VERSION */ | |||
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226 | ||||
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227 | ||||
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228 | /** \brief Set Main Stack Pointer | |||
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229 | ||||
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230 | This function assigns the given value to the Main Stack Pointer (MSP). | |||
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231 | ||||
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232 | \param [in] topOfMainStack Main Stack Pointer value to set | |||
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233 | */ | |||
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234 | #if (__ARMCC_VERSION < 400000) | |||
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235 | __ASM void __set_MSP(uint32_t mainStackPointer) | |||
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236 | { | |||
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237 | msr msp, r0 | |||
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238 | bx lr | |||
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239 | } | |||
|
240 | #endif /* __ARMCC_VERSION */ | |||
|
241 | ||||
|
242 | ||||
|
243 | /** \brief Get Base Priority | |||
|
244 | ||||
|
245 | This function returns the current value of the Base Priority register. | |||
|
246 | ||||
|
247 | \return Base Priority register value | |||
|
248 | */ | |||
|
249 | #if (__ARMCC_VERSION < 400000) | |||
|
250 | __ASM uint32_t __get_BASEPRI(void) | |||
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251 | { | |||
|
252 | mrs r0, basepri | |||
|
253 | bx lr | |||
|
254 | } | |||
|
255 | #endif /* __ARMCC_VERSION */ | |||
|
256 | ||||
|
257 | ||||
|
258 | /** \brief Set Base Priority | |||
|
259 | ||||
|
260 | This function assigns the given value to the Base Priority register. | |||
|
261 | ||||
|
262 | \param [in] basePri Base Priority value to set | |||
|
263 | */ | |||
|
264 | #if (__ARMCC_VERSION < 400000) | |||
|
265 | __ASM void __set_BASEPRI(uint32_t basePri) | |||
|
266 | { | |||
|
267 | msr basepri, r0 | |||
|
268 | bx lr | |||
|
269 | } | |||
|
270 | #endif /* __ARMCC_VERSION */ | |||
|
271 | ||||
|
272 | /** \brief Get Priority Mask | |||
|
273 | ||||
|
274 | This function returns the current state of the priority mask bit from the Priority Mask Register. | |||
|
275 | ||||
|
276 | \return Priority Mask value | |||
|
277 | */ | |||
|
278 | #if (__ARMCC_VERSION < 400000) | |||
|
279 | __ASM uint32_t __get_PRIMASK(void) | |||
|
280 | { | |||
|
281 | mrs r0, primask | |||
|
282 | bx lr | |||
|
283 | } | |||
|
284 | #endif /* __ARMCC_VERSION */ | |||
|
285 | ||||
|
286 | ||||
|
287 | /** \brief Set Priority Mask | |||
|
288 | ||||
|
289 | This function assigns the given value to the Priority Mask Register. | |||
|
290 | ||||
|
291 | \param [in] priMask Priority Mask | |||
|
292 | */ | |||
|
293 | #if (__ARMCC_VERSION < 400000) | |||
|
294 | __ASM void __set_PRIMASK(uint32_t priMask) | |||
|
295 | { | |||
|
296 | msr primask, r0 | |||
|
297 | bx lr | |||
|
298 | } | |||
|
299 | #endif /* __ARMCC_VERSION */ | |||
|
300 | ||||
|
301 | ||||
|
302 | /** \brief Get Fault Mask | |||
|
303 | ||||
|
304 | This function returns the current value of the Fault Mask Register. | |||
|
305 | ||||
|
306 | \return Fault Mask value | |||
|
307 | */ | |||
|
308 | #if (__ARMCC_VERSION < 400000) | |||
|
309 | __ASM uint32_t __get_FAULTMASK(void) | |||
|
310 | { | |||
|
311 | mrs r0, faultmask | |||
|
312 | bx lr | |||
|
313 | } | |||
|
314 | #endif /* __ARMCC_VERSION */ | |||
|
315 | ||||
|
316 | ||||
|
317 | /** \brief Set the Fault Mask | |||
|
318 | ||||
|
319 | This function assigns the given value to the Fault Mask Register. | |||
|
320 | ||||
|
321 | \param [in] faultMask Fault Mask value value to set | |||
|
322 | */ | |||
|
323 | #if (__ARMCC_VERSION < 400000) | |||
|
324 | __ASM void __set_FAULTMASK(uint32_t faultMask) | |||
|
325 | { | |||
|
326 | msr faultmask, r0 | |||
|
327 | bx lr | |||
|
328 | } | |||
|
329 | #endif /* __ARMCC_VERSION */ | |||
|
330 | ||||
|
331 | ||||
|
332 | ||||
|
333 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ | |||
|
334 | /* obsolete */ | |||
|
335 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ | |||
|
336 | /* obsolete */ | |||
|
337 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ | |||
|
338 | /* obsolete */ | |||
|
339 | #endif |
@@ -0,0 +1,299 | |||||
|
1 | /****************************************************************************//** | |||
|
2 | * @file : startup_LPC17xx.c | |||
|
3 | * @brief : CMSIS Cortex-M3 Core Device Startup File | |||
|
4 | * @version : V1.01 | |||
|
5 | * @date : 4. Feb. 2009 | |||
|
6 | * | |||
|
7 | *---------------------------------------------------------------------------- | |||
|
8 | * | |||
|
9 | * Copyright (C) 2009 ARM Limited. All rights reserved. | |||
|
10 | * | |||
|
11 | * ARM Limited (ARM) is supplying this software for use with Cortex-Mx | |||
|
12 | * processor based microcontrollers. This file can be freely distributed | |||
|
13 | * within development tools that are supporting such ARM based processors. | |||
|
14 | * | |||
|
15 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED | |||
|
16 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF | |||
|
17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. | |||
|
18 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR | |||
|
19 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. | |||
|
20 | * | |||
|
21 | ******************************************************************************/ | |||
|
22 | ||||
|
23 | // Mod by nio for the .fastcode part | |||
|
24 | ||||
|
25 | #include "LPC17xx.h" | |||
|
26 | ||||
|
27 | #define WEAK __attribute__ ((weak)) | |||
|
28 | //***************************************************************************** | |||
|
29 | // | |||
|
30 | // Forward declaration of the default fault handlers. | |||
|
31 | // | |||
|
32 | //***************************************************************************** | |||
|
33 | /* System exception vector handler */ | |||
|
34 | void WEAK Reset_Handler(void); /* Reset Handler */ | |||
|
35 | void WEAK NMI_Handler(void); /* NMI Handler */ | |||
|
36 | void WEAK HardFault_Handler(void); /* Hard Fault Handler */ | |||
|
37 | void WEAK MemManage_Handler(void); /* MPU Fault Handler */ | |||
|
38 | void WEAK BusFault_Handler(void); /* Bus Fault Handler */ | |||
|
39 | void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ | |||
|
40 | void WEAK SVC_Handler(void); /* SVCall Handler */ | |||
|
41 | void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ | |||
|
42 | void WEAK PendSV_Handler(void); /* PendSV Handler */ | |||
|
43 | void WEAK SysTick_Handler(void); /* SysTick Handler */ | |||
|
44 | ||||
|
45 | /* External interrupt vector handler */ | |||
|
46 | void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ | |||
|
47 | void WEAK TIMER0_IRQHandler(void); /* Timer0 */ | |||
|
48 | void WEAK TIMER1_IRQHandler(void); /* Timer1 */ | |||
|
49 | void WEAK TIMER2_IRQHandler(void); /* Timer2 */ | |||
|
50 | void WEAK TIMER3_IRQHandler(void); /* Timer3 */ | |||
|
51 | void WEAK UART0_IRQHandler(void); /* UART0 */ | |||
|
52 | void WEAK UART1_IRQHandler(void); /* UART1 */ | |||
|
53 | void WEAK UART2_IRQHandler(void); /* UART2 */ | |||
|
54 | void WEAK UART3_IRQHandler(void); /* UART3 */ | |||
|
55 | void WEAK PWM1_IRQHandler(void); /* PWM1 */ | |||
|
56 | void WEAK I2C0_IRQHandler(void); /* I2C0 */ | |||
|
57 | void WEAK I2C1_IRQHandler(void); /* I2C1 */ | |||
|
58 | void WEAK I2C2_IRQHandler(void); /* I2C2 */ | |||
|
59 | void WEAK SPI_IRQHandler(void); /* SPI */ | |||
|
60 | void WEAK SSP0_IRQHandler(void); /* SSP0 */ | |||
|
61 | void WEAK SSP1_IRQHandler(void); /* SSP1 */ | |||
|
62 | void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ | |||
|
63 | void WEAK RTC_IRQHandler(void); /* Real Time Clock */ | |||
|
64 | void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ | |||
|
65 | void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ | |||
|
66 | void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ | |||
|
67 | void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ | |||
|
68 | void WEAK ADC_IRQHandler(void); /* A/D Converter */ | |||
|
69 | void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ | |||
|
70 | void WEAK USB_IRQHandler(void); /* USB */ | |||
|
71 | void WEAK CAN_IRQHandler(void); /* CAN */ | |||
|
72 | void WEAK DMA_IRQHandler(void); /* GP DMA */ | |||
|
73 | void WEAK I2S_IRQHandler(void); /* I2S */ | |||
|
74 | void WEAK ENET_IRQHandler(void); /* Ethernet */ | |||
|
75 | void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ | |||
|
76 | void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ | |||
|
77 | void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ | |||
|
78 | void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ | |||
|
79 | ||||
|
80 | ||||
|
81 | ||||
|
82 | /* Exported types --------------------------------------------------------------*/ | |||
|
83 | /* Exported constants --------------------------------------------------------*/ | |||
|
84 | extern unsigned long _etext; | |||
|
85 | extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ | |||
|
86 | extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ | |||
|
87 | extern unsigned long _edata; /* end address for the .data section. defined in linker script */ | |||
|
88 | extern unsigned long _sitestdata; /* start address for the initialization values of the .data section. defined in linker script */ | |||
|
89 | extern unsigned long _stestdata; /* start address for the .data section. defined in linker script */ | |||
|
90 | extern unsigned long _etestdata; | |||
|
91 | ||||
|
92 | ||||
|
93 | extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */ | |||
|
94 | extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */ | |||
|
95 | extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */ | |||
|
96 | ||||
|
97 | extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ | |||
|
98 | extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ | |||
|
99 | ||||
|
100 | extern void _estack; /* init value for the stack pointer. defined in linker script */ | |||
|
101 | ||||
|
102 | extern int bsp_init(); | |||
|
103 | ||||
|
104 | /* Private typedef -----------------------------------------------------------*/ | |||
|
105 | /* function prototypes ------------------------------------------------------*/ | |||
|
106 | void Reset_Handler(void) __attribute__((__interrupt__)); | |||
|
107 | extern int main(void); | |||
|
108 | ||||
|
109 | ||||
|
110 | /****************************************************************************** | |||
|
111 | * | |||
|
112 | * The minimal vector table for a Cortex M3. Note that the proper constructs | |||
|
113 | * must be placed on this to ensure that it ends up at physical address | |||
|
114 | * 0x0000.0000. | |||
|
115 | * | |||
|
116 | ******************************************************************************/ | |||
|
117 | #define STACK_SIZE 0x00000800 /*2kO*/ | |||
|
118 | ||||
|
119 | __attribute__ ((section(".stackarea"))) | |||
|
120 | /* static */ unsigned long pulStack[STACK_SIZE]; | |||
|
121 | ||||
|
122 | ||||
|
123 | __attribute__ ((section(".isr_vector"))) | |||
|
124 | void (* const g_pfnVectors[])(void) = | |||
|
125 | { | |||
|
126 | /* &_estack, // The initial stack pointer */ | |||
|
127 | (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer | |||
|
128 | Reset_Handler, /* Reset Handler */ | |||
|
129 | NMI_Handler, /* NMI Handler */ | |||
|
130 | HardFault_Handler, /* Hard Fault Handler */ | |||
|
131 | MemManage_Handler, /* MPU Fault Handler */ | |||
|
132 | BusFault_Handler, /* Bus Fault Handler */ | |||
|
133 | UsageFault_Handler, /* Usage Fault Handler */ | |||
|
134 | 0, /* Reserved */ | |||
|
135 | 0, /* Reserved */ | |||
|
136 | 0, /* Reserved */ | |||
|
137 | 0, /* Reserved */ | |||
|
138 | SVC_Handler, /* SVCall Handler */ | |||
|
139 | DebugMon_Handler, /* Debug Monitor Handler */ | |||
|
140 | 0, /* Reserved */ | |||
|
141 | PendSV_Handler, /* PendSV Handler */ | |||
|
142 | SysTick_Handler, /* SysTick Handler */ | |||
|
143 | ||||
|
144 | // External Interrupts | |||
|
145 | WDT_IRQHandler, /* Watchdog Timer */ | |||
|
146 | TIMER0_IRQHandler, /* Timer0 */ | |||
|
147 | TIMER1_IRQHandler, /* Timer1 */ | |||
|
148 | TIMER2_IRQHandler, /* Timer2 */ | |||
|
149 | TIMER3_IRQHandler, /* Timer3 */ | |||
|
150 | UART0_IRQHandler, /* UART0 */ | |||
|
151 | UART1_IRQHandler, /* UART1 */ | |||
|
152 | UART2_IRQHandler, /* UART2 */ | |||
|
153 | UART3_IRQHandler, /* UART3 */ | |||
|
154 | PWM1_IRQHandler, /* PWM1 */ | |||
|
155 | I2C0_IRQHandler, /* I2C0 */ | |||
|
156 | I2C1_IRQHandler, /* I2C1 */ | |||
|
157 | I2C2_IRQHandler, /* I2C2 */ | |||
|
158 | SPI_IRQHandler, /* SPI */ | |||
|
159 | SSP0_IRQHandler, /* SSP0 */ | |||
|
160 | SSP1_IRQHandler, /* SSP1 */ | |||
|
161 | PLL0_IRQHandler, /* PLL0 (Main PLL) */ | |||
|
162 | RTC_IRQHandler, /* Real Time Clock */ | |||
|
163 | EINT0_IRQHandler, /* External Interrupt 0 */ | |||
|
164 | EINT1_IRQHandler, /* External Interrupt 1 */ | |||
|
165 | EINT2_IRQHandler, /* External Interrupt 2 */ | |||
|
166 | EINT3_IRQHandler, /* External Interrupt 3 */ | |||
|
167 | ADC_IRQHandler, /* A/D Converter */ | |||
|
168 | BOD_IRQHandler, /* Brown Out Detect */ | |||
|
169 | USB_IRQHandler, /* USB */ | |||
|
170 | CAN_IRQHandler, /* CAN */ | |||
|
171 | DMA_IRQHandler, /* GP DMA */ | |||
|
172 | I2S_IRQHandler, /* I2S */ | |||
|
173 | ENET_IRQHandler, /* Ethernet */ | |||
|
174 | RIT_IRQHandler, /* Repetitive Interrupt Timer */ | |||
|
175 | MCPWM_IRQHandler, /* Motor Control PWM */ | |||
|
176 | QEI_IRQHandler, /* Quadrature Encoder Interface */ | |||
|
177 | PLL1_IRQHandler, /* PLL1 (USB PLL) */ | |||
|
178 | }; | |||
|
179 | ||||
|
180 | /******************************************************************************* | |||
|
181 | * Function Name : Reset_Handler | |||
|
182 | * Description : This is the code that gets called when the processor first starts execution | |||
|
183 | * following a reset event. Only the absolutely necessary set is performed, | |||
|
184 | * after which the application supplied main() routine is called. | |||
|
185 | * Input : | |||
|
186 | * Output : | |||
|
187 | * Return : | |||
|
188 | *******************************************************************************/ | |||
|
189 | void Reset_Handler(void) | |||
|
190 | { | |||
|
191 | SystemInit(); | |||
|
192 | ||||
|
193 | unsigned long *pulDest; | |||
|
194 | unsigned long *pulSrc; | |||
|
195 | ||||
|
196 | // | |||
|
197 | // Copy the data segment initializers from flash to SRAM in ROM mode | |||
|
198 | // | |||
|
199 | ||||
|
200 | if (&_sidata != &_sdata) { // only if needed | |||
|
201 | pulSrc = &_sidata; | |||
|
202 | for(pulDest = &_sdata; pulDest < &_edata; ) { | |||
|
203 | *(pulDest++) = *(pulSrc++); | |||
|
204 | } | |||
|
205 | } | |||
|
206 | if (&_sitestdata != &_stestdata) { // only if needed | |||
|
207 | pulSrc = &_sitestdata; | |||
|
208 | for(pulDest = &_stestdata; pulDest < &_etestdata; ) { | |||
|
209 | *(pulDest++) = *(pulSrc++); | |||
|
210 | } | |||
|
211 | } | |||
|
212 | ||||
|
213 | // Copy the .fastcode code from ROM to SRAM | |||
|
214 | ||||
|
215 | if (&_sifastcode != &_sfastcode) { // only if needed | |||
|
216 | pulSrc = &_sifastcode; | |||
|
217 | for(pulDest = &_sfastcode; pulDest < &_efastcode; ) { | |||
|
218 | *(pulDest++) = *(pulSrc++); | |||
|
219 | } | |||
|
220 | } | |||
|
221 | ||||
|
222 | // | |||
|
223 | // Zero fill the bss segment. | |||
|
224 | // | |||
|
225 | for(pulDest = &_sbss; pulDest < &_ebss; ) | |||
|
226 | { | |||
|
227 | *(pulDest++) = 0; | |||
|
228 | } | |||
|
229 | ||||
|
230 | // | |||
|
231 | // Call the application's entry point. | |||
|
232 | // | |||
|
233 | bsp_init(); | |||
|
234 | main(); | |||
|
235 | } | |||
|
236 | ||||
|
237 | //***************************************************************************** | |||
|
238 | // | |||
|
239 | // Provide weak aliases for each Exception handler to the Default_Handler. | |||
|
240 | // As they are weak aliases, any function with the same name will override | |||
|
241 | // this definition. | |||
|
242 | // | |||
|
243 | //***************************************************************************** | |||
|
244 | #pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ | |||
|
245 | #pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ | |||
|
246 | #pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ | |||
|
247 | #pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ | |||
|
248 | #pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ | |||
|
249 | #pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ | |||
|
250 | #pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ | |||
|
251 | ||||
|
252 | /* External interrupt vector handler */ | |||
|
253 | #pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */ | |||
|
254 | #pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */ | |||
|
255 | #pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */ | |||
|
256 | #pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */ | |||
|
257 | #pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */ | |||
|
258 | #pragma weak UART0_IRQHandler = Default_Handler /* UART0 */ | |||
|
259 | #pragma weak UART1_IRQHandler = Default_Handler /* UART1 */ | |||
|
260 | #pragma weak UART2_IRQHandler = Default_Handler /* UART2 */ | |||
|
261 | #pragma weak UART3_IRQHandler = Default_Handler /* UART3 */ | |||
|
262 | #pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */ | |||
|
263 | #pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */ | |||
|
264 | #pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */ | |||
|
265 | #pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */ | |||
|
266 | #pragma weak SPI_IRQHandler = Default_Handler /* SPI */ | |||
|
267 | #pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */ | |||
|
268 | #pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */ | |||
|
269 | #pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */ | |||
|
270 | #pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */ | |||
|
271 | #pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */ | |||
|
272 | #pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */ | |||
|
273 | #pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */ | |||
|
274 | #pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */ | |||
|
275 | #pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */ | |||
|
276 | #pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */ | |||
|
277 | #pragma weak USB_IRQHandler = Default_Handler /* USB */ | |||
|
278 | #pragma weak CAN_IRQHandler = Default_Handler /* CAN */ | |||
|
279 | #pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */ | |||
|
280 | #pragma weak I2S_IRQHandler = Default_Handler /* I2S */ | |||
|
281 | #pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */ | |||
|
282 | #pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */ | |||
|
283 | #pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */ | |||
|
284 | #pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */ | |||
|
285 | #pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */ | |||
|
286 | ||||
|
287 | //***************************************************************************** | |||
|
288 | // | |||
|
289 | // This is the code that gets called when the processor receives an unexpected | |||
|
290 | // interrupt. This simply enters an infinite loop, preserving the system state | |||
|
291 | // for examination by a debugger. | |||
|
292 | // | |||
|
293 | //***************************************************************************** | |||
|
294 | void Default_Handler(void) { | |||
|
295 | // Go into an infinite loop. | |||
|
296 | // | |||
|
297 | while (1) { | |||
|
298 | } | |||
|
299 | } |
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1 | /**************************************************************************//** | |||
|
2 | * @file system_LPC17xx.c | |||
|
3 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File | |||
|
4 | * for the NXP LPC17xx Device Series | |||
|
5 | * @version V1.08 | |||
|
6 | * @date 12. May 2010 | |||
|
7 | * | |||
|
8 | * @note | |||
|
9 | * Copyright (C) 2009 ARM Limited. All rights reserved. | |||
|
10 | * | |||
|
11 | * @par | |||
|
12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M | |||
|
13 | * processor based microcontrollers. This file can be freely distributed | |||
|
14 | * within development tools that are supporting such ARM based processors. | |||
|
15 | * | |||
|
16 | * @par | |||
|
17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED | |||
|
18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF | |||
|
19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. | |||
|
20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR | |||
|
21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. | |||
|
22 | * | |||
|
23 | ******************************************************************************/ | |||
|
24 | ||||
|
25 | ||||
|
26 | #include <stdint.h> | |||
|
27 | #include "LPC17xx.h" | |||
|
28 | ||||
|
29 | /* | |||
|
30 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ | |||
|
31 | */ | |||
|
32 | ||||
|
33 | /*--------------------- Clock Configuration ---------------------------------- | |||
|
34 | // | |||
|
35 | // <e> Clock Configuration | |||
|
36 | // <h> System Controls and Status Register (SCS) | |||
|
37 | // <o1.4> OSCRANGE: Main Oscillator Range Select | |||
|
38 | // <0=> 1 MHz to 20 MHz | |||
|
39 | // <1=> 15 MHz to 24 MHz | |||
|
40 | // <e1.5> OSCEN: Main Oscillator Enable | |||
|
41 | // </e> | |||
|
42 | // </h> | |||
|
43 | // | |||
|
44 | // <h> Clock Source Select Register (CLKSRCSEL) | |||
|
45 | // <o2.0..1> CLKSRC: PLL Clock Source Selection | |||
|
46 | // <0=> Internal RC oscillator | |||
|
47 | // <1=> Main oscillator | |||
|
48 | // <2=> RTC oscillator | |||
|
49 | // </h> | |||
|
50 | // | |||
|
51 | // <e3> PLL0 Configuration (Main PLL) | |||
|
52 | // <h> PLL0 Configuration Register (PLL0CFG) | |||
|
53 | // <i> F_cco0 = (2 * M * F_in) / N | |||
|
54 | // <i> F_in must be in the range of 32 kHz to 50 MHz | |||
|
55 | // <i> F_cco0 must be in the range of 275 MHz to 550 MHz | |||
|
56 | // <o4.0..14> MSEL: PLL Multiplier Selection | |||
|
57 | // <6-32768><#-1> | |||
|
58 | // <i> M Value | |||
|
59 | // <o4.16..23> NSEL: PLL Divider Selection | |||
|
60 | // <1-256><#-1> | |||
|
61 | // <i> N Value | |||
|
62 | // </h> | |||
|
63 | // </e> | |||
|
64 | // | |||
|
65 | // <e5> PLL1 Configuration (USB PLL) | |||
|
66 | // <h> PLL1 Configuration Register (PLL1CFG) | |||
|
67 | // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) | |||
|
68 | // <i> F_cco1 = F_osc * M * 2 * P | |||
|
69 | // <i> F_cco1 must be in the range of 156 MHz to 320 MHz | |||
|
70 | // <o6.0..4> MSEL: PLL Multiplier Selection | |||
|
71 | // <1-32><#-1> | |||
|
72 | // <i> M Value (for USB maximum value is 4) | |||
|
73 | // <o6.5..6> PSEL: PLL Divider Selection | |||
|
74 | // <0=> 1 | |||
|
75 | // <1=> 2 | |||
|
76 | // <2=> 4 | |||
|
77 | // <3=> 8 | |||
|
78 | // <i> P Value | |||
|
79 | // </h> | |||
|
80 | // </e> | |||
|
81 | // | |||
|
82 | // <h> CPU Clock Configuration Register (CCLKCFG) | |||
|
83 | // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 | |||
|
84 | // <1-256><#-1> | |||
|
85 | // </h> | |||
|
86 | // | |||
|
87 | // <h> USB Clock Configuration Register (USBCLKCFG) | |||
|
88 | // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 | |||
|
89 | // <0-15> | |||
|
90 | // <i> Divide is USBSEL + 1 | |||
|
91 | // </h> | |||
|
92 | // | |||
|
93 | // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) | |||
|
94 | // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT | |||
|
95 | // <0=> Pclk = Cclk / 4 | |||
|
96 | // <1=> Pclk = Cclk | |||
|
97 | // <2=> Pclk = Cclk / 2 | |||
|
98 | // <3=> Pclk = Hclk / 8 | |||
|
99 | // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 | |||
|
100 | // <0=> Pclk = Cclk / 4 | |||
|
101 | // <1=> Pclk = Cclk | |||
|
102 | // <2=> Pclk = Cclk / 2 | |||
|
103 | // <3=> Pclk = Hclk / 8 | |||
|
104 | // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 | |||
|
105 | // <0=> Pclk = Cclk / 4 | |||
|
106 | // <1=> Pclk = Cclk | |||
|
107 | // <2=> Pclk = Cclk / 2 | |||
|
108 | // <3=> Pclk = Hclk / 8 | |||
|
109 | // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 | |||
|
110 | // <0=> Pclk = Cclk / 4 | |||
|
111 | // <1=> Pclk = Cclk | |||
|
112 | // <2=> Pclk = Cclk / 2 | |||
|
113 | // <3=> Pclk = Hclk / 8 | |||
|
114 | // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 | |||
|
115 | // <0=> Pclk = Cclk / 4 | |||
|
116 | // <1=> Pclk = Cclk | |||
|
117 | // <2=> Pclk = Cclk / 2 | |||
|
118 | // <3=> Pclk = Hclk / 8 | |||
|
119 | // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 | |||
|
120 | // <0=> Pclk = Cclk / 4 | |||
|
121 | // <1=> Pclk = Cclk | |||
|
122 | // <2=> Pclk = Cclk / 2 | |||
|
123 | // <3=> Pclk = Hclk / 8 | |||
|
124 | // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 | |||
|
125 | // <0=> Pclk = Cclk / 4 | |||
|
126 | // <1=> Pclk = Cclk | |||
|
127 | // <2=> Pclk = Cclk / 2 | |||
|
128 | // <3=> Pclk = Hclk / 8 | |||
|
129 | // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI | |||
|
130 | // <0=> Pclk = Cclk / 4 | |||
|
131 | // <1=> Pclk = Cclk | |||
|
132 | // <2=> Pclk = Cclk / 2 | |||
|
133 | // <3=> Pclk = Hclk / 8 | |||
|
134 | // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 | |||
|
135 | // <0=> Pclk = Cclk / 4 | |||
|
136 | // <1=> Pclk = Cclk | |||
|
137 | // <2=> Pclk = Cclk / 2 | |||
|
138 | // <3=> Pclk = Hclk / 8 | |||
|
139 | // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC | |||
|
140 | // <0=> Pclk = Cclk / 4 | |||
|
141 | // <1=> Pclk = Cclk | |||
|
142 | // <2=> Pclk = Cclk / 2 | |||
|
143 | // <3=> Pclk = Hclk / 8 | |||
|
144 | // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC | |||
|
145 | // <0=> Pclk = Cclk / 4 | |||
|
146 | // <1=> Pclk = Cclk | |||
|
147 | // <2=> Pclk = Cclk / 2 | |||
|
148 | // <3=> Pclk = Hclk / 8 | |||
|
149 | // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 | |||
|
150 | // <0=> Pclk = Cclk / 4 | |||
|
151 | // <1=> Pclk = Cclk | |||
|
152 | // <2=> Pclk = Cclk / 2 | |||
|
153 | // <3=> Pclk = Hclk / 6 | |||
|
154 | // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 | |||
|
155 | // <0=> Pclk = Cclk / 4 | |||
|
156 | // <1=> Pclk = Cclk | |||
|
157 | // <2=> Pclk = Cclk / 2 | |||
|
158 | // <3=> Pclk = Hclk / 6 | |||
|
159 | // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF | |||
|
160 | // <0=> Pclk = Cclk / 4 | |||
|
161 | // <1=> Pclk = Cclk | |||
|
162 | // <2=> Pclk = Cclk / 2 | |||
|
163 | // <3=> Pclk = Hclk / 6 | |||
|
164 | // </h> | |||
|
165 | // | |||
|
166 | // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) | |||
|
167 | // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface | |||
|
168 | // <0=> Pclk = Cclk / 4 | |||
|
169 | // <1=> Pclk = Cclk | |||
|
170 | // <2=> Pclk = Cclk / 2 | |||
|
171 | // <3=> Pclk = Hclk / 8 | |||
|
172 | // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs | |||
|
173 | // <0=> Pclk = Cclk / 4 | |||
|
174 | // <1=> Pclk = Cclk | |||
|
175 | // <2=> Pclk = Cclk / 2 | |||
|
176 | // <3=> Pclk = Hclk / 8 | |||
|
177 | // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block | |||
|
178 | // <0=> Pclk = Cclk / 4 | |||
|
179 | // <1=> Pclk = Cclk | |||
|
180 | // <2=> Pclk = Cclk / 2 | |||
|
181 | // <3=> Pclk = Hclk / 8 | |||
|
182 | // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 | |||
|
183 | // <0=> Pclk = Cclk / 4 | |||
|
184 | // <1=> Pclk = Cclk | |||
|
185 | // <2=> Pclk = Cclk / 2 | |||
|
186 | // <3=> Pclk = Hclk / 8 | |||
|
187 | // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 | |||
|
188 | // <0=> Pclk = Cclk / 4 | |||
|
189 | // <1=> Pclk = Cclk | |||
|
190 | // <2=> Pclk = Cclk / 2 | |||
|
191 | // <3=> Pclk = Hclk / 8 | |||
|
192 | // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 | |||
|
193 | // <0=> Pclk = Cclk / 4 | |||
|
194 | // <1=> Pclk = Cclk | |||
|
195 | // <2=> Pclk = Cclk / 2 | |||
|
196 | // <3=> Pclk = Hclk / 8 | |||
|
197 | // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 | |||
|
198 | // <0=> Pclk = Cclk / 4 | |||
|
199 | // <1=> Pclk = Cclk | |||
|
200 | // <2=> Pclk = Cclk / 2 | |||
|
201 | // <3=> Pclk = Hclk / 8 | |||
|
202 | // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 | |||
|
203 | // <0=> Pclk = Cclk / 4 | |||
|
204 | // <1=> Pclk = Cclk | |||
|
205 | // <2=> Pclk = Cclk / 2 | |||
|
206 | // <3=> Pclk = Hclk / 8 | |||
|
207 | // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 | |||
|
208 | // <0=> Pclk = Cclk / 4 | |||
|
209 | // <1=> Pclk = Cclk | |||
|
210 | // <2=> Pclk = Cclk / 2 | |||
|
211 | // <3=> Pclk = Hclk / 8 | |||
|
212 | // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 | |||
|
213 | // <0=> Pclk = Cclk / 4 | |||
|
214 | // <1=> Pclk = Cclk | |||
|
215 | // <2=> Pclk = Cclk / 2 | |||
|
216 | // <3=> Pclk = Hclk / 8 | |||
|
217 | // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S | |||
|
218 | // <0=> Pclk = Cclk / 4 | |||
|
219 | // <1=> Pclk = Cclk | |||
|
220 | // <2=> Pclk = Cclk / 2 | |||
|
221 | // <3=> Pclk = Hclk / 8 | |||
|
222 | // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer | |||
|
223 | // <0=> Pclk = Cclk / 4 | |||
|
224 | // <1=> Pclk = Cclk | |||
|
225 | // <2=> Pclk = Cclk / 2 | |||
|
226 | // <3=> Pclk = Hclk / 8 | |||
|
227 | // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block | |||
|
228 | // <0=> Pclk = Cclk / 4 | |||
|
229 | // <1=> Pclk = Cclk | |||
|
230 | // <2=> Pclk = Cclk / 2 | |||
|
231 | // <3=> Pclk = Hclk / 8 | |||
|
232 | // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM | |||
|
233 | // <0=> Pclk = Cclk / 4 | |||
|
234 | // <1=> Pclk = Cclk | |||
|
235 | // <2=> Pclk = Cclk / 2 | |||
|
236 | // <3=> Pclk = Hclk / 8 | |||
|
237 | // </h> | |||
|
238 | // | |||
|
239 | // <h> Power Control for Peripherals Register (PCONP) | |||
|
240 | // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable | |||
|
241 | // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable | |||
|
242 | // <o11.3> PCUART0: UART 0 power/clock enable | |||
|
243 | // <o11.4> PCUART1: UART 1 power/clock enable | |||
|
244 | // <o11.6> PCPWM1: PWM 1 power/clock enable | |||
|
245 | // <o11.7> PCI2C0: I2C interface 0 power/clock enable | |||
|
246 | // <o11.8> PCSPI: SPI interface power/clock enable | |||
|
247 | // <o11.9> PCRTC: RTC power/clock enable | |||
|
248 | // <o11.10> PCSSP1: SSP interface 1 power/clock enable | |||
|
249 | // <o11.12> PCAD: A/D converter power/clock enable | |||
|
250 | // <o11.13> PCCAN1: CAN controller 1 power/clock enable | |||
|
251 | // <o11.14> PCCAN2: CAN controller 2 power/clock enable | |||
|
252 | // <o11.15> PCGPIO: GPIOs power/clock enable | |||
|
253 | // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable | |||
|
254 | // <o11.17> PCMC: Motor control PWM power/clock enable | |||
|
255 | // <o11.18> PCQEI: Quadrature encoder interface power/clock enable | |||
|
256 | // <o11.19> PCI2C1: I2C interface 1 power/clock enable | |||
|
257 | // <o11.21> PCSSP0: SSP interface 0 power/clock enable | |||
|
258 | // <o11.22> PCTIM2: Timer 2 power/clock enable | |||
|
259 | // <o11.23> PCTIM3: Timer 3 power/clock enable | |||
|
260 | // <o11.24> PCUART2: UART 2 power/clock enable | |||
|
261 | // <o11.25> PCUART3: UART 3 power/clock enable | |||
|
262 | // <o11.26> PCI2C2: I2C interface 2 power/clock enable | |||
|
263 | // <o11.27> PCI2S: I2S interface power/clock enable | |||
|
264 | // <o11.29> PCGPDMA: GP DMA function power/clock enable | |||
|
265 | // <o11.30> PCENET: Ethernet block power/clock enable | |||
|
266 | // <o11.31> PCUSB: USB interface power/clock enable | |||
|
267 | // </h> | |||
|
268 | // | |||
|
269 | // <h> Clock Output Configuration Register (CLKOUTCFG) | |||
|
270 | // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT | |||
|
271 | // <0=> CPU clock | |||
|
272 | // <1=> Main oscillator | |||
|
273 | // <2=> Internal RC oscillator | |||
|
274 | // <3=> USB clock | |||
|
275 | // <4=> RTC oscillator | |||
|
276 | // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT | |||
|
277 | // <1-16><#-1> | |||
|
278 | // <o12.8> CLKOUT_EN: CLKOUT enable control | |||
|
279 | // </h> | |||
|
280 | // | |||
|
281 | // </e> | |||
|
282 | */ | |||
|
283 | #define CLOCK_SETUP 1 | |||
|
284 | #define SCS_Val 0x00000000 | |||
|
285 | #define CLKSRCSEL_Val 0x00000000 | |||
|
286 | #define PLL0_SETUP 0 | |||
|
287 | #define PLL0CFG_Val 0x00050063 | |||
|
288 | #define PLL1_SETUP 0 | |||
|
289 | #define PLL1CFG_Val 0x00000023 | |||
|
290 | #define CCLKCFG_Val 0x00000003 | |||
|
291 | #define USBCLKCFG_Val 0x00000000 | |||
|
292 | #define PCLKSEL0_Val 0x00000000 | |||
|
293 | #define PCLKSEL1_Val 0x00000000 | |||
|
294 | #define PCONP_Val 0x042887DE | |||
|
295 | #define CLKOUTCFG_Val 0x00000000 | |||
|
296 | ||||
|
297 | ||||
|
298 | /*--------------------- Flash Accelerator Configuration ---------------------- | |||
|
299 | // | |||
|
300 | // <e> Flash Accelerator Configuration | |||
|
301 | // <o1.12..15> FLASHTIM: Flash Access Time | |||
|
302 | // <0=> 1 CPU clock (for CPU clock up to 20 MHz) | |||
|
303 | // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) | |||
|
304 | // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) | |||
|
305 | // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) | |||
|
306 | // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) | |||
|
307 | // <5=> 6 CPU clocks (for any CPU clock) | |||
|
308 | // </e> | |||
|
309 | */ | |||
|
310 | #define FLASH_SETUP 1 | |||
|
311 | #define FLASHCFG_Val 0x00005000 | |||
|
312 | ||||
|
313 | /* | |||
|
314 | //-------- <<< end of configuration section >>> ------------------------------ | |||
|
315 | */ | |||
|
316 | ||||
|
317 | /*---------------------------------------------------------------------------- | |||
|
318 | Check the register settings | |||
|
319 | *----------------------------------------------------------------------------*/ | |||
|
320 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) | |||
|
321 | #define CHECK_RSVD(val, mask) (val & mask) | |||
|
322 | ||||
|
323 | /* Clock Configuration -------------------------------------------------------*/ | |||
|
324 | #if (CHECK_RSVD((SCS_Val), ~0x00000030)) | |||
|
325 | #error "SCS: Invalid values of reserved bits!" | |||
|
326 | #endif | |||
|
327 | ||||
|
328 | #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) | |||
|
329 | #error "CLKSRCSEL: Value out of range!" | |||
|
330 | #endif | |||
|
331 | ||||
|
332 | #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) | |||
|
333 | #error "PLL0CFG: Invalid values of reserved bits!" | |||
|
334 | #endif | |||
|
335 | ||||
|
336 | #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) | |||
|
337 | #error "PLL1CFG: Invalid values of reserved bits!" | |||
|
338 | #endif | |||
|
339 | ||||
|
340 | #if (PLL0_SETUP) /* if PLL0 is used */ | |||
|
341 | #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ | |||
|
342 | #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" | |||
|
343 | #endif | |||
|
344 | #endif | |||
|
345 | ||||
|
346 | #if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) | |||
|
347 | #error "CCLKCFG: Value out of range!" | |||
|
348 | #endif | |||
|
349 | ||||
|
350 | #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) | |||
|
351 | #error "USBCLKCFG: Invalid values of reserved bits!" | |||
|
352 | #endif | |||
|
353 | ||||
|
354 | #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) | |||
|
355 | #error "PCLKSEL0: Invalid values of reserved bits!" | |||
|
356 | #endif | |||
|
357 | ||||
|
358 | #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) | |||
|
359 | #error "PCLKSEL1: Invalid values of reserved bits!" | |||
|
360 | #endif | |||
|
361 | ||||
|
362 | #if (CHECK_RSVD((PCONP_Val), 0x10100821)) | |||
|
363 | #error "PCONP: Invalid values of reserved bits!" | |||
|
364 | #endif | |||
|
365 | ||||
|
366 | #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) | |||
|
367 | #error "CLKOUTCFG: Invalid values of reserved bits!" | |||
|
368 | #endif | |||
|
369 | ||||
|
370 | /* Flash Accelerator Configuration -------------------------------------------*/ | |||
|
371 | #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) | |||
|
372 | #error "FLASHCFG: Invalid values of reserved bits!" | |||
|
373 | #endif | |||
|
374 | ||||
|
375 | ||||
|
376 | /*---------------------------------------------------------------------------- | |||
|
377 | DEFINES | |||
|
378 | *----------------------------------------------------------------------------*/ | |||
|
379 | ||||
|
380 | /*---------------------------------------------------------------------------- | |||
|
381 | Define clocks | |||
|
382 | *----------------------------------------------------------------------------*/ | |||
|
383 | #define XTAL (12000000UL) /* Oscillator frequency */ | |||
|
384 | #define OSC_CLK ( IRC_OSC) /* Main oscillator frequency */ | |||
|
385 | //#define OSC_CLK ( XTAL) /* Main oscillator frequency */ | |||
|
386 | #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ | |||
|
387 | #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ | |||
|
388 | ||||
|
389 | ||||
|
390 | /* F_cco0 = (2 * M * F_in) / N */ | |||
|
391 | #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) | |||
|
392 | #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) | |||
|
393 | #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) | |||
|
394 | #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) | |||
|
395 | ||||
|
396 | /* Determine core clock frequency according to settings */ | |||
|
397 | #if (PLL0_SETUP) | |||
|
398 | #if ((CLKSRCSEL_Val & 0x03) == 1) | |||
|
399 | #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) | |||
|
400 | #elif ((CLKSRCSEL_Val & 0x03) == 2) | |||
|
401 | #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) | |||
|
402 | #else | |||
|
403 | #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) | |||
|
404 | #endif | |||
|
405 | #else | |||
|
406 | #if ((CLKSRCSEL_Val & 0x03) == 1) | |||
|
407 | #define __CORE_CLK (OSC_CLK / __CCLK_DIV) | |||
|
408 | #elif ((CLKSRCSEL_Val & 0x03) == 2) | |||
|
409 | #define __CORE_CLK (RTC_CLK / __CCLK_DIV) | |||
|
410 | #else | |||
|
411 | #define __CORE_CLK (IRC_OSC / __CCLK_DIV) | |||
|
412 | #endif | |||
|
413 | #endif | |||
|
414 | ||||
|
415 | ||||
|
416 | /*---------------------------------------------------------------------------- | |||
|
417 | Clock Variable definitions | |||
|
418 | *----------------------------------------------------------------------------*/ | |||
|
419 | uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ | |||
|
420 | ||||
|
421 | ||||
|
422 | /*---------------------------------------------------------------------------- | |||
|
423 | Clock functions | |||
|
424 | *----------------------------------------------------------------------------*/ | |||
|
425 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ | |||
|
426 | { | |||
|
427 | /* Determine clock frequency according to clock register values */ | |||
|
428 | if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ | |||
|
429 | switch (LPC_SC->CLKSRCSEL & 0x03) { | |||
|
430 | case 0: /* Int. RC oscillator => PLL0 */ | |||
|
431 | case 3: /* Reserved, default to Int. RC */ | |||
|
432 | SystemCoreClock = (IRC_OSC * | |||
|
433 | ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / | |||
|
434 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / | |||
|
435 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); | |||
|
436 | break; | |||
|
437 | case 1: /* Main oscillator => PLL0 */ | |||
|
438 | SystemCoreClock = (OSC_CLK * | |||
|
439 | ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / | |||
|
440 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / | |||
|
441 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); | |||
|
442 | break; | |||
|
443 | case 2: /* RTC oscillator => PLL0 */ | |||
|
444 | SystemCoreClock = (RTC_CLK * | |||
|
445 | ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / | |||
|
446 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / | |||
|
447 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); | |||
|
448 | break; | |||
|
449 | } | |||
|
450 | } else { | |||
|
451 | switch (LPC_SC->CLKSRCSEL & 0x03) { | |||
|
452 | case 0: /* Int. RC oscillator => PLL0 */ | |||
|
453 | case 3: /* Reserved, default to Int. RC */ | |||
|
454 | SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); | |||
|
455 | break; | |||
|
456 | case 1: /* Main oscillator => PLL0 */ | |||
|
457 | SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); | |||
|
458 | break; | |||
|
459 | case 2: /* RTC oscillator => PLL0 */ | |||
|
460 | SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); | |||
|
461 | break; | |||
|
462 | } | |||
|
463 | } | |||
|
464 | ||||
|
465 | } | |||
|
466 | ||||
|
467 | /** | |||
|
468 | * Initialize the system | |||
|
469 | * | |||
|
470 | * @param none | |||
|
471 | * @return none | |||
|
472 | * | |||
|
473 | * @brief Setup the microcontroller system. | |||
|
474 | * Initialize the System. | |||
|
475 | */ | |||
|
476 | void SystemInit (void) | |||
|
477 | { | |||
|
478 | ||||
|
479 | #if (CLOCK_SETUP) /* Clock Setup */ | |||
|
480 | LPC_SC->SCS = SCS_Val; | |||
|
481 | if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ | |||
|
482 | while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ | |||
|
483 | } | |||
|
484 | ||||
|
485 | ||||
|
486 | ||||
|
487 | LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ | |||
|
488 | ||||
|
489 | LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ | |||
|
490 | LPC_SC->PCLKSEL1 = PCLKSEL1_Val; | |||
|
491 | ||||
|
492 | LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ | |||
|
493 | ||||
|
494 | #if (PLL0_SETUP) | |||
|
495 | // LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ | |||
|
496 | // LPC_SC->PLL0FEED = 0xAA; | |||
|
497 | // LPC_SC->PLL0FEED = 0x55; | |||
|
498 | ||||
|
499 | // LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ | |||
|
500 | // LPC_SC->PLL0FEED = 0xAA; | |||
|
501 | // LPC_SC->PLL0FEED = 0x55; | |||
|
502 | // while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ | |||
|
503 | ||||
|
504 | // LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ | |||
|
505 | // LPC_SC->PLL0FEED = 0xAA; | |||
|
506 | // LPC_SC->PLL0FEED = 0x55; | |||
|
507 | // while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ | |||
|
508 | #endif | |||
|
509 | ||||
|
510 | ||||
|
511 | ||||
|
512 | #if (PLL1_SETUP) | |||
|
513 | // LPC_SC->PLL1CFG = PLL1CFG_Val; | |||
|
514 | // LPC_SC->PLL1FEED = 0xAA; | |||
|
515 | // LPC_SC->PLL1FEED = 0x55; | |||
|
516 | ||||
|
517 | // LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ | |||
|
518 | // LPC_SC->PLL1FEED = 0xAA; | |||
|
519 | // LPC_SC->PLL1FEED = 0x55; | |||
|
520 | // while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ | |||
|
521 | ||||
|
522 | // LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ | |||
|
523 | // LPC_SC->PLL1FEED = 0xAA; | |||
|
524 | // LPC_SC->PLL1FEED = 0x55; | |||
|
525 | // while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ | |||
|
526 | #else | |||
|
527 | LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ | |||
|
528 | #endif | |||
|
529 | ||||
|
530 | LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ | |||
|
531 | ||||
|
532 | LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ | |||
|
533 | #endif | |||
|
534 | ||||
|
535 | #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ | |||
|
536 | LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; | |||
|
537 | #endif | |||
|
538 | ||||
|
539 | ||||
|
540 | ||||
|
541 | } |
@@ -0,0 +1,56 | |||||
|
1 | #/*------------------------------------------------------------------------------ | |||
|
2 | #-- This file is a part of the libuc, microcontroler library | |||
|
3 | #-- Copyright (C) 2011, Alexis Jeandet | |||
|
4 | #-- | |||
|
5 | #-- This program is free software; you can redistribute it and/or modify | |||
|
6 | #-- it under the terms of the GNU General Public License as published by | |||
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | #-- (at your option) any later version. | |||
|
9 | #-- | |||
|
10 | #-- This program is distributed in the hope that it will be useful, | |||
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | #-- GNU General Public License for more details. | |||
|
14 | #-- | |||
|
15 | #-- You should have received a copy of the GNU General Public License | |||
|
16 | #-- along with this program; if not, write to the Free Software | |||
|
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | #------------------------------------------------------------------------------- | |||
|
19 | #-- Author : Alexis Jeandet | |||
|
20 | #-- Mail : alexis.jeandet@gmail.com | |||
|
21 | #-------------------------------------------------------------------------------*/ | |||
|
22 | #include "ssp.h" | |||
|
23 | #include "vs1053.h" | |||
|
24 | //#include <bsp.h> | |||
|
25 | ||||
|
26 | void vs1053open(vs1053Dev* codec,sspDev dev){ | |||
|
27 | codec->SSP_device = dev; | |||
|
28 | ||||
|
29 | } | |||
|
30 | ||||
|
31 | void vs1053softreset(vs1053Dev* dev) | |||
|
32 | { | |||
|
33 | vs1053cmdwrite(dev,VSMODE,(1<<2)); | |||
|
34 | } | |||
|
35 | ||||
|
36 | int vs1053cmdread(vs1053Dev* dev,char address) | |||
|
37 | { | |||
|
38 | int result; | |||
|
39 | while(!vs10XXDREQ()); | |||
|
40 | vs10XXclearXCS(); | |||
|
41 | sspputw(dev->SSP_device,(3<<8)+address); | |||
|
42 | result = sspgetw(dev->SSP_device); | |||
|
43 | vs10XXsetXCS(); | |||
|
44 | return result; | |||
|
45 | } | |||
|
46 | ||||
|
47 | ||||
|
48 | void vs1053cmdwrite(vs1053Dev* dev,char address,int value) | |||
|
49 | { | |||
|
50 | while(!vs10XXDREQ()); | |||
|
51 | vs10XXclearXCS(); | |||
|
52 | sspputw(dev->SSP_device,(2<<8)+address); | |||
|
53 | sspputw(dev->SSP_device,value); | |||
|
54 | vs10XXsetXCS(); | |||
|
55 | } | |||
|
56 |
@@ -0,0 +1,78 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | #-- This file is a part of the libuc, microcontroler library | |||
|
3 | #-- Copyright (C) 2011, Alexis Jeandet | |||
|
4 | #-- | |||
|
5 | #-- This program is free software; you can redistribute it and/or modify | |||
|
6 | #-- it under the terms of the GNU General Public License as published by | |||
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | #-- (at your option) any later version. | |||
|
9 | #-- | |||
|
10 | #-- This program is distributed in the hope that it will be useful, | |||
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | #-- GNU General Public License for more details. | |||
|
14 | #-- | |||
|
15 | #-- You should have received a copy of the GNU General Public License | |||
|
16 | #-- along with this program; if not, write to the Free Software | |||
|
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | #------------------------------------------------------------------------------- | |||
|
19 | #-- Author : Alexis Jeandet | |||
|
20 | #-- Mail : alexis.jeandet@gmail.com | |||
|
21 | #-------------------------------------------------------------------------------*/ | |||
|
22 | #ifndef VS1053_H | |||
|
23 | #define VS1053_H | |||
|
24 | #include <uhandle.h> | |||
|
25 | ||||
|
26 | #define VSMODE 0 | |||
|
27 | #define VSSTATUS 1 | |||
|
28 | #define VSBASS 2 | |||
|
29 | #define VSCLOCKF 3 | |||
|
30 | #define VSDECODE_TIME 4 | |||
|
31 | #define VSAUDATA 5 | |||
|
32 | #define VSWRAM 6 | |||
|
33 | #define VSWRAMADDR 7 | |||
|
34 | #define VSHDAT0 8 | |||
|
35 | #define VSHDAT1 9 | |||
|
36 | #define VSAIADDR 0xA | |||
|
37 | #define VSVOL 0xB | |||
|
38 | #define VSAICTRL0 0xC | |||
|
39 | #define VSAICTRL1 0xD | |||
|
40 | #define VSAICTRL2 0xE | |||
|
41 | #define VSAICTRL3 0xF | |||
|
42 | ||||
|
43 | struct vs1053Regs | |||
|
44 | { | |||
|
45 | sspDev SSP_device; | |||
|
46 | int a; | |||
|
47 | }; | |||
|
48 | ||||
|
49 | typedef struct vs1053Regs vs1053Dev; | |||
|
50 | ||||
|
51 | void vs1053open(vs1053Dev* codec,sspDev dev); | |||
|
52 | void vs1053softreset(vs1053Dev* dev); | |||
|
53 | int vs1053cmdread(vs1053Dev* dev,char address); | |||
|
54 | void vs1053cmdwrite(vs1053Dev* dev,char address,int value); | |||
|
55 | ||||
|
56 | extern void vs10XXclearXCS(); | |||
|
57 | extern void vs10XXsetXCS(); | |||
|
58 | extern int vs10XXDREQ(); | |||
|
59 | ||||
|
60 | #endif | |||
|
61 | ||||
|
62 | ||||
|
63 | ||||
|
64 | ||||
|
65 | ||||
|
66 | ||||
|
67 | ||||
|
68 | ||||
|
69 | ||||
|
70 | ||||
|
71 | ||||
|
72 | ||||
|
73 | ||||
|
74 | ||||
|
75 | ||||
|
76 | ||||
|
77 | ||||
|
78 |
@@ -0,0 +1,12 | |||||
|
1 | TEMPLATE = lib | |||
|
2 | ARCH = stm32f4-arm-none-eabi-gcc | |||
|
3 | TARGET = libvs10XX | |||
|
4 | TARGETINSTALLPATH = $(LIBUC_LIBS_DIR_VS10XX) | |||
|
5 | HEADERSINSTALLPATH = $(LIBUC_INC_DIR_VS10XX) | |||
|
6 | ||||
|
7 | LIBS += CORE SSP UHANDLE | |||
|
8 | ||||
|
9 | SOURCES += vs1053.c | |||
|
10 | ||||
|
11 | ||||
|
12 | HEADERS += vs1053.h |
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