diff --git a/lib/includes/CS43L22.h b/lib/includes/CS43L22.h new file mode 100644 --- /dev/null +++ b/lib/includes/CS43L22.h @@ -0,0 +1,87 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the libuc, microcontroler library +-- Copyright (C) 2011, Alexis Jeandet +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@gmail.com +-------------------------------------------------------------------------------*/ +#ifndef CS43L22_H +#define CS43L22_H + +#include +#include + +typedef struct CS43L22_t +{ + i2c_t i2cdev; + uint8_t devAddress; +}CS43L22_t; + +extern int cs43l22open(CS43L22_t* dev,uint8_t address); + + + + + +#define CS43L22_MAP_ID 1 +#define CS43L22_MAP_Power_Ctl_1 2 +#define CS43L22_MAP_Power_Ctl_2 4 +#define CS43L22_MAP_Clocking_Ctl 5 +#define CS43L22_MAP_Interface_Ctl_1 6 +#define CS43L22_MAP_Interface_Ctl_2 7 +#define CS43L22_MAP_Passthrough_A 8 +#define CS43L22_MAP_Passthrough_B 9 +#define CS43L22_MAP_Analog_ZC_SR 0xA +#define CS43L22_MAP_Passthrough 0xC +#define CS43L22_MAP_Playback_Ctl_1 0xD +#define CS43L22_MAP_Misc_Ctl 0xE +#define CS43L22_MAP_Playback_Ctl_2 0xF +#define CS43L22_MAP_Passthrough_A 0x14 +#define CS43L22_MAP_Passthrough_B 0x15 +#define CS43L22_MAP_PCMA_Vol 0x1A +#define CS43L22_MAP_PCMB_Vol 0x1B +#define CS43L22_MAP_BEEP_Freq 0x1C +#define CS43L22_MAP_BEEP_Vol 0x1d +#define CS43L22_MAP_BEEP_Tone_Cfg 0x1E +#define CS43L22_MAP_Tone_Ctl 0x1F +#define CS43L22_MAP_Master_A_Vol 0x20 +#define CS43L22_MAP_Master_B_Vol 0x21 +#define CS43L22_MAP_Headphone_A_Vol 0x22 +#define CS43L22_MAP_Headphone_B_Vol 0x23 +#define CS43L22_MAP_Speaker_A_Vol 0x24 +#define CS43L22_MAP_Speaker_B_Vol 0x25 +#define CS43L22_MAP_Channel_Mixer 0x26 +#define CS43L22_MAP_Limit_Ctl_1 0x27 +#define CS43L22_MAP_Limit Ctl_2 0x28 +#define CS43L22_MAP_Limiter_Attack 0x29 +#define CS43L22_MAP_Overflow_&_Clock_Status 0x2E +#define CS43L22_MAP_Battery_Compensation 0x2F +#define CS43L22_MAP_VP_Battery_Level 0x30 +#define CS43L22_MAP_Speaker_Status 0x31 +#define CS43L22_MAP_Temperature_Monitor_Control 0x32 +#define CS43L22_MAP_Thermal_Foldback 0x33 +#define CS43L22_MAP_Charge_Pump_Frequency 0x34 + + +#endif + + + + + + + diff --git a/lib/src/common/24LCXX/24LC0X/core_cm3.c b/lib/src/common/24LCXX/24LC0X/core_cm3.c deleted file mode 100644 --- a/lib/src/common/24LCXX/24LC0X/core_cm3.c +++ /dev/null @@ -1,339 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V2.00 - * @date 13. September 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask Register. - - \return Fault Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set the Fault Mask - - This function assigns the given value to the Fault Mask Register. - - \param [in] faultMask Fault Mask value value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif diff --git a/lib/src/common/24LCXX/24LC0X/lpc17XX.mk b/lib/src/common/24LCXX/24LC0X/lpc17XX.mk deleted file mode 100644 --- a/lib/src/common/24LCXX/24LC0X/lpc17XX.mk +++ /dev/null @@ -1,95 +0,0 @@ -PROJECTDIR = `pwd` -LIBUC = /opt/libuc2 - -HEADERSINSTALLPATH = $(LIBUC_INC_DIR_24LC0X) -HEADERS += 24LC0X.h -SOURCES += 24LC0X.c -OBJDIR = obj -BINDIR = bin -OBJECTFILES = - -ARCH = stm32f4-arm-none-eabi-gcc -ARCHFOLDER = $(LIBUC)/rules/stm32f4-arm-none-eabi-gcc -TARGET=lib24lc0X -LIBUC_INCLUDES=$(LIBUC_INC_DIR_CORE_CMD) $(LIBUC_INC_DIR_IIC_CMD) $(LIBUC_INC_DIR_UHANDLE_CMD) -LIBUC_LIBRARIES=$(LIBUC_LIBS_DIR_CORE_CMD) $(LIBUC_LIBS_CORE) $(LIBUC_LIBS_DIR_IIC_CMD) $(LIBUC_LIBS_IIC) $(LIBUC_LIBS_DIR_UHANDLE_CMD) $(LIBUC_LIBS_UHANDLE) -TARGETINSTALLPATH=$(LIBUC_LIBS_DIR_24LC0X) -HEADERSINSTALLPATH=$(LIBUC_INC_DIR_24LC0X) -BSP=generic -include $(ARCHFOLDER)/rules.mk -INCLUDES += -I ./ - - - - -all:lib - @echo Code compiled - -.SUFFIXES: .o .c .s - -.c.o: - $(LIBUC_CC) -O3 -I $(INCLUDES) -c $(CFLAGS) $< -o $@ - -.s.o: - $(LIBUC_CC) -O3 -I $(INCLUDES) -c $(CFLAGS) $< -o $@ - -bin: $(BINDIR)/$(TARGET).elf $(BINDIR)/$(TARGET).bin $(BINDIR)/$(TARGET).hex - @echo "compile bin" - -lib: $(BINDIR)/$(TARGET).a - @echo "compile lib" - - -$(BINDIR)/$(TARGET).a: $(OBJECTFILES) - mkdir -p $(BINDIR) - $(LIBUC_AR) rcs $@ $(OBJECTFILES) - -$(OBJDIR): - mkdir -p $(OBJDIR) - -%.elf: $(LINKER_SCRIPT) $(OBJECTFILES) - mkdir -p $(BINDIR) - $(LIBUC_CC) $(LIBUC_LDFLAGS) $(LIBUC_CFLAGS) -T $^ -o $@ $(LIBUC_BSP) $(LIBUC_LIBRARIES) - $(LIBUC_OBJDUMP) $(LIBUC_ODFLAGS) $@ > $(@:.elf=.dump) - $(LIBUC_SIZE) $@ - - -%.bin: %.elf $(BIN_LIBS_DEPS) - $(LIBUC_OBJCOPY) $(LIBUC_CPFLAGS) -O binary $< $*.bin - @echo "BIN_LIBS_DEPS" - @echo $(BIN_LIBS_DEPS) - - -%.hex: %.elf - $(LIBUC_OBJCOPY) $(LIBUC_CPFLAGS) -O ihex $< $*.hex - -$(TARGETINSTALLPATH)/$(TARGET).a: $(BINDIR)/$(TARGET).a - mkdir -p $(TARGETINSTALLPATH) - cp $(BINDIR)/$(TARGET).a $(TARGETINSTALLPATH)/$(TARGET).a - -libinstall: $(TARGETINSTALLPATH)/$(TARGET).a - @if [ -z $(HEADERSINSTALLPATH) ] ; then echo "No headers to install" ; else mkdir -p $(HEADERSINSTALLPATH) ; fi - @if [ -z "$(HEADERS)" ] ; then echo "No headers to install" ; else echo "cp -f $(HEADERS) $(HEADERSINSTALLPATH)/" ; cp -f $(HEADERS) $(HEADERSINSTALLPATH)/ ; fi - -clean: - rm -f *.o *.d *.bin *.hex *.dump *.map *.a *.elf - rm -f $(OBJECTFILES) - rm -f $(BINDIR)/*.bin - rm -f $(BINDIR)/*.hex - rm -f $(BINDIR)/*.dump - rm -f $(BINDIR)/*.map - rm -f $(BINDIR)/*.a - rm -f $(BINDIR)/*.elf - rm -f $(DEVSOURCESND) - rm -f $(ASMDEVSOURCESND) - -distclean: clean libclean - rm -f $(TARGETINSTALLPATH)/*.bin - rm -f $(TARGETINSTALLPATH)/*.a - rm -f Makefile - -install:libinstall - - -libclean: - rm -f $(TARGETINSTALLPATH)/$(TARGET).a diff --git a/lib/src/common/24LCXX/24LC0X/startup_LPC17xx.c b/lib/src/common/24LCXX/24LC0X/startup_LPC17xx.c deleted file mode 100644 --- a/lib/src/common/24LCXX/24LC0X/startup_LPC17xx.c +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************//** - * @file : startup_LPC17xx.c - * @brief : CMSIS Cortex-M3 Core Device Startup File - * @version : V1.01 - * @date : 4. Feb. 2009 - * - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -// Mod by nio for the .fastcode part - -#include "LPC17xx.h" - -#define WEAK __attribute__ ((weak)) -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -/* System exception vector handler */ -void WEAK Reset_Handler(void); /* Reset Handler */ -void WEAK NMI_Handler(void); /* NMI Handler */ -void WEAK HardFault_Handler(void); /* Hard Fault Handler */ -void WEAK MemManage_Handler(void); /* MPU Fault Handler */ -void WEAK BusFault_Handler(void); /* Bus Fault Handler */ -void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ -void WEAK SVC_Handler(void); /* SVCall Handler */ -void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ -void WEAK PendSV_Handler(void); /* PendSV Handler */ -void WEAK SysTick_Handler(void); /* SysTick Handler */ - -/* External interrupt vector handler */ -void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ -void WEAK TIMER0_IRQHandler(void); /* Timer0 */ -void WEAK TIMER1_IRQHandler(void); /* Timer1 */ -void WEAK TIMER2_IRQHandler(void); /* Timer2 */ -void WEAK TIMER3_IRQHandler(void); /* Timer3 */ -void WEAK UART0_IRQHandler(void); /* UART0 */ -void WEAK UART1_IRQHandler(void); /* UART1 */ -void WEAK UART2_IRQHandler(void); /* UART2 */ -void WEAK UART3_IRQHandler(void); /* UART3 */ -void WEAK PWM1_IRQHandler(void); /* PWM1 */ -void WEAK I2C0_IRQHandler(void); /* I2C0 */ -void WEAK I2C1_IRQHandler(void); /* I2C1 */ -void WEAK I2C2_IRQHandler(void); /* I2C2 */ -void WEAK SPI_IRQHandler(void); /* SPI */ -void WEAK SSP0_IRQHandler(void); /* SSP0 */ -void WEAK SSP1_IRQHandler(void); /* SSP1 */ -void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ -void WEAK RTC_IRQHandler(void); /* Real Time Clock */ -void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ -void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ -void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ -void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ -void WEAK ADC_IRQHandler(void); /* A/D Converter */ -void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ -void WEAK USB_IRQHandler(void); /* USB */ -void WEAK CAN_IRQHandler(void); /* CAN */ -void WEAK DMA_IRQHandler(void); /* GP DMA */ -void WEAK I2S_IRQHandler(void); /* I2S */ -void WEAK ENET_IRQHandler(void); /* Ethernet */ -void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ -void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ -void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ -void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ - - - -/* Exported types --------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -extern unsigned long _etext; -extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ -extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ -extern unsigned long _edata; /* end address for the .data section. defined in linker script */ -extern unsigned long _sitestdata; /* start address for the initialization values of the .data section. defined in linker script */ -extern unsigned long _stestdata; /* start address for the .data section. defined in linker script */ -extern unsigned long _etestdata; - - -extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */ -extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */ -extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */ - -extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ -extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ - -extern void _estack; /* init value for the stack pointer. defined in linker script */ - -extern int bsp_init(); - -/* Private typedef -----------------------------------------------------------*/ -/* function prototypes ------------------------------------------------------*/ -void Reset_Handler(void) __attribute__((__interrupt__)); -extern int main(void); - - -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ -#define STACK_SIZE 0x00000800 /*2kO*/ - -__attribute__ ((section(".stackarea"))) -/* static */ unsigned long pulStack[STACK_SIZE]; - - -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - /* &_estack, // The initial stack pointer */ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - // External Interrupts - WDT_IRQHandler, /* Watchdog Timer */ - TIMER0_IRQHandler, /* Timer0 */ - TIMER1_IRQHandler, /* Timer1 */ - TIMER2_IRQHandler, /* Timer2 */ - TIMER3_IRQHandler, /* Timer3 */ - UART0_IRQHandler, /* UART0 */ - UART1_IRQHandler, /* UART1 */ - UART2_IRQHandler, /* UART2 */ - UART3_IRQHandler, /* UART3 */ - PWM1_IRQHandler, /* PWM1 */ - I2C0_IRQHandler, /* I2C0 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI_IRQHandler, /* SPI */ - SSP0_IRQHandler, /* SSP0 */ - SSP1_IRQHandler, /* SSP1 */ - PLL0_IRQHandler, /* PLL0 (Main PLL) */ - RTC_IRQHandler, /* Real Time Clock */ - EINT0_IRQHandler, /* External Interrupt 0 */ - EINT1_IRQHandler, /* External Interrupt 1 */ - EINT2_IRQHandler, /* External Interrupt 2 */ - EINT3_IRQHandler, /* External Interrupt 3 */ - ADC_IRQHandler, /* A/D Converter */ - BOD_IRQHandler, /* Brown Out Detect */ - USB_IRQHandler, /* USB */ - CAN_IRQHandler, /* CAN */ - DMA_IRQHandler, /* GP DMA */ - I2S_IRQHandler, /* I2S */ - ENET_IRQHandler, /* Ethernet */ - RIT_IRQHandler, /* Repetitive Interrupt Timer */ - MCPWM_IRQHandler, /* Motor Control PWM */ - QEI_IRQHandler, /* Quadrature Encoder Interface */ - PLL1_IRQHandler, /* PLL1 (USB PLL) */ -}; - -/******************************************************************************* -* Function Name : Reset_Handler -* Description : This is the code that gets called when the processor first starts execution -* following a reset event. Only the absolutely necessary set is performed, -* after which the application supplied main() routine is called. -* Input : -* Output : -* Return : -*******************************************************************************/ -void Reset_Handler(void) -{ - SystemInit(); - - unsigned long *pulDest; - unsigned long *pulSrc; - - // - // Copy the data segment initializers from flash to SRAM in ROM mode - // - - if (&_sidata != &_sdata) { // only if needed - pulSrc = &_sidata; - for(pulDest = &_sdata; pulDest < &_edata; ) { - *(pulDest++) = *(pulSrc++); - } - } - if (&_sitestdata != &_stestdata) { // only if needed - pulSrc = &_sitestdata; - for(pulDest = &_stestdata; pulDest < &_etestdata; ) { - *(pulDest++) = *(pulSrc++); - } - } - - // Copy the .fastcode code from ROM to SRAM - - if (&_sifastcode != &_sfastcode) { // only if needed - pulSrc = &_sifastcode; - for(pulDest = &_sfastcode; pulDest < &_efastcode; ) { - *(pulDest++) = *(pulSrc++); - } - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_sbss; pulDest < &_ebss; ) - { - *(pulDest++) = 0; - } - - // - // Call the application's entry point. - // - bsp_init(); - main(); -} - -//***************************************************************************** -// -// Provide weak aliases for each Exception handler to the Default_Handler. -// As they are weak aliases, any function with the same name will override -// this definition. -// -//***************************************************************************** -#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ -#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ -#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ -#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ -#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ -#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ -#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ - -/* External interrupt vector handler */ -#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */ -#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */ -#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */ -#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */ -#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */ -#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */ -#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */ -#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */ -#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */ -#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */ -#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */ -#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */ -#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */ -#pragma weak SPI_IRQHandler = Default_Handler /* SPI */ -#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */ -#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */ -#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */ -#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */ -#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */ -#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */ -#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */ -#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */ -#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */ -#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */ -#pragma weak USB_IRQHandler = Default_Handler /* USB */ -#pragma weak CAN_IRQHandler = Default_Handler /* CAN */ -#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */ -#pragma weak I2S_IRQHandler = Default_Handler /* I2S */ -#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */ -#pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */ -#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */ -#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */ -#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */ - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -void Default_Handler(void) { - // Go into an infinite loop. - // - while (1) { - } -} diff --git a/lib/src/common/24LCXX/24LC0X/system_LPC17xx.c b/lib/src/common/24LCXX/24LC0X/system_LPC17xx.c deleted file mode 100644 --- a/lib/src/common/24LCXX/24LC0X/system_LPC17xx.c +++ /dev/null @@ -1,541 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC17xx Device Series - * @version V1.08 - * @date 12. May 2010 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 24 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <1-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000000 -#define CLKSRCSEL_Val 0x00000000 -#define PLL0_SETUP 0 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 0 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x00000030)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (PLL0_SETUP) /* if PLL0 is used */ - #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ - #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" - #endif -#endif - -#if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) - #error "CCLKCFG: Value out of range!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( IRC_OSC) /* Main oscillator frequency */ -//#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) -#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) -#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else - #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (RTC_CLK / __CCLK_DIV) - #else - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #endif - #endif - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - -#if (PLL0_SETUP) -// LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; - -// LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; -// while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - -// LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; -// while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - - - -#if (PLL1_SETUP) -// LPC_SC->PLL1CFG = PLL1CFG_Val; -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; - -// LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; -// while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - -// LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; -// while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; -#endif - - - -} diff --git a/lib/src/common/AUDIO/AUDIO.pro b/lib/src/common/AUDIO/AUDIO.pro new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/AUDIO.pro @@ -0,0 +1,5 @@ +TEMPLATE = subdirs +CONFIG += ordered + +SUBDIRS += CS43L22 #\ +# VS10XX diff --git a/lib/src/common/AUDIO/CS43L22/CS43L22.c b/lib/src/common/AUDIO/CS43L22/CS43L22.c new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/CS43L22/CS43L22.c @@ -0,0 +1,31 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the libuc, microcontroler library +-- Copyright (C) 2012, Alexis Jeandet +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@gmail.com +-------------------------------------------------------------------------------*/ + + + + + + + + + + diff --git a/lib/src/common/AUDIO/CS43L22/CS43L22.pro b/lib/src/common/AUDIO/CS43L22/CS43L22.pro new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/CS43L22/CS43L22.pro @@ -0,0 +1,4 @@ +TEMPLATE = subdirs +CONFIG += ordered + +SUBDIRS += ./CS43L22_STM32F4.pro diff --git a/lib/src/common/AUDIO/CS43L22/CS43L22_STM32F4.pro b/lib/src/common/AUDIO/CS43L22/CS43L22_STM32F4.pro new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/CS43L22/CS43L22_STM32F4.pro @@ -0,0 +1,11 @@ +TEMPLATE = lib +CONFIG += console +CONFIG -= qt +TARGET = CS43L22 +include($$(libuc2)/rules/stm32f4-arm-none-eabi-gcc/rules.pri) + +SOURCES += \ + CS43L22.c + +HEADERS += \ + $$(libuc2)/lib/includes/CS43L22.h diff --git a/lib/src/common/AUDIO/VS10XX/core_cm3.c b/lib/src/common/AUDIO/VS10XX/core_cm3.c new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/core_cm3.c @@ -0,0 +1,339 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V2.00 + * @date 13. September 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask Register. + + \return Fault Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set the Fault Mask + + This function assigns the given value to the Fault Mask Register. + + \param [in] faultMask Fault Mask value value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/lib/src/common/AUDIO/VS10XX/startup_LPC17xx.c b/lib/src/common/AUDIO/VS10XX/startup_LPC17xx.c new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/startup_LPC17xx.c @@ -0,0 +1,299 @@ +/****************************************************************************//** + * @file : startup_LPC17xx.c + * @brief : CMSIS Cortex-M3 Core Device Startup File + * @version : V1.01 + * @date : 4. Feb. 2009 + * + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Mod by nio for the .fastcode part + +#include "LPC17xx.h" + +#define WEAK __attribute__ ((weak)) +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +/* System exception vector handler */ +void WEAK Reset_Handler(void); /* Reset Handler */ +void WEAK NMI_Handler(void); /* NMI Handler */ +void WEAK HardFault_Handler(void); /* Hard Fault Handler */ +void WEAK MemManage_Handler(void); /* MPU Fault Handler */ +void WEAK BusFault_Handler(void); /* Bus Fault Handler */ +void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ +void WEAK SVC_Handler(void); /* SVCall Handler */ +void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ +void WEAK PendSV_Handler(void); /* PendSV Handler */ +void WEAK SysTick_Handler(void); /* SysTick Handler */ + +/* External interrupt vector handler */ +void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ +void WEAK TIMER0_IRQHandler(void); /* Timer0 */ +void WEAK TIMER1_IRQHandler(void); /* Timer1 */ +void WEAK TIMER2_IRQHandler(void); /* Timer2 */ +void WEAK TIMER3_IRQHandler(void); /* Timer3 */ +void WEAK UART0_IRQHandler(void); /* UART0 */ +void WEAK UART1_IRQHandler(void); /* UART1 */ +void WEAK UART2_IRQHandler(void); /* UART2 */ +void WEAK UART3_IRQHandler(void); /* UART3 */ +void WEAK PWM1_IRQHandler(void); /* PWM1 */ +void WEAK I2C0_IRQHandler(void); /* I2C0 */ +void WEAK I2C1_IRQHandler(void); /* I2C1 */ +void WEAK I2C2_IRQHandler(void); /* I2C2 */ +void WEAK SPI_IRQHandler(void); /* SPI */ +void WEAK SSP0_IRQHandler(void); /* SSP0 */ +void WEAK SSP1_IRQHandler(void); /* SSP1 */ +void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ +void WEAK RTC_IRQHandler(void); /* Real Time Clock */ +void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ +void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ +void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ +void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ +void WEAK ADC_IRQHandler(void); /* A/D Converter */ +void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ +void WEAK USB_IRQHandler(void); /* USB */ +void WEAK CAN_IRQHandler(void); /* CAN */ +void WEAK DMA_IRQHandler(void); /* GP DMA */ +void WEAK I2S_IRQHandler(void); /* I2S */ +void WEAK ENET_IRQHandler(void); /* Ethernet */ +void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ +void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ +void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ +void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ + + + +/* Exported types --------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +extern unsigned long _etext; +extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ +extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ +extern unsigned long _edata; /* end address for the .data section. defined in linker script */ +extern unsigned long _sitestdata; /* start address for the initialization values of the .data section. defined in linker script */ +extern unsigned long _stestdata; /* start address for the .data section. defined in linker script */ +extern unsigned long _etestdata; + + +extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */ +extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */ +extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */ + +extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ +extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ + +extern void _estack; /* init value for the stack pointer. defined in linker script */ + +extern int bsp_init(); + +/* Private typedef -----------------------------------------------------------*/ +/* function prototypes ------------------------------------------------------*/ +void Reset_Handler(void) __attribute__((__interrupt__)); +extern int main(void); + + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ +#define STACK_SIZE 0x00000800 /*2kO*/ + +__attribute__ ((section(".stackarea"))) +/* static */ unsigned long pulStack[STACK_SIZE]; + + +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + /* &_estack, // The initial stack pointer */ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + // External Interrupts + WDT_IRQHandler, /* Watchdog Timer */ + TIMER0_IRQHandler, /* Timer0 */ + TIMER1_IRQHandler, /* Timer1 */ + TIMER2_IRQHandler, /* Timer2 */ + TIMER3_IRQHandler, /* Timer3 */ + UART0_IRQHandler, /* UART0 */ + UART1_IRQHandler, /* UART1 */ + UART2_IRQHandler, /* UART2 */ + UART3_IRQHandler, /* UART3 */ + PWM1_IRQHandler, /* PWM1 */ + I2C0_IRQHandler, /* I2C0 */ + I2C1_IRQHandler, /* I2C1 */ + I2C2_IRQHandler, /* I2C2 */ + SPI_IRQHandler, /* SPI */ + SSP0_IRQHandler, /* SSP0 */ + SSP1_IRQHandler, /* SSP1 */ + PLL0_IRQHandler, /* PLL0 (Main PLL) */ + RTC_IRQHandler, /* Real Time Clock */ + EINT0_IRQHandler, /* External Interrupt 0 */ + EINT1_IRQHandler, /* External Interrupt 1 */ + EINT2_IRQHandler, /* External Interrupt 2 */ + EINT3_IRQHandler, /* External Interrupt 3 */ + ADC_IRQHandler, /* A/D Converter */ + BOD_IRQHandler, /* Brown Out Detect */ + USB_IRQHandler, /* USB */ + CAN_IRQHandler, /* CAN */ + DMA_IRQHandler, /* GP DMA */ + I2S_IRQHandler, /* I2S */ + ENET_IRQHandler, /* Ethernet */ + RIT_IRQHandler, /* Repetitive Interrupt Timer */ + MCPWM_IRQHandler, /* Motor Control PWM */ + QEI_IRQHandler, /* Quadrature Encoder Interface */ + PLL1_IRQHandler, /* PLL1 (USB PLL) */ +}; + +/******************************************************************************* +* Function Name : Reset_Handler +* Description : This is the code that gets called when the processor first starts execution +* following a reset event. Only the absolutely necessary set is performed, +* after which the application supplied main() routine is called. +* Input : +* Output : +* Return : +*******************************************************************************/ +void Reset_Handler(void) +{ + SystemInit(); + + unsigned long *pulDest; + unsigned long *pulSrc; + + // + // Copy the data segment initializers from flash to SRAM in ROM mode + // + + if (&_sidata != &_sdata) { // only if needed + pulSrc = &_sidata; + for(pulDest = &_sdata; pulDest < &_edata; ) { + *(pulDest++) = *(pulSrc++); + } + } + if (&_sitestdata != &_stestdata) { // only if needed + pulSrc = &_sitestdata; + for(pulDest = &_stestdata; pulDest < &_etestdata; ) { + *(pulDest++) = *(pulSrc++); + } + } + + // Copy the .fastcode code from ROM to SRAM + + if (&_sifastcode != &_sfastcode) { // only if needed + pulSrc = &_sifastcode; + for(pulDest = &_sfastcode; pulDest < &_efastcode; ) { + *(pulDest++) = *(pulSrc++); + } + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_sbss; pulDest < &_ebss; ) + { + *(pulDest++) = 0; + } + + // + // Call the application's entry point. + // + bsp_init(); + main(); +} + +//***************************************************************************** +// +// Provide weak aliases for each Exception handler to the Default_Handler. +// As they are weak aliases, any function with the same name will override +// this definition. +// +//***************************************************************************** +#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ +#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ +#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ +#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ +#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ +#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ +#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ + +/* External interrupt vector handler */ +#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */ +#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */ +#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */ +#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */ +#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */ +#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */ +#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */ +#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */ +#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */ +#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */ +#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */ +#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */ +#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */ +#pragma weak SPI_IRQHandler = Default_Handler /* SPI */ +#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */ +#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */ +#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */ +#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */ +#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */ +#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */ +#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */ +#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */ +#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */ +#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */ +#pragma weak USB_IRQHandler = Default_Handler /* USB */ +#pragma weak CAN_IRQHandler = Default_Handler /* CAN */ +#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */ +#pragma weak I2S_IRQHandler = Default_Handler /* I2S */ +#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */ +#pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */ +#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */ +#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */ +#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */ + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void Default_Handler(void) { + // Go into an infinite loop. + // + while (1) { + } +} diff --git a/lib/src/common/AUDIO/VS10XX/system_LPC17xx.c b/lib/src/common/AUDIO/VS10XX/system_LPC17xx.c new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/system_LPC17xx.c @@ -0,0 +1,541 @@ +/**************************************************************************//** + * @file system_LPC17xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC17xx Device Series + * @version V1.08 + * @date 12. May 2010 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include "LPC17xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <1-256><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL0 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +// Clock Output Configuration Register (CLKOUTCFG) +// CLKOUTSEL: Selects clock source for CLKOUT +// <0=> CPU clock +// <1=> Main oscillator +// <2=> Internal RC oscillator +// <3=> USB clock +// <4=> RTC oscillator +// CLKOUTDIV: Selects clock divider for CLKOUT +// <1-16><#-1> +// CLKOUT_EN: CLKOUT enable control +// +// +// +*/ +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000000 +#define CLKSRCSEL_Val 0x00000000 +#define PLL0_SETUP 0 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 0 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x042887DE +#define CLKOUTCFG_Val 0x00000000 + + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x00005000 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if (PLL0_SETUP) /* if PLL0 is used */ + #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ + #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" + #endif +#endif + +#if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) + #error "CCLKCFG: Value out of range!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) + #error "CLKOUTCFG: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( IRC_OSC) /* Main oscillator frequency */ +//#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #else + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (OSC_CLK / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (RTC_CLK / __CCLK_DIV) + #else + #define __CORE_CLK (IRC_OSC / __CCLK_DIV) + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + +#if (PLL0_SETUP) +// LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ +// LPC_SC->PLL0FEED = 0xAA; +// LPC_SC->PLL0FEED = 0x55; + +// LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ +// LPC_SC->PLL0FEED = 0xAA; +// LPC_SC->PLL0FEED = 0x55; +// while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + +// LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ +// LPC_SC->PLL0FEED = 0xAA; +// LPC_SC->PLL0FEED = 0x55; +// while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ +#endif + + + +#if (PLL1_SETUP) +// LPC_SC->PLL1CFG = PLL1CFG_Val; +// LPC_SC->PLL1FEED = 0xAA; +// LPC_SC->PLL1FEED = 0x55; + +// LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ +// LPC_SC->PLL1FEED = 0xAA; +// LPC_SC->PLL1FEED = 0x55; +// while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ + +// LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ +// LPC_SC->PLL1FEED = 0xAA; +// LPC_SC->PLL1FEED = 0x55; +// while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ +#else + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ +#endif + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; +#endif + + + +} diff --git a/lib/src/common/AUDIO/VS10XX/vs1053.c b/lib/src/common/AUDIO/VS10XX/vs1053.c new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/vs1053.c @@ -0,0 +1,56 @@ +#/*------------------------------------------------------------------------------ +#-- This file is a part of the libuc, microcontroler library +#-- Copyright (C) 2011, Alexis Jeandet +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------- +#-- Author : Alexis Jeandet +#-- Mail : alexis.jeandet@gmail.com +#-------------------------------------------------------------------------------*/ +#include "ssp.h" +#include "vs1053.h" +//#include + +void vs1053open(vs1053Dev* codec,sspDev dev){ + codec->SSP_device = dev; + +} + +void vs1053softreset(vs1053Dev* dev) +{ + vs1053cmdwrite(dev,VSMODE,(1<<2)); +} + +int vs1053cmdread(vs1053Dev* dev,char address) +{ + int result; + while(!vs10XXDREQ()); + vs10XXclearXCS(); + sspputw(dev->SSP_device,(3<<8)+address); + result = sspgetw(dev->SSP_device); + vs10XXsetXCS(); + return result; +} + + +void vs1053cmdwrite(vs1053Dev* dev,char address,int value) +{ + while(!vs10XXDREQ()); + vs10XXclearXCS(); + sspputw(dev->SSP_device,(2<<8)+address); + sspputw(dev->SSP_device,value); + vs10XXsetXCS(); +} + diff --git a/lib/src/common/AUDIO/VS10XX/vs1053.h b/lib/src/common/AUDIO/VS10XX/vs1053.h new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/vs1053.h @@ -0,0 +1,78 @@ +/*------------------------------------------------------------------------------ +#-- This file is a part of the libuc, microcontroler library +#-- Copyright (C) 2011, Alexis Jeandet +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------- +#-- Author : Alexis Jeandet +#-- Mail : alexis.jeandet@gmail.com +#-------------------------------------------------------------------------------*/ +#ifndef VS1053_H +#define VS1053_H +#include + +#define VSMODE 0 +#define VSSTATUS 1 +#define VSBASS 2 +#define VSCLOCKF 3 +#define VSDECODE_TIME 4 +#define VSAUDATA 5 +#define VSWRAM 6 +#define VSWRAMADDR 7 +#define VSHDAT0 8 +#define VSHDAT1 9 +#define VSAIADDR 0xA +#define VSVOL 0xB +#define VSAICTRL0 0xC +#define VSAICTRL1 0xD +#define VSAICTRL2 0xE +#define VSAICTRL3 0xF + +struct vs1053Regs +{ + sspDev SSP_device; + int a; +}; + +typedef struct vs1053Regs vs1053Dev; + +void vs1053open(vs1053Dev* codec,sspDev dev); +void vs1053softreset(vs1053Dev* dev); +int vs1053cmdread(vs1053Dev* dev,char address); +void vs1053cmdwrite(vs1053Dev* dev,char address,int value); + +extern void vs10XXclearXCS(); +extern void vs10XXsetXCS(); +extern int vs10XXDREQ(); + +#endif + + + + + + + + + + + + + + + + + + diff --git a/lib/src/common/AUDIO/VS10XX/vs1053.pro b/lib/src/common/AUDIO/VS10XX/vs1053.pro new file mode 100644 --- /dev/null +++ b/lib/src/common/AUDIO/VS10XX/vs1053.pro @@ -0,0 +1,12 @@ +TEMPLATE = lib +ARCH = stm32f4-arm-none-eabi-gcc +TARGET = libvs10XX +TARGETINSTALLPATH = $(LIBUC_LIBS_DIR_VS10XX) +HEADERSINSTALLPATH = $(LIBUC_INC_DIR_VS10XX) + +LIBS += CORE SSP UHANDLE + +SOURCES += vs1053.c + + +HEADERS += vs1053.h diff --git a/lib/src/common/VS10XX/core_cm3.c b/lib/src/common/VS10XX/core_cm3.c deleted file mode 100644 --- a/lib/src/common/VS10XX/core_cm3.c +++ /dev/null @@ -1,339 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V2.00 - * @date 13. September 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask Register. - - \return Fault Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set the Fault Mask - - This function assigns the given value to the Fault Mask Register. - - \param [in] faultMask Fault Mask value value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif diff --git a/lib/src/common/VS10XX/startup_LPC17xx.c b/lib/src/common/VS10XX/startup_LPC17xx.c deleted file mode 100644 --- a/lib/src/common/VS10XX/startup_LPC17xx.c +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************//** - * @file : startup_LPC17xx.c - * @brief : CMSIS Cortex-M3 Core Device Startup File - * @version : V1.01 - * @date : 4. Feb. 2009 - * - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -// Mod by nio for the .fastcode part - -#include "LPC17xx.h" - -#define WEAK __attribute__ ((weak)) -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -/* System exception vector handler */ -void WEAK Reset_Handler(void); /* Reset Handler */ -void WEAK NMI_Handler(void); /* NMI Handler */ -void WEAK HardFault_Handler(void); /* Hard Fault Handler */ -void WEAK MemManage_Handler(void); /* MPU Fault Handler */ -void WEAK BusFault_Handler(void); /* Bus Fault Handler */ -void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ -void WEAK SVC_Handler(void); /* SVCall Handler */ -void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ -void WEAK PendSV_Handler(void); /* PendSV Handler */ -void WEAK SysTick_Handler(void); /* SysTick Handler */ - -/* External interrupt vector handler */ -void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ -void WEAK TIMER0_IRQHandler(void); /* Timer0 */ -void WEAK TIMER1_IRQHandler(void); /* Timer1 */ -void WEAK TIMER2_IRQHandler(void); /* Timer2 */ -void WEAK TIMER3_IRQHandler(void); /* Timer3 */ -void WEAK UART0_IRQHandler(void); /* UART0 */ -void WEAK UART1_IRQHandler(void); /* UART1 */ -void WEAK UART2_IRQHandler(void); /* UART2 */ -void WEAK UART3_IRQHandler(void); /* UART3 */ -void WEAK PWM1_IRQHandler(void); /* PWM1 */ -void WEAK I2C0_IRQHandler(void); /* I2C0 */ -void WEAK I2C1_IRQHandler(void); /* I2C1 */ -void WEAK I2C2_IRQHandler(void); /* I2C2 */ -void WEAK SPI_IRQHandler(void); /* SPI */ -void WEAK SSP0_IRQHandler(void); /* SSP0 */ -void WEAK SSP1_IRQHandler(void); /* SSP1 */ -void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ -void WEAK RTC_IRQHandler(void); /* Real Time Clock */ -void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ -void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ -void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ -void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ -void WEAK ADC_IRQHandler(void); /* A/D Converter */ -void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ -void WEAK USB_IRQHandler(void); /* USB */ -void WEAK CAN_IRQHandler(void); /* CAN */ -void WEAK DMA_IRQHandler(void); /* GP DMA */ -void WEAK I2S_IRQHandler(void); /* I2S */ -void WEAK ENET_IRQHandler(void); /* Ethernet */ -void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ -void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ -void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ -void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ - - - -/* Exported types --------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -extern unsigned long _etext; -extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ -extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ -extern unsigned long _edata; /* end address for the .data section. defined in linker script */ -extern unsigned long _sitestdata; /* start address for the initialization values of the .data section. defined in linker script */ -extern unsigned long _stestdata; /* start address for the .data section. defined in linker script */ -extern unsigned long _etestdata; - - -extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */ -extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */ -extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */ - -extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ -extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ - -extern void _estack; /* init value for the stack pointer. defined in linker script */ - -extern int bsp_init(); - -/* Private typedef -----------------------------------------------------------*/ -/* function prototypes ------------------------------------------------------*/ -void Reset_Handler(void) __attribute__((__interrupt__)); -extern int main(void); - - -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ -#define STACK_SIZE 0x00000800 /*2kO*/ - -__attribute__ ((section(".stackarea"))) -/* static */ unsigned long pulStack[STACK_SIZE]; - - -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - /* &_estack, // The initial stack pointer */ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - // External Interrupts - WDT_IRQHandler, /* Watchdog Timer */ - TIMER0_IRQHandler, /* Timer0 */ - TIMER1_IRQHandler, /* Timer1 */ - TIMER2_IRQHandler, /* Timer2 */ - TIMER3_IRQHandler, /* Timer3 */ - UART0_IRQHandler, /* UART0 */ - UART1_IRQHandler, /* UART1 */ - UART2_IRQHandler, /* UART2 */ - UART3_IRQHandler, /* UART3 */ - PWM1_IRQHandler, /* PWM1 */ - I2C0_IRQHandler, /* I2C0 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI_IRQHandler, /* SPI */ - SSP0_IRQHandler, /* SSP0 */ - SSP1_IRQHandler, /* SSP1 */ - PLL0_IRQHandler, /* PLL0 (Main PLL) */ - RTC_IRQHandler, /* Real Time Clock */ - EINT0_IRQHandler, /* External Interrupt 0 */ - EINT1_IRQHandler, /* External Interrupt 1 */ - EINT2_IRQHandler, /* External Interrupt 2 */ - EINT3_IRQHandler, /* External Interrupt 3 */ - ADC_IRQHandler, /* A/D Converter */ - BOD_IRQHandler, /* Brown Out Detect */ - USB_IRQHandler, /* USB */ - CAN_IRQHandler, /* CAN */ - DMA_IRQHandler, /* GP DMA */ - I2S_IRQHandler, /* I2S */ - ENET_IRQHandler, /* Ethernet */ - RIT_IRQHandler, /* Repetitive Interrupt Timer */ - MCPWM_IRQHandler, /* Motor Control PWM */ - QEI_IRQHandler, /* Quadrature Encoder Interface */ - PLL1_IRQHandler, /* PLL1 (USB PLL) */ -}; - -/******************************************************************************* -* Function Name : Reset_Handler -* Description : This is the code that gets called when the processor first starts execution -* following a reset event. Only the absolutely necessary set is performed, -* after which the application supplied main() routine is called. -* Input : -* Output : -* Return : -*******************************************************************************/ -void Reset_Handler(void) -{ - SystemInit(); - - unsigned long *pulDest; - unsigned long *pulSrc; - - // - // Copy the data segment initializers from flash to SRAM in ROM mode - // - - if (&_sidata != &_sdata) { // only if needed - pulSrc = &_sidata; - for(pulDest = &_sdata; pulDest < &_edata; ) { - *(pulDest++) = *(pulSrc++); - } - } - if (&_sitestdata != &_stestdata) { // only if needed - pulSrc = &_sitestdata; - for(pulDest = &_stestdata; pulDest < &_etestdata; ) { - *(pulDest++) = *(pulSrc++); - } - } - - // Copy the .fastcode code from ROM to SRAM - - if (&_sifastcode != &_sfastcode) { // only if needed - pulSrc = &_sifastcode; - for(pulDest = &_sfastcode; pulDest < &_efastcode; ) { - *(pulDest++) = *(pulSrc++); - } - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_sbss; pulDest < &_ebss; ) - { - *(pulDest++) = 0; - } - - // - // Call the application's entry point. - // - bsp_init(); - main(); -} - -//***************************************************************************** -// -// Provide weak aliases for each Exception handler to the Default_Handler. -// As they are weak aliases, any function with the same name will override -// this definition. -// -//***************************************************************************** -#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ -#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ -#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ -#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ -#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ -#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ -#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ - -/* External interrupt vector handler */ -#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */ -#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */ -#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */ -#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */ -#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */ -#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */ -#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */ -#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */ -#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */ -#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */ -#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */ -#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */ -#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */ -#pragma weak SPI_IRQHandler = Default_Handler /* SPI */ -#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */ -#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */ -#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */ -#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */ -#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */ -#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */ -#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */ -#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */ -#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */ -#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */ -#pragma weak USB_IRQHandler = Default_Handler /* USB */ -#pragma weak CAN_IRQHandler = Default_Handler /* CAN */ -#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */ -#pragma weak I2S_IRQHandler = Default_Handler /* I2S */ -#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */ -#pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */ -#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */ -#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */ -#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */ - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -void Default_Handler(void) { - // Go into an infinite loop. - // - while (1) { - } -} diff --git a/lib/src/common/VS10XX/system_LPC17xx.c b/lib/src/common/VS10XX/system_LPC17xx.c deleted file mode 100644 --- a/lib/src/common/VS10XX/system_LPC17xx.c +++ /dev/null @@ -1,541 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC17xx Device Series - * @version V1.08 - * @date 12. May 2010 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 24 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <1-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000000 -#define CLKSRCSEL_Val 0x00000000 -#define PLL0_SETUP 0 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 0 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x00000030)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (PLL0_SETUP) /* if PLL0 is used */ - #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ - #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" - #endif -#endif - -#if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) - #error "CCLKCFG: Value out of range!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( IRC_OSC) /* Main oscillator frequency */ -//#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) -#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) -#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else - #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (RTC_CLK / __CCLK_DIV) - #else - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #endif - #endif - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - -#if (PLL0_SETUP) -// LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; - -// LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; -// while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - -// LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ -// LPC_SC->PLL0FEED = 0xAA; -// LPC_SC->PLL0FEED = 0x55; -// while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - - - -#if (PLL1_SETUP) -// LPC_SC->PLL1CFG = PLL1CFG_Val; -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; - -// LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; -// while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - -// LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ -// LPC_SC->PLL1FEED = 0xAA; -// LPC_SC->PLL1FEED = 0x55; -// while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; -#endif - - - -} diff --git a/lib/src/common/VS10XX/vs1053.c b/lib/src/common/VS10XX/vs1053.c deleted file mode 100644 --- a/lib/src/common/VS10XX/vs1053.c +++ /dev/null @@ -1,56 +0,0 @@ -#/*------------------------------------------------------------------------------ -#-- This file is a part of the libuc, microcontroler library -#-- Copyright (C) 2011, Alexis Jeandet -#-- -#-- This program is free software; you can redistribute it and/or modify -#-- it under the terms of the GNU General Public License as published by -#-- the Free Software Foundation; either version 3 of the License, or -#-- (at your option) any later version. -#-- -#-- This program is distributed in the hope that it will be useful, -#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -#-- GNU General Public License for more details. -#-- -#-- You should have received a copy of the GNU General Public License -#-- along with this program; if not, write to the Free Software -#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -#------------------------------------------------------------------------------- -#-- Author : Alexis Jeandet -#-- Mail : alexis.jeandet@gmail.com -#-------------------------------------------------------------------------------*/ -#include "ssp.h" -#include "vs1053.h" -//#include - -void vs1053open(vs1053Dev* codec,sspDev dev){ - codec->SSP_device = dev; - -} - -void vs1053softreset(vs1053Dev* dev) -{ - vs1053cmdwrite(dev,VSMODE,(1<<2)); -} - -int vs1053cmdread(vs1053Dev* dev,char address) -{ - int result; - while(!vs10XXDREQ()); - vs10XXclearXCS(); - sspputw(dev->SSP_device,(3<<8)+address); - result = sspgetw(dev->SSP_device); - vs10XXsetXCS(); - return result; -} - - -void vs1053cmdwrite(vs1053Dev* dev,char address,int value) -{ - while(!vs10XXDREQ()); - vs10XXclearXCS(); - sspputw(dev->SSP_device,(2<<8)+address); - sspputw(dev->SSP_device,value); - vs10XXsetXCS(); -} - diff --git a/lib/src/common/VS10XX/vs1053.h b/lib/src/common/VS10XX/vs1053.h deleted file mode 100644 --- a/lib/src/common/VS10XX/vs1053.h +++ /dev/null @@ -1,78 +0,0 @@ -/*------------------------------------------------------------------------------ -#-- This file is a part of the libuc, microcontroler library -#-- Copyright (C) 2011, Alexis Jeandet -#-- -#-- This program is free software; you can redistribute it and/or modify -#-- it under the terms of the GNU General Public License as published by -#-- the Free Software Foundation; either version 3 of the License, or -#-- (at your option) any later version. -#-- -#-- This program is distributed in the hope that it will be useful, -#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -#-- GNU General Public License for more details. -#-- -#-- You should have received a copy of the GNU General Public License -#-- along with this program; if not, write to the Free Software -#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -#------------------------------------------------------------------------------- -#-- Author : Alexis Jeandet -#-- Mail : alexis.jeandet@gmail.com -#-------------------------------------------------------------------------------*/ -#ifndef VS1053_H -#define VS1053_H -#include - -#define VSMODE 0 -#define VSSTATUS 1 -#define VSBASS 2 -#define VSCLOCKF 3 -#define VSDECODE_TIME 4 -#define VSAUDATA 5 -#define VSWRAM 6 -#define VSWRAMADDR 7 -#define VSHDAT0 8 -#define VSHDAT1 9 -#define VSAIADDR 0xA -#define VSVOL 0xB -#define VSAICTRL0 0xC -#define VSAICTRL1 0xD -#define VSAICTRL2 0xE -#define VSAICTRL3 0xF - -struct vs1053Regs -{ - sspDev SSP_device; - int a; -}; - -typedef struct vs1053Regs vs1053Dev; - -void vs1053open(vs1053Dev* codec,sspDev dev); -void vs1053softreset(vs1053Dev* dev); -int vs1053cmdread(vs1053Dev* dev,char address); -void vs1053cmdwrite(vs1053Dev* dev,char address,int value); - -extern void vs10XXclearXCS(); -extern void vs10XXsetXCS(); -extern int vs10XXDREQ(); - -#endif - - - - - - - - - - - - - - - - - - diff --git a/lib/src/common/VS10XX/vs1053.pro b/lib/src/common/VS10XX/vs1053.pro deleted file mode 100644 --- a/lib/src/common/VS10XX/vs1053.pro +++ /dev/null @@ -1,12 +0,0 @@ -TEMPLATE = lib -ARCH = stm32f4-arm-none-eabi-gcc -TARGET = libvs10XX -TARGETINSTALLPATH = $(LIBUC_LIBS_DIR_VS10XX) -HEADERSINSTALLPATH = $(LIBUC_INC_DIR_VS10XX) - -LIBS += CORE SSP UHANDLE - -SOURCES += vs1053.c - - -HEADERS += vs1053.h