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1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2013, Alexis Jeandet
3 -- Copyright (C) 2013, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------*/
19 /** @author Alexis Jeandet alexis.jeandet@member.fsf.org
19 /** @author Alexis Jeandet alexis.jeandet@member.fsf.org
20 -------------------------------------------------------------------------------*/
20 -------------------------------------------------------------------------------*/
21 /**
21 /**
22 * This file is a simple example for the DAC library.
22 * This file is a simple example for the DAC library.
23 *
23 *
24 */
24 */
25
25
26 #include <stdio.h>
26 #include <stdio.h>
27 #include <uhandle.h>
27 #include <uhandle.h>
28 #include <dac.h>
28 #include <dac.h>
29 #include <timer.h>
29 #include <timer.h>
30 #include <gpio.h>
30 #include <gpio.h>
31 #include <math.h>
31 #include <math.h>
32 int16_t __attribute__ ((aligned (4))) data[512];
32 int16_t __attribute__ ((aligned (4))) data[4096];
33 int libuc_main()
33 int libuc_main()
34 {
34 {
35 /**
35 /**
36 Depending on the board the printf can be directed on one uart or LCD screen or
36 Depending on the board the printf can be directed on one uart or LCD screen or
37 any other stream device.
37 any other stream device.
38 */
38 */
39 printf("DAC example\n\r");
39 printf("DAC example \n\r");
40 for(int i=0;i<512;i++)
40 for(int i=0;i<4096;i++)
41 {
41 {
42 data[i]=(int16_t)(2000.0*cos(i/10.0))+2000.0;
42 data[i]=(2048+i)%4096;
43 }
43 }
44 data[0]=4000;
44 dacopen(PA4);
45 dacopen(PA4);
45 dacsetconfig(timer8, 512, DAC1,DAC1_12bit_right_align , 100000,(void*)data);
46 dacsetconfig(timer8, 4096, DAC1,DAC1_12bit_right_align , 100000,(void*)&data);
47 while (1);
46 return 0;
48 return 0;
47 }
49 }
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1 /* File: startup_ARMCM4.S
1 /* File: startup_ARMCM4.S
2 * Purpose: startup file for Cortex-M4 devices. Should use with
2 * Purpose: startup file for Cortex-M4 devices. Should use with
3 * GCC for ARM Embedded Processors
3 * GCC for ARM Embedded Processors
4 * Version: V2.0
4 * Version: V2.0
5 * Date: 16 August 2013
5 * Date: 16 August 2013
6 *
6 *
7 /* Copyright (c) 2011 - 2013 ARM LIMITED
7 /* Copyright (c) 2011 - 2013 ARM LIMITED
8
8
9 All rights reserved.
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
18 to endorse or promote products derived from this software without
19 specific prior written permission.
19 specific prior written permission.
20 *
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
32 ---------------------------------------------------------------------------*/
33 /*
33 /*
34 2013 Modified for libuc2 use by Alexis Jeandet.
34 2013 Modified for libuc2 use by Alexis Jeandet.
35 */
35 */
36 .syntax unified
36 .syntax unified
37 .cpu cortex-m4
37 .cpu cortex-m4
38 .fpu fpv4-sp-d16
38 .fpu fpv4-sp-d16
39
39
40 .section .stack
40 .section .stack
41 .align 3
41 .align 4
42 #ifdef __STACK_SIZE
42 #ifdef __STACK_SIZE
43 .equ Stack_Size, __STACK_SIZE
43 .equ Stack_Size, __STACK_SIZE
44 #else
44 #else
45 .equ Stack_Size, 0x2000
45 .equ Stack_Size, 0x7F00
46 #endif
46 #endif
47 .globl __StackTop
47 .globl __StackTop
48 .globl __StackLimit
48 .globl __StackLimit
49 __StackLimit:
49 __StackLimit:
50 .space Stack_Size
50 .space Stack_Size
51 .size __StackLimit, . - __StackLimit
51 .size __StackLimit, . - __StackLimit
52 __StackTop:
52 __StackTop:
53 .size __StackTop, . - __StackTop
53 .size __StackTop, . - __StackTop
54
54
55 .section .heap
55 .section .heap
56 .align 3
56 .align 3
57 #ifdef __HEAP_SIZE
57 #ifdef __HEAP_SIZE
58 .equ Heap_Size, __HEAP_SIZE
58 .equ Heap_Size, __HEAP_SIZE
59 #else
59 #else
60 .equ Heap_Size, 0x2000
60 .equ Heap_Size, 0x7F00
61 #endif
61 #endif
62 .globl __HeapBase
62 .globl __HeapBase
63 .globl __HeapLimit
63 .globl __HeapLimit
64 __HeapBase:
64 __HeapBase:
65 .if Heap_Size
65 .if Heap_Size
66 .space Heap_Size
66 .space Heap_Size
67 .endif
67 .endif
68 .size __HeapBase, . - __HeapBase
68 .size __HeapBase, . - __HeapBase
69 __HeapLimit:
69 __HeapLimit:
70 .size __HeapLimit, . - __HeapLimit
70 .size __HeapLimit, . - __HeapLimit
71
71
72 .section .isr_vector
72 .section .isr_vector
73 .align 2
73 .align 2
74 .globl __isr_vector
74 .globl __isr_vector
75 __isr_vector:
75 __isr_vector:
76 .long __StackTop /* Top of Stack */
76 .long __StackTop /* Top of Stack */
77 .long Reset_Handler /* Reset Handler */
77 .long Reset_Handler /* Reset Handler */
78 .long NMI_Handler /* NMI Handler */
78 .long NMI_Handler /* NMI Handler */
79 .long HardFault_Handler /* Hard Fault Handler */
79 .long HardFault_Handler /* Hard Fault Handler */
80 .long MemManage_Handler /* MPU Fault Handler */
80 .long MemManage_Handler /* MPU Fault Handler */
81 .long BusFault_Handler /* Bus Fault Handler */
81 .long BusFault_Handler /* Bus Fault Handler */
82 .long UsageFault_Handler /* Usage Fault Handler */
82 .long UsageFault_Handler /* Usage Fault Handler */
83 .long 0 /* Reserved */
83 .long 0 /* Reserved */
84 .long 0 /* Reserved */
84 .long 0 /* Reserved */
85 .long 0 /* Reserved */
85 .long 0 /* Reserved */
86 .long 0 /* Reserved */
86 .long 0 /* Reserved */
87 .long SVC_Handler /* SVCall Handler */
87 .long SVC_Handler /* SVCall Handler */
88 .long DebugMon_Handler /* Debug Monitor Handler */
88 .long DebugMon_Handler /* Debug Monitor Handler */
89 .long 0 /* Reserved */
89 .long 0 /* Reserved */
90 .long PendSV_Handler /* PendSV Handler */
90 .long PendSV_Handler /* PendSV Handler */
91 .long SysTick_Handler /* SysTick Handler */
91 .long SysTick_Handler /* SysTick Handler */
92
92
93 /* External interrupts */
93 /* External interrupts */
94 .word WWDG_IRQHandler /* Window WatchDog */
94 .word WWDG_IRQHandler /* Window WatchDog */
95 .word PVD_IRQHandler /* PVD through EXTI Line detection */
95 .word PVD_IRQHandler /* PVD through EXTI Line detection */
96 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
96 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
97 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
97 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
98 .word FLASH_IRQHandler /* FLASH */
98 .word FLASH_IRQHandler /* FLASH */
99 .word RCC_IRQHandler /* RCC */
99 .word RCC_IRQHandler /* RCC */
100 .word EXTI0_IRQHandler /* EXTI Line0 */
100 .word EXTI0_IRQHandler /* EXTI Line0 */
101 .word EXTI1_IRQHandler /* EXTI Line1 */
101 .word EXTI1_IRQHandler /* EXTI Line1 */
102 .word EXTI2_IRQHandler /* EXTI Line2 */
102 .word EXTI2_IRQHandler /* EXTI Line2 */
103 .word EXTI3_IRQHandler /* EXTI Line3 */
103 .word EXTI3_IRQHandler /* EXTI Line3 */
104 .word EXTI4_IRQHandler /* EXTI Line4 */
104 .word EXTI4_IRQHandler /* EXTI Line4 */
105 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
105 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
106 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
106 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
107 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
107 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
108 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
108 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
109 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
109 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
110 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
110 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
111 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
111 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
112 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
112 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
113 .word CAN1_TX_IRQHandler /* CAN1 TX */
113 .word CAN1_TX_IRQHandler /* CAN1 TX */
114 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
114 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
115 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
115 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
116 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
116 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
117 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
117 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
118 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
118 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
119 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
119 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
120 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
120 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
121 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
121 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
122 .word TIM2_IRQHandler /* TIM2 */
122 .word TIM2_IRQHandler /* TIM2 */
123 .word TIM3_IRQHandler /* TIM3 */
123 .word TIM3_IRQHandler /* TIM3 */
124 .word TIM4_IRQHandler /* TIM4 */
124 .word TIM4_IRQHandler /* TIM4 */
125 .word I2C1_EV_IRQHandler /* I2C1 Event */
125 .word I2C1_EV_IRQHandler /* I2C1 Event */
126 .word I2C1_ER_IRQHandler /* I2C1 Error */
126 .word I2C1_ER_IRQHandler /* I2C1 Error */
127 .word I2C2_EV_IRQHandler /* I2C2 Event */
127 .word I2C2_EV_IRQHandler /* I2C2 Event */
128 .word I2C2_ER_IRQHandler /* I2C2 Error */
128 .word I2C2_ER_IRQHandler /* I2C2 Error */
129 .word SPI1_IRQHandler /* SPI1 */
129 .word SPI1_IRQHandler /* SPI1 */
130 .word SPI2_IRQHandler /* SPI2 */
130 .word SPI2_IRQHandler /* SPI2 */
131 .word USART1_IRQHandler /* USART1 */
131 .word USART1_IRQHandler /* USART1 */
132 .word USART2_IRQHandler /* USART2 */
132 .word USART2_IRQHandler /* USART2 */
133 .word USART3_IRQHandler /* USART3 */
133 .word USART3_IRQHandler /* USART3 */
134 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
134 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
135 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
135 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
136 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
136 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
137 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
137 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
138 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
138 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
139 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
139 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
140 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
140 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
141 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
141 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
142 .word FSMC_IRQHandler /* FSMC */
142 .word FSMC_IRQHandler /* FSMC */
143 .word SDIO_IRQHandler /* SDIO */
143 .word SDIO_IRQHandler /* SDIO */
144 .word TIM5_IRQHandler /* TIM5 */
144 .word TIM5_IRQHandler /* TIM5 */
145 .word SPI3_IRQHandler /* SPI3 */
145 .word SPI3_IRQHandler /* SPI3 */
146 .word UART4_IRQHandler /* UART4 */
146 .word UART4_IRQHandler /* UART4 */
147 .word UART5_IRQHandler /* UART5 */
147 .word UART5_IRQHandler /* UART5 */
148 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
148 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
149 .word TIM7_IRQHandler /* TIM7 */
149 .word TIM7_IRQHandler /* TIM7 */
150 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
150 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
151 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
151 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
152 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
152 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
153 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
153 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
154 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
154 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
155 .word ETH_IRQHandler /* Ethernet */
155 .word ETH_IRQHandler /* Ethernet */
156 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
156 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
157 .word CAN2_TX_IRQHandler /* CAN2 TX */
157 .word CAN2_TX_IRQHandler /* CAN2 TX */
158 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
158 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
159 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
159 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
160 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
160 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
161 .word OTG_FS_IRQHandler /* USB OTG FS */
161 .word OTG_FS_IRQHandler /* USB OTG FS */
162 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
162 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
163 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
163 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
164 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
164 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
165 .word USART6_IRQHandler /* USART6 */
165 .word USART6_IRQHandler /* USART6 */
166 .word I2C3_EV_IRQHandler /* I2C3 event */
166 .word I2C3_EV_IRQHandler /* I2C3 event */
167 .word I2C3_ER_IRQHandler /* I2C3 error */
167 .word I2C3_ER_IRQHandler /* I2C3 error */
168 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
168 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
169 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
169 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
170 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
170 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
171 .word OTG_HS_IRQHandler /* USB OTG HS */
171 .word OTG_HS_IRQHandler /* USB OTG HS */
172 .word DCMI_IRQHandler /* DCMI */
172 .word DCMI_IRQHandler /* DCMI */
173 .word CRYP_IRQHandler /* CRYP crypto */
173 .word CRYP_IRQHandler /* CRYP crypto */
174 .word HASH_RNG_IRQHandler /* Hash and Rng */
174 .word HASH_RNG_IRQHandler /* Hash and Rng */
175 .word FPU_IRQHandler /* FPU */
175 .word FPU_IRQHandler /* FPU */
176
176
177
177
178 .size __isr_vector, . - __isr_vector
178 .size __isr_vector, . - __isr_vector
179
179
180 .text
180 .text
181 .thumb
181 .thumb
182 .thumb_func
182 .thumb_func
183 .align 2
183 .align 2
184 .globl Reset_Handler
184 .globl Reset_Handler
185 .type Reset_Handler, %function
185 .type Reset_Handler, %function
186 Reset_Handler:
186 Reset_Handler:
187 /* Firstly it copies data from read only memory to RAM. There are two schemes
187 /* Firstly it copies data from read only memory to RAM. There are two schemes
188 * to copy. One can copy more than one sections. Another can only copy
188 * to copy. One can copy more than one sections. Another can only copy
189 * one section. The former scheme needs more instructions and read-only
189 * one section. The former scheme needs more instructions and read-only
190 * data to implement than the latter.
190 * data to implement than the latter.
191 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
191 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
192
192
193 /* Single section scheme.
193 /* Single section scheme.
194 *
194 *
195 * The ranges of copy from/to are specified by following symbols
195 * The ranges of copy from/to are specified by following symbols
196 * __etext: LMA of start of the section to copy from. Usually end of text
196 * __etext: LMA of start of the section to copy from. Usually end of text
197 * __data_start__: VMA of start of the section to copy to
197 * __data_start__: VMA of start of the section to copy to
198 * __data_end__: VMA of end of the section to copy to
198 * __data_end__: VMA of end of the section to copy to
199 *
199 *
200 * All addresses must be aligned to 4 bytes boundary.
200 * All addresses must be aligned to 4 bytes boundary.
201 */
201 */
202 ldr r1, =__etext
202 ldr r1, =__etext
203 ldr r2, =__data_start__
203 ldr r2, =__data_start__
204 ldr r3, =__data_end__
204 ldr r3, =__data_end__
205
205
206 .L_loop1:
206 .L_loop1:
207 cmp r2, r3
207 cmp r2, r3
208 ittt lt
208 ittt lt
209 ldrlt r0, [r1], #4
209 ldrlt r0, [r1], #4
210 strlt r0, [r2], #4
210 strlt r0, [r2], #4
211 blt .L_loop1
211 blt .L_loop1
212
212
213 /* This part of work usually is done in C library startup code. Otherwise,
213 /* This part of work usually is done in C library startup code. Otherwise,
214 * define this macro to enable it in this startup.
214 * define this macro to enable it in this startup.
215 *
215 *
216 * There are two schemes too. One can clear multiple BSS sections. Another
216 * There are two schemes too. One can clear multiple BSS sections. Another
217 * can only clear one section. The former is more size expensive than the
217 * can only clear one section. The former is more size expensive than the
218 * latter.
218 * latter.
219 *
219 *
220 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
220 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
221 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
221 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
222 */
222 */
223
223
224 /* Single BSS section scheme.
224 /* Single BSS section scheme.
225 *
225 *
226 * The BSS section is specified by following symbols
226 * The BSS section is specified by following symbols
227 * __bss_start__: start of the BSS section.
227 * __bss_start__: start of the BSS section.
228 * __bss_end__: end of the BSS section.
228 * __bss_end__: end of the BSS section.
229 *
229 *
230 * Both addresses must be aligned to 4 bytes boundary.
230 * Both addresses must be aligned to 4 bytes boundary.
231 */
231 */
232 ldr r1, =__bss_start__
232 ldr r1, =__bss_start__
233 ldr r2, =__bss_end__
233 ldr r2, =__bss_end__
234
234
235 movs r0, 0
235 movs r0, 0
236 .L_loop3:
236 .L_loop3:
237 cmp r1, r2
237 cmp r1, r2
238 itt lt
238 itt lt
239 strlt r0, [r1], #4
239 strlt r0, [r1], #4
240 blt .L_loop3
240 blt .L_loop3
241
241
242 bl main
242 bl main
243
243
244
244
245 .pool
245 .pool
246 .size Reset_Handler, . - Reset_Handler
246 .size Reset_Handler, . - Reset_Handler
247
247
248 .align 1
248 .align 1
249 .thumb_func
249 .thumb_func
250 .weak Default_Handler
250 .weak Default_Handler
251 .type Default_Handler, %function
251 .type Default_Handler, %function
252 Default_Handler:
252 Default_Handler:
253 b .
253 b .
254 .size Default_Handler, . - Default_Handler
254 .size Default_Handler, . - Default_Handler
255
255
256 /* Macro to define default handlers. Default handler
256 /* Macro to define default handlers. Default handler
257 * will be weak symbol and just dead loops. They can be
257 * will be weak symbol and just dead loops. They can be
258 * overwritten by other handlers */
258 * overwritten by other handlers */
259 .macro def_irq_handler handler_name
259 .macro def_irq_handler handler_name
260 .weak \handler_name
260 .weak \handler_name
261 .set \handler_name, Default_Handler
261 .set \handler_name, Default_Handler
262 .endm
262 .endm
263
263
264 def_irq_handler NMI_Handler
264 def_irq_handler NMI_Handler
265 def_irq_handler HardFault_Handler
265 def_irq_handler HardFault_Handler
266 def_irq_handler MemManage_Handler
266 def_irq_handler MemManage_Handler
267 def_irq_handler BusFault_Handler
267 def_irq_handler BusFault_Handler
268 def_irq_handler UsageFault_Handler
268 def_irq_handler UsageFault_Handler
269 def_irq_handler SVC_Handler
269 def_irq_handler SVC_Handler
270 def_irq_handler DebugMon_Handler
270 def_irq_handler DebugMon_Handler
271 def_irq_handler PendSV_Handler
271 def_irq_handler PendSV_Handler
272 def_irq_handler SysTick_Handler
272 def_irq_handler SysTick_Handler
273 def_irq_handler DEF_IRQHandler
273 def_irq_handler DEF_IRQHandler
274
274
275 def_irq_handler WWDG_IRQHandler
275 def_irq_handler WWDG_IRQHandler
276 def_irq_handler PVD_IRQHandler
276 def_irq_handler PVD_IRQHandler
277 def_irq_handler TAMP_STAMP_IRQHandler
277 def_irq_handler TAMP_STAMP_IRQHandler
278 def_irq_handler RTC_WKUP_IRQHandler
278 def_irq_handler RTC_WKUP_IRQHandler
279 def_irq_handler FLASH_IRQHandler
279 def_irq_handler FLASH_IRQHandler
280 def_irq_handler RCC_IRQHandler
280 def_irq_handler RCC_IRQHandler
281 def_irq_handler EXTI0_IRQHandler
281 def_irq_handler EXTI0_IRQHandler
282 def_irq_handler EXTI1_IRQHandler
282 def_irq_handler EXTI1_IRQHandler
283 def_irq_handler EXTI2_IRQHandler
283 def_irq_handler EXTI2_IRQHandler
284 def_irq_handler EXTI3_IRQHandler
284 def_irq_handler EXTI3_IRQHandler
285 def_irq_handler EXTI4_IRQHandler
285 def_irq_handler EXTI4_IRQHandler
286 def_irq_handler DMA1_Stream0_IRQHandler
286 def_irq_handler DMA1_Stream0_IRQHandler
287 def_irq_handler DMA1_Stream1_IRQHandler
287 def_irq_handler DMA1_Stream1_IRQHandler
288 def_irq_handler DMA1_Stream2_IRQHandler
288 def_irq_handler DMA1_Stream2_IRQHandler
289 def_irq_handler DMA1_Stream3_IRQHandler
289 def_irq_handler DMA1_Stream3_IRQHandler
290 def_irq_handler DMA1_Stream4_IRQHandler
290 def_irq_handler DMA1_Stream4_IRQHandler
291 def_irq_handler DMA1_Stream5_IRQHandler
291 def_irq_handler DMA1_Stream5_IRQHandler
292 def_irq_handler DMA1_Stream6_IRQHandler
292 def_irq_handler DMA1_Stream6_IRQHandler
293 def_irq_handler ADC_IRQHandler
293 def_irq_handler ADC_IRQHandler
294 def_irq_handler CAN1_TX_IRQHandler
294 def_irq_handler CAN1_TX_IRQHandler
295 def_irq_handler CAN1_RX0_IRQHandler
295 def_irq_handler CAN1_RX0_IRQHandler
296 def_irq_handler CAN1_RX1_IRQHandler
296 def_irq_handler CAN1_RX1_IRQHandler
297 def_irq_handler CAN1_SCE_IRQHandler
297 def_irq_handler CAN1_SCE_IRQHandler
298 def_irq_handler EXTI9_5_IRQHandler
298 def_irq_handler EXTI9_5_IRQHandler
299 def_irq_handler TIM1_BRK_TIM9_IRQHandler
299 def_irq_handler TIM1_BRK_TIM9_IRQHandler
300 def_irq_handler TIM1_UP_TIM10_IRQHandler
300 def_irq_handler TIM1_UP_TIM10_IRQHandler
301 def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler
301 def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler
302 def_irq_handler TIM1_CC_IRQHandler
302 def_irq_handler TIM1_CC_IRQHandler
303 def_irq_handler TIM2_IRQHandler
303 def_irq_handler TIM2_IRQHandler
304 def_irq_handler TIM3_IRQHandler
304 def_irq_handler TIM3_IRQHandler
305 def_irq_handler TIM4_IRQHandler
305 def_irq_handler TIM4_IRQHandler
306 def_irq_handler I2C1_EV_IRQHandler
306 def_irq_handler I2C1_EV_IRQHandler
307 def_irq_handler I2C1_ER_IRQHandler
307 def_irq_handler I2C1_ER_IRQHandler
308 def_irq_handler I2C2_EV_IRQHandler
308 def_irq_handler I2C2_EV_IRQHandler
309 def_irq_handler I2C2_ER_IRQHandler
309 def_irq_handler I2C2_ER_IRQHandler
310 def_irq_handler SPI1_IRQHandler
310 def_irq_handler SPI1_IRQHandler
311 def_irq_handler SPI2_IRQHandler
311 def_irq_handler SPI2_IRQHandler
312 def_irq_handler USART1_IRQHandler
312 def_irq_handler USART1_IRQHandler
313 def_irq_handler USART2_IRQHandler
313 def_irq_handler USART2_IRQHandler
314 def_irq_handler USART3_IRQHandler
314 def_irq_handler USART3_IRQHandler
315 def_irq_handler EXTI15_10_IRQHandler
315 def_irq_handler EXTI15_10_IRQHandler
316 def_irq_handler RTC_Alarm_IRQHandler
316 def_irq_handler RTC_Alarm_IRQHandler
317 def_irq_handler OTG_FS_WKUP_IRQHandler
317 def_irq_handler OTG_FS_WKUP_IRQHandler
318 def_irq_handler TIM8_BRK_TIM12_IRQHandler
318 def_irq_handler TIM8_BRK_TIM12_IRQHandler
319 def_irq_handler TIM8_UP_TIM13_IRQHandler
319 def_irq_handler TIM8_UP_TIM13_IRQHandler
320 def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler
320 def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler
321 def_irq_handler TIM8_CC_IRQHandler
321 def_irq_handler TIM8_CC_IRQHandler
322 def_irq_handler DMA1_Stream7_IRQHandler
322 def_irq_handler DMA1_Stream7_IRQHandler
323 def_irq_handler FSMC_IRQHandler
323 def_irq_handler FSMC_IRQHandler
324 def_irq_handler SDIO_IRQHandler
324 def_irq_handler SDIO_IRQHandler
325 def_irq_handler TIM5_IRQHandler
325 def_irq_handler TIM5_IRQHandler
326 def_irq_handler SPI3_IRQHandler
326 def_irq_handler SPI3_IRQHandler
327 def_irq_handler UART4_IRQHandler
327 def_irq_handler UART4_IRQHandler
328 def_irq_handler UART5_IRQHandler
328 def_irq_handler UART5_IRQHandler
329 def_irq_handler TIM6_DAC_IRQHandler
329 def_irq_handler TIM6_DAC_IRQHandler
330 def_irq_handler TIM7_IRQHandler
330 def_irq_handler TIM7_IRQHandler
331 def_irq_handler DMA2_Stream0_IRQHandler
331 def_irq_handler DMA2_Stream0_IRQHandler
332 def_irq_handler DMA2_Stream1_IRQHandler
332 def_irq_handler DMA2_Stream1_IRQHandler
333 def_irq_handler DMA2_Stream2_IRQHandler
333 def_irq_handler DMA2_Stream2_IRQHandler
334 def_irq_handler DMA2_Stream3_IRQHandler
334 def_irq_handler DMA2_Stream3_IRQHandler
335 def_irq_handler DMA2_Stream4_IRQHandler
335 def_irq_handler DMA2_Stream4_IRQHandler
336 def_irq_handler ETH_IRQHandler
336 def_irq_handler ETH_IRQHandler
337 def_irq_handler ETH_WKUP_IRQHandler
337 def_irq_handler ETH_WKUP_IRQHandler
338 def_irq_handler CAN2_TX_IRQHandler
338 def_irq_handler CAN2_TX_IRQHandler
339 def_irq_handler CAN2_RX0_IRQHandler
339 def_irq_handler CAN2_RX0_IRQHandler
340 def_irq_handler CAN2_RX1_IRQHandler
340 def_irq_handler CAN2_RX1_IRQHandler
341 def_irq_handler CAN2_SCE_IRQHandler
341 def_irq_handler CAN2_SCE_IRQHandler
342 def_irq_handler OTG_FS_IRQHandler
342 def_irq_handler OTG_FS_IRQHandler
343 def_irq_handler DMA2_Stream5_IRQHandler
343 def_irq_handler DMA2_Stream5_IRQHandler
344 def_irq_handler DMA2_Stream6_IRQHandler
344 def_irq_handler DMA2_Stream6_IRQHandler
345 def_irq_handler DMA2_Stream7_IRQHandler
345 def_irq_handler DMA2_Stream7_IRQHandler
346 def_irq_handler USART6_IRQHandler
346 def_irq_handler USART6_IRQHandler
347 def_irq_handler I2C3_EV_IRQHandler
347 def_irq_handler I2C3_EV_IRQHandler
348 def_irq_handler I2C3_ER_IRQHandler
348 def_irq_handler I2C3_ER_IRQHandler
349 def_irq_handler OTG_HS_EP1_OUT_IRQHandler
349 def_irq_handler OTG_HS_EP1_OUT_IRQHandler
350 def_irq_handler OTG_HS_EP1_IN_IRQHandler
350 def_irq_handler OTG_HS_EP1_IN_IRQHandler
351 def_irq_handler OTG_HS_WKUP_IRQHandler
351 def_irq_handler OTG_HS_WKUP_IRQHandler
352 def_irq_handler OTG_HS_IRQHandler
352 def_irq_handler OTG_HS_IRQHandler
353 def_irq_handler DCMI_IRQHandler
353 def_irq_handler DCMI_IRQHandler
354 def_irq_handler CRYP_IRQHandler
354 def_irq_handler CRYP_IRQHandler
355 def_irq_handler HASH_RNG_IRQHandler
355 def_irq_handler HASH_RNG_IRQHandler
356 def_irq_handler FPU_IRQHandler
356 def_irq_handler FPU_IRQHandler
357
357
358 .end
358 .end
Show file before | Show file after | Hide comments
@@ -1,282 +1,281
1 #include <stdlib.h>
1 #include <stdlib.h>
2 #include <errno.h>
2 #include <errno.h>
3 #include <string.h>
3 #include <string.h>
4 #include <sys/stat.h>
4 #include <sys/stat.h>
5 #include <sys/types.h>
5 #include <sys/types.h>
6 #include <sys/times.h>
6 #include <sys/times.h>
7 #include <streamdevices.h>
7 #include <streamdevices.h>
8 #include <string.h>
8 #include <string.h>
9 #include <stdio.h>
9 #include <stdio.h>
10 #include <gpio.h>
10 #include <gpio.h>
11 #include <uart.h>
11 #include <uart.h>
12 #include <stdint.h>
12 #include <stdint.h>
13 #include <bsp.h>
13 #include <bsp.h>
14 #include <core.h>
15
14
16 #undef errno
15 #undef errno
17
16
18
17
19 #ifdef __cplusplus
18 #ifdef __cplusplus
20 extern "C" {
19 extern "C" {
21 #endif
20 #endif
22 extern int errno;
21 extern int errno;
23 extern int32_t __max_opened_files__;
22 extern int32_t __max_opened_files__;
24 extern streamdevice* __opnfiles__[];
23 extern streamdevice* __opnfiles__[];
25 extern int32_t* __fs_root__;
24 extern int32_t* __fs_root__;
26 extern int32_t __fs_root_size__;
25 extern int32_t __fs_root_size__;
27
26
28 char *__env[1] = { 0 };
27 char *__env[1] = { 0 };
29 char **environ = __env;
28 char **environ = __env;
30
29
31 int _exit()
30 int _exit()
32 {
31 {
33 while(1)
32 while(1)
34 {
33 {
35 delay_100us(10000);
34 delay_100us(10000);
36 gpioset(LED2);
35 gpioset(LED2);
37 delay_100us(10000);
36 delay_100us(10000);
38 gpioclr(LED2);
37 gpioclr(LED2);
39 }
38 }
40 }
39 }
41
40
42 int _close(int file)
41 int _close(int file)
43 {
42 {
44 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
43 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
45 {
44 {
46 return __opnfiles__[file]->ops->close( __opnfiles__[file]);
45 return __opnfiles__[file]->ops->close( __opnfiles__[file]);
47 }
46 }
48 return 0;
47 return 0;
49 }
48 }
50
49
51
50
52 int _write(int file, char *ptr, int len)
51 int _write(int file, char *ptr, int len)
53 {
52 {
54 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
53 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
55 {
54 {
56 if(__opnfiles__[file]->ops->write(__opnfiles__[file],ptr,1,len)) return len;
55 if(__opnfiles__[file]->ops->write(__opnfiles__[file],ptr,1,len)) return len;
57 }
56 }
58 return len;
57 return len;
59 }
58 }
60
59
61 int _execve(char *name, char **argv, char **env) {
60 int _execve(char *name, char **argv, char **env) {
62 errno = ENOMEM;
61 errno = ENOMEM;
63 return -1;
62 return -1;
64 }
63 }
65
64
66
65
67 int _fork(void) {
66 int _fork(void) {
68 errno = EAGAIN;
67 errno = EAGAIN;
69 return -1;
68 return -1;
70 }
69 }
71
70
72 int _fstat(int file, struct stat *st) {
71 int _fstat(int file, struct stat *st) {
73 st->st_mode = S_IFCHR;
72 st->st_mode = S_IFCHR;
74 return 0;
73 return 0;
75 }
74 }
76
75
77
76
78 int _getpid(void) {
77 int _getpid(void) {
79 return 1;
78 return 1;
80 }
79 }
81
80
82
81
83 int _isatty(int file) {
82 int _isatty(int file) {
84 return 1;
83 return 1;
85 }
84 }
86
85
87
86
88 int _kill(int pid, int sig) {
87 int _kill(int pid, int sig) {
89 errno = EINVAL;
88 errno = EINVAL;
90 return -1;
89 return -1;
91 }
90 }
92
91
93
92
94 int _link(char *old, char *_new) {
93 int _link(char *old, char *_new) {
95 errno = EMLINK;
94 errno = EMLINK;
96 return -1;
95 return -1;
97 }
96 }
98
97
99
98
100 int _lseek(int file, int ptr, int dir) {
99 int _lseek(int file, int ptr, int dir) {
101 return 0;
100 return 0;
102 }
101 }
103
102
104 #include <gpio.h>
103 #include <gpio.h>
105
104
106 int _open(const char *name, int flags, int mode)
105 int _open(const char *name, int flags, int mode)
107 {
106 {
108 if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30))
107 if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30))
109 {
108 {
110 //uart_t* uart1 = malloc(sizeof(uart_t));
109 //uart_t* uart1 = malloc(sizeof(uart_t));
111 streamdevice* fd1 = malloc(sizeof(streamdevice));
110 streamdevice* fd1 = malloc(sizeof(streamdevice));
112 uart_t uart=uartopen((name[4] & 0xF)-1);
111 uart_t uart=uartopen((name[4] & 0xF)-1);
113 if(uart!=-1);
112 if(uart!=-1);
114 {
113 {
115 uartmkstreamdev(uart,fd1);
114 uartmkstreamdev(uart,fd1);
116 int i=2;
115 int i=2;
117 while((i<__max_opened_files__) && (__opnfiles__[i]!=NULL))i++;
116 while((i<__max_opened_files__) && (__opnfiles__[i]!=NULL))i++;
118 if(i!=__max_opened_files__)
117 if(i!=__max_opened_files__)
119 {
118 {
120 __opnfiles__[i] = fd1;
119 __opnfiles__[i] = fd1;
121 return i;
120 return i;
122 }
121 }
123 else printf("Too much files opened\n\r");
122 else printf("Too much files opened\n\r");
124 }
123 }
125 }
124 }
126 return -1;
125 return -1;
127 }
126 }
128
127
129 int _read(int file, char *ptr, int len) {
128 int _read(int file, char *ptr, int len) {
130 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
129 if(file<__max_opened_files__ && __opnfiles__[file]!=NULL)
131 {
130 {
132 if(__opnfiles__[file]->ops->read(__opnfiles__[file],ptr,1,len)) return len;
131 if(__opnfiles__[file]->ops->read(__opnfiles__[file],ptr,1,len)) return len;
133 }
132 }
134 return 0;
133 return 0;
135 }
134 }
136
135
137
136
138
137
139 caddr_t _sbrk(int incr) {
138 caddr_t _sbrk(int incr) {
140 register char * stack_ptr __asm__ ("sp");
139 register char * stack_ptr __asm__ ("sp");
141 extern char end; /* Defined by the linker */
140 extern char end; /* Defined by the linker */
142 static char *heap_end;
141 static char *heap_end;
143 char *prev_heap_end;
142 char *prev_heap_end;
144 if (heap_end == 0) {
143 if (heap_end == 0) {
145 heap_end = &end;
144 heap_end = &end;
146 }
145 }
147 prev_heap_end = heap_end;
146 prev_heap_end = heap_end;
148 if (heap_end + incr > stack_ptr) {
147 if (heap_end + incr > stack_ptr) {
149 printf("Heap and stack collision\n");
148 printf("Heap and stack collision\n");
150 //abort ();
149 //abort ();
151 while(1)
150 while(1)
152 {
151 {
153 delay_100us(10000);
152 delay_100us(10000);
154 gpioset(LED2);
153 gpioset(LED2);
155 delay_100us(10000);
154 delay_100us(10000);
156 gpioclr(LED2);
155 gpioclr(LED2);
157 }
156 }
158 }
157 }
159 heap_end += incr;
158 heap_end += incr;
160 return (caddr_t) prev_heap_end;
159 return (caddr_t) prev_heap_end;
161 }
160 }
162
161
163
162
164
163
165 int _stat(char *file, struct stat *st) {
164 int _stat(char *file, struct stat *st) {
166 st->st_mode = S_IFCHR;
165 st->st_mode = S_IFCHR;
167 return 0;
166 return 0;
168 }
167 }
169
168
170
169
171 int _times(struct tms *buf) {
170 int _times(struct tms *buf) {
172 return -1;
171 return -1;
173 }
172 }
174
173
175
174
176 int _unlink(char *name) {
175 int _unlink(char *name) {
177 errno = ENOENT;
176 errno = ENOENT;
178 return -1;
177 return -1;
179 }
178 }
180
179
181 int _wait(int *status) {
180 int _wait(int *status) {
182 errno = ECHILD;
181 errno = ECHILD;
183 return -1;
182 return -1;
184 }
183 }
185
184
186
185
187 int _read_r (struct _reent *r, int file, char * ptr, int len)
186 int _read_r (struct _reent *r, int file, char * ptr, int len)
188 {
187 {
189 r = r;
188 r = r;
190 file = file;
189 file = file;
191 ptr = ptr;
190 ptr = ptr;
192 len = len;
191 len = len;
193 _read(file,ptr,len);
192 _read(file,ptr,len);
194 errno = EINVAL;
193 errno = EINVAL;
195 return -1;
194 return -1;
196 }
195 }
197
196
198 /***************************************************************************/
197 /***************************************************************************/
199
198
200 int _lseek_r (struct _reent *r, int file, int ptr, int dir)
199 int _lseek_r (struct _reent *r, int file, int ptr, int dir)
201 {
200 {
202 r = r;
201 r = r;
203 file = file;
202 file = file;
204 ptr = ptr;
203 ptr = ptr;
205 dir = dir;
204 dir = dir;
206
205
207 return 0;
206 return 0;
208 }
207 }
209
208
210 /***************************************************************************/
209 /***************************************************************************/
211
210
212 int _write_r (struct _reent *r, int file, char * ptr, int len)
211 int _write_r (struct _reent *r, int file, char * ptr, int len)
213 {
212 {
214 return _write(file, ptr, len);
213 return _write(file, ptr, len);
215 }
214 }
216
215
217 /***************************************************************************/
216 /***************************************************************************/
218
217
219 int _close_r (struct _reent *r, int file)
218 int _close_r (struct _reent *r, int file)
220 {
219 {
221 return 0;
220 return 0;
222 }
221 }
223
222
224 /***************************************************************************/
223 /***************************************************************************/
225
224
226 caddr_t _sbrk_r (struct _reent *r, int incr)
225 caddr_t _sbrk_r (struct _reent *r, int incr)
227 {
226 {
228 register char * stack_ptr __asm__ ("sp");
227 register char * stack_ptr __asm__ ("sp");
229 extern char end; /* Defined by the linker */
228 extern char end; /* Defined by the linker */
230 static char *heap_end;
229 static char *heap_end;
231 char *prev_heap_end;
230 char *prev_heap_end;
232 if (heap_end == 0) {
231 if (heap_end == 0) {
233 heap_end = &end;
232 heap_end = &end;
234 }
233 }
235 prev_heap_end = heap_end;
234 prev_heap_end = heap_end;
236 if (heap_end + incr > stack_ptr) {
235 if (heap_end + incr > stack_ptr) {
237 printf( "Heap and stack collision\n");
236 printf( "Heap and stack collision\n");
238 //abort ();
237 //abort ();
239 while(1)
238 while(1)
240 {
239 {
241 delay_100us(10000);
240 delay_100us(10000);
242 gpioset(LED2);
241 gpioset(LED2);
243 delay_100us(10000);
242 delay_100us(10000);
244 gpioclr(LED2);
243 gpioclr(LED2);
245 }
244 }
246 }
245 }
247 heap_end += incr;
246 heap_end += incr;
248 return (caddr_t) prev_heap_end;
247 return (caddr_t) prev_heap_end;
249 }
248 }
250
249
251 /***************************************************************************/
250 /***************************************************************************/
252
251
253 int _fstat_r (struct _reent *r, int file, struct stat * st)
252 int _fstat_r (struct _reent *r, int file, struct stat * st)
254 {
253 {
255 r = r;
254 r = r;
256 file = file;
255 file = file;
257
256
258 memset (st, 0, sizeof (* st));
257 memset (st, 0, sizeof (* st));
259 st->st_mode = S_IFCHR;
258 st->st_mode = S_IFCHR;
260 return 0;
259 return 0;
261 }
260 }
262
261
263 /***************************************************************************/
262 /***************************************************************************/
264 int _open_r(struct _reent *r,const char *name, int flags, int mode)
263 int _open_r(struct _reent *r,const char *name, int flags, int mode)
265 {
264 {
266 return _open(name, flags, mode);
265 return _open(name, flags, mode);
267 }
266 }
268
267
269 int _isatty_r(struct _reent *r, int fd)
268 int _isatty_r(struct _reent *r, int fd)
270 {
269 {
271 r = r;
270 r = r;
272 fd = fd;
271 fd = fd;
273
272
274 return 1;
273 return 1;
275 }
274 }
276
275
277
276
278 #ifdef __cplusplus
277 #ifdef __cplusplus
279 }
278 }
280 #endif
279 #endif
281
280
282
281
Show file before | Show file after | Hide comments
@@ -1,379 +1,379
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
20 -- Mail : alexis.jeandet@member.fsf.org
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22 #include <core.h>
22 #include <core.h>
23 #include <stm32f4xx_rcc.h>
23 #include <stm32f4xx_rcc.h>
24 #include <stdlib.h>
24 #include <stdlib.h>
25 #include <stdio.h>
25 #include <stdio.h>
26 #include <core_cm4.h>
26 #include <core_cm4.h>
27 #include <gpio.h>
27 #include <gpio.h>
28
28
29
29
30 extern uint32_t OSC0;
30 extern uint32_t OSC0;
31 extern uint32_t INTOSC;
31 extern uint32_t INTOSC;
32 extern uint32_t RTCOSC;
32 extern uint32_t RTCOSC;
33 extern gpio_t TickLed;
33 extern gpio_t TickLed;
34
34
35 volatile uint32_t tickCounter=0;
35 volatile uint32_t tickCounter=0;
36
36
37
37
38 void SysTick_Handler(void)
38 void SysTick_Handler(void)
39 {
39 {
40 tickCounter+=1;
40 tickCounter+=1;
41 if((tickCounter&0xFFF)==0x800)
41 if((tickCounter&0xFFF)==0x800)
42 gpiosetval(TickLed,!gpiogetval(TickLed));
42 gpiosetval(TickLed,!gpiogetval(TickLed));
43 }
43 }
44
44
45 void delay_us(uint32_t value)
45 void delay_us(uint32_t value)
46 {
46 {
47 extern uint32_t currentCpuFreq;
47 extern uint32_t currentCpuFreq;
48 if(value)
48 if(value)
49 {
49 {
50 uint32_t tickperus=currentCpuFreq/(1000*10);
50 uint32_t tickperus=currentCpuFreq/(1000*10);
51 uint32_t tickCounterSnap = SysTick->VAL+((value%100)*tickperus);
51 uint32_t tickCounterSnap = SysTick->VAL+((value%100)*tickperus);
52 uint32_t targetVal=tickCounterSnap +(value/100);
52 uint32_t targetVal=tickCounterSnap +(value/100);
53 if(targetVal < tickCounterSnap)
53 if(targetVal < tickCounterSnap)
54 {
54 {
55 while(tickCounter > targetVal);
55 while(tickCounter > targetVal);
56 }
56 }
57 while((tickCounter < targetVal) | (SysTick->VAL<tickCounterSnap));
57 while((tickCounter < targetVal) | (SysTick->VAL<tickCounterSnap));
58 }
58 }
59 }
59 }
60
60
61 void delay_100us(uint32_t value)
61 void delay_100us(uint32_t value)
62 {
62 {
63 if(value)
63 if(value)
64 {
64 {
65 uint32_t tickCounterSnap = tickCounter;
65 uint32_t tickCounterSnap = tickCounter;
66 uint32_t SysTickSnap = SysTick->VAL;
66 uint32_t SysTickSnap = SysTick->VAL;
67 uint32_t targetVal=tickCounterSnap +(value);
67 uint32_t targetVal=tickCounterSnap +(value);
68 if(targetVal < tickCounterSnap)
68 if(targetVal < tickCounterSnap)
69 {
69 {
70 while(tickCounter > targetVal);
70 while(tickCounter > targetVal);
71 }
71 }
72 while((tickCounter < targetVal) | (SysTick->VAL<SysTickSnap));
72 while((tickCounter < targetVal) | (SysTick->VAL<SysTickSnap));
73 }
73 }
74 }
74 }
75
75
76 uint32_t getAPB1Freq()
76 uint32_t getAPB1Freq()
77 {
77 {
78 RCC_ClocksTypeDef RCC_ClocksStatus;
78 RCC_ClocksTypeDef RCC_ClocksStatus;
79 RCC_GetClocksFreq(&RCC_ClocksStatus);
79 RCC_GetClocksFreq(&RCC_ClocksStatus);
80 return RCC_ClocksStatus.PCLK1_Frequency;
80 return RCC_ClocksStatus.PCLK1_Frequency;
81 }
81 }
82
82
83 uint32_t getAPB2Freq()
83 uint32_t getAPB2Freq()
84 {
84 {
85 RCC_ClocksTypeDef RCC_ClocksStatus;
85 RCC_ClocksTypeDef RCC_ClocksStatus;
86 RCC_GetClocksFreq(&RCC_ClocksStatus);
86 RCC_GetClocksFreq(&RCC_ClocksStatus);
87 return RCC_ClocksStatus.PCLK2_Frequency;
87 return RCC_ClocksStatus.PCLK2_Frequency;
88 }
88 }
89
89
90
90
91 uint32_t getCpuFreq()
91 uint32_t getCpuFreq()
92 {
92 {
93 uint32_t cpufreq = OSC0;
93 uint32_t _freq_ = OSC0;
94 uint32_t PLLN,PLLM,PLLP;
94 uint32_t PLLN,PLLM,PLLP;
95
95
96 if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
96 if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
97 {
97 {
98 uint32_t pllinput=INTOSC;
98 uint32_t _pllin_=INTOSC;
99 if((RCC->PLLCFGR & (1<<22)) == (1<<22))
99 if((RCC->PLLCFGR & (1<<22)) == (1<<22))
100 {
100 {
101 pllinput=OSC0;
101 _pllin_=OSC0;
102 }
102 }
103 PLLN = (RCC->PLLCFGR>>6) & 0x1FF;
103 PLLN = (RCC->PLLCFGR>>6) & 0x1FF;
104 PLLM = RCC->PLLCFGR & 0x3F;
104 PLLM = RCC->PLLCFGR & 0x3F;
105 PLLP = 1<<(((RCC->PLLCFGR>>16) & 3 )+1);
105 PLLP = 1<<(((RCC->PLLCFGR>>16) & 3 )+1);
106 cpufreq = (pllinput * PLLN )/(PLLM*PLLP);
106 _freq_ = (_pllin_ * PLLN )/(PLLM*PLLP);
107 }
107 }
108 else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
108 else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
109 {
109 {
110 cpufreq=INTOSC;
110 _freq_=INTOSC;
111 }
111 }
112 if((RCC->CFGR & (1<<7))==1<<7)
112 if((RCC->CFGR & (1<<7))==(1<<7))
113 {
113 {
114 return cpufreq>>((RCC->CFGR & (7<<4))>>4);
114 return _freq_>>((RCC->CFGR & (7<<4))>>4);
115 }
115 }
116 return cpufreq;
116 return _freq_;
117 }
117 }
118
118
119 void reset_AHB1()
119 void reset_AHB1()
120 {
120 {
121 RCC->AHB1RSTR = -1;
121 RCC->AHB1RSTR = -1;
122 RCC->AHB1RSTR = 0;
122 RCC->AHB1RSTR = 0;
123 }
123 }
124
124
125 void reset_AHB2()
125 void reset_AHB2()
126 {
126 {
127 RCC->AHB2RSTR = -1;
127 RCC->AHB2RSTR = -1;
128 RCC->AHB2RSTR = 0;
128 RCC->AHB2RSTR = 0;
129 }
129 }
130
130
131 void reset_APB1()
131 void reset_APB1()
132 {
132 {
133 RCC->APB1RSTR = -1;
133 RCC->APB1RSTR = -1;
134 RCC->APB1RSTR = 0;
134 RCC->APB1RSTR = 0;
135 }
135 }
136
136
137 void reset_APB2()
137 void reset_APB2()
138 {
138 {
139 RCC->APB2RSTR = -1;
139 RCC->APB2RSTR = -1;
140 RCC->APB2RSTR = 0;
140 RCC->APB2RSTR = 0;
141 }
141 }
142
142
143
143
144
144
145 /*
145 /*
146 | 2.7->3.6V
146 | 2.7->3.6V
147 -------------------------
147 -------------------------
148 0WS | 0<HCLK<=30
148 0WS | 0<HCLK<=30
149 1WS | 30<HCLK<=60
149 1WS | 30<HCLK<=60
150 2WS | 60<HCLK<=90
150 2WS | 60<HCLK<=90
151 3WS | 90<HCLK<=120
151 3WS | 90<HCLK<=120
152 4WS | 120<HCLK<=150
152 4WS | 120<HCLK<=150
153 5WS | 150<HCLK<=168
153 5WS | 150<HCLK<=168
154
154
155 f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) [1]
155 f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) [1]
156 64MHz <= f(VCO clock) <= 432MHz [2]
156 64MHz <= f(VCO clock) <= 432MHz [2]
157
157
158 f(VCO clock input) must be between 1MHz and 2MHz and as close to 2MHz as possible!! [3]
158 f(VCO clock input) must be between 1MHz and 2MHz and as close to 2MHz as possible!! [3]
159
159
160 f(PLL general clock output) = f(VCO clock) / PLLP [4]
160 f(PLL general clock output) = f(VCO clock) / PLLP [4]
161
161
162 CPU<168MHz AHB1<168MHz AHB2<168MHz APB1<42MHz APB2<84MHz [5]
162 CPU<168MHz AHB1<168MHz AHB2<168MHz APB1<42MHz APB2<84MHz [5]
163
163
164 ! 63<=PLLN<=432 [6]
164 ! 63<=PLLN<=432 [6]
165 ! 2<=PLLM<=63 [7]
165 ! 2<=PLLM<=63 [7]
166 ! PLLP=2,4,6,8 [8]
166 ! PLLP=2,4,6,8 [8]
167 4<=PLLM*PLLP<=504
167 4<=PLLM*PLLP<=504
168
168
169 F= f(PLL clock input) * A/B with
169 F= f(PLL clock input) * A/B with
170 63<=A<=432
170 63<=A<=432
171 4<=B<=504
171 4<=B<=504
172
172
173 */
173 */
174
174
175
175
176 int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx)
176 int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx)
177 {
177 {
178 uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
178 uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
179 uint32_t AHBPR=0,AHBPR_r=0,PLLN_r=0,PLLP_r=0;
179 uint32_t AHBPR=0,AHBPR_r=0,PLLN_r=0,PLLP_r=0;
180 uint32_t Fplli=0;
180 uint32_t Fplli=0;
181 int32_t f_error=100000000;
181 int32_t f_error=100000000;
182 int32_t f_errornw=100000000;
182 int32_t f_errornw=100000000;
183 Fplli = srcfreq / PLLM;
183 Fplli = srcfreq / PLLM;
184 //not efficient but should find the best parameters
184 //not efficient but should find the best parameters
185 for((*AHBPRindx)=0;(*AHBPRindx)<9;(*AHBPRindx)++) //lowest priority
185 for((*AHBPRindx)=0;(*AHBPRindx)<9;(*AHBPRindx)++) //lowest priority
186 {
186 {
187 AHBPR = AHBPRtbl[(*AHBPRindx)];
187 AHBPR = AHBPRtbl[(*AHBPRindx)];
188 for(*PLLP=2;*PLLP<9;*PLLP+=2)
188 for(*PLLP=2;*PLLP<9;*PLLP+=2)
189 {
189 {
190 *PLLN = (freq*(*PLLP)*AHBPR)/Fplli;
190 *PLLN = (freq*(*PLLP)*AHBPR)/Fplli;
191 if(((*PLLN)>62) && ((*PLLN)<433) && ((Fplli * (*PLLN)) < 433000000))
191 if(((*PLLN)>62) && ((*PLLN)<433) && ((Fplli * (*PLLN)) < 433000000))
192 {
192 {
193 f_errornw = abs((int32_t)((int32_t)((Fplli*(*PLLN))/((*PLLP)*AHBPR))-freq));
193 f_errornw = abs((int32_t)((int32_t)((Fplli*(*PLLN))/((*PLLP)*AHBPR))-freq));
194 if( ( (f_error)>(f_errornw) ) || ( (*AHBPRindx==0)&&(*PLLP==2)&&(*PLLN==63) ) )
194 if( ( (f_error)>(f_errornw) ) || ( (*AHBPRindx==0)&&(*PLLP==2)&&(*PLLN==63) ) )
195 {
195 {
196 f_error=f_errornw;
196 f_error=f_errornw;
197 PLLN_r = *PLLN;
197 PLLN_r = *PLLN;
198 PLLP_r = *PLLP;
198 PLLP_r = *PLLP;
199 AHBPR_r=*AHBPRindx;
199 AHBPR_r=*AHBPRindx;
200 if(f_error==0)
200 if(f_error==0)
201 {
201 {
202 *PLLN = PLLN_r;
202 *PLLN = PLLN_r;
203 *PLLP = PLLP_r;
203 *PLLP = PLLP_r;
204 *AHBPRindx = AHBPR_r;
204 *AHBPRindx = AHBPR_r;
205 return 1;
205 return 1;
206 }
206 }
207 }
207 }
208 }
208 }
209 }
209 }
210 }
210 }
211 *PLLN = PLLN_r;
211 *PLLN = PLLN_r;
212 *PLLP = PLLP_r;
212 *PLLP = PLLP_r;
213 *AHBPRindx = AHBPR_r;
213 *AHBPRindx = AHBPR_r;
214 return 1;
214 return 1;
215 }
215 }
216
216
217
217
218 int setPll(uint32_t freq)
218 int setPll(uint32_t freq)
219 {
219 {
220 extern uint32_t OSC0;
220 extern uint32_t OSC0;
221 extern uint32_t INTOSC;
221 extern uint32_t INTOSC;
222 uint32_t srcfreq = INTOSC;
222 uint32_t srcfreq = INTOSC;
223 uint8_t AHBPRindx;
223 uint8_t AHBPRindx;
224 uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
224 uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
225 uint32_t PLLN=0,PLLM=0,PLLP=0,AHBPR=0;
225 uint32_t PLLN=0,PLLM=0,PLLP=0,AHBPR=0;
226 uint32_t Fplli=0;
226 uint32_t Fplli=0;
227 if((RCC->PLLCFGR & (1<<22))==(1<<22))
227 if((RCC->PLLCFGR & (1<<22))==(1<<22))
228 {
228 {
229 srcfreq = OSC0;
229 srcfreq = OSC0;
230 }
230 }
231 PLLM = srcfreq / 1500000; // [3]
231 PLLM = srcfreq / 1500000; // [3]
232 Fplli = srcfreq / PLLM;
232 Fplli = srcfreq / PLLM;
233 optimizePLLcfg(freq,srcfreq,PLLM,&PLLP,&PLLN,&AHBPRindx);
233 optimizePLLcfg(freq,srcfreq,PLLM,&PLLP,&PLLN,&AHBPRindx);
234 srcfreq = (Fplli*PLLN)/(PLLP*AHBPRtbl[AHBPRindx]); //Put real clk freq in srcfreq for return value
234 srcfreq = (Fplli*PLLN)/(PLLP*AHBPRtbl[AHBPRindx]); //Put real clk freq in srcfreq for return value
235 //now switch to HSIs
235 //now switch to HSIs
236 if((RCC->CR & 1)==0)RCC->CR |= 1; //turn ON HSI
236 if((RCC->CR & 1)==0)RCC->CR |= 1; //turn ON HSI
237 while((RCC->CR & 2)!=2); //wait for HSI Ready
237 while((RCC->CR & 2)!=2); //wait for HSI Ready
238 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
238 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
239 RCC->CFGR |= RCC_CFGR_SW_HSI; //set HSI as main clk
239 RCC->CFGR |= RCC_CFGR_SW_HSI; //set HSI as main clk
240 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI);
240 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI);
241 RCC->CR &= ~(1<<24); //Turn OFF PLL
241 RCC->CR &= ~(1<<24); //Turn OFF PLL
242 RCC->PLLCFGR &= ~0x37FFF; //clear PLLP PLLM PLLN
242 RCC->PLLCFGR &= ~0x37FFF; //clear PLLP PLLM PLLN
243 RCC->PLLCFGR |= PLLM + (PLLN<<6) + (((PLLP>>1) -1)<<16);
243 RCC->PLLCFGR |= PLLM + (PLLN<<6) + (((PLLP>>1) -1)<<16);
244 RCC->CR |= RCC_CR_PLLON; //Turn ON PLL
244 RCC->CR |= RCC_CR_PLLON; //Turn ON PLL
245 while((RCC->CR & (1<<25))!=(1<<25)); //wait for PLL Ready
245 while((RCC->CR & (1<<25))!=(1<<25)); //wait for PLL Ready
246 if(AHBPRindx!=0)AHBPRindx|=0x8;
246 if(AHBPRindx!=0)AHBPRindx|=0x8;
247 RCC->CFGR &= ~(0xF<<4);
247 RCC->CFGR &= ~(0xF<<4);
248 RCC->CFGR |= (uint32_t)(AHBPRindx<<4);
248 RCC->CFGR |= (uint32_t)(AHBPRindx<<4);
249 AHBPR=0;
249 AHBPR=0;
250 while((srcfreq>>AHBPR)>42000000)AHBPR++; //[5] //Thune APB1 prescaler to keep APB1 CLK below 42MHz
250 while((srcfreq>>AHBPR)>42000000)AHBPR++; //[5] //Thune APB1 prescaler to keep APB1 CLK below 42MHz
251 if(AHBPR!=0)
251 if(AHBPR!=0)
252 {
252 {
253 AHBPR-=1;
253 AHBPR-=1;
254 AHBPR|=0x4;
254 AHBPR|=0x4;
255 }
255 }
256 RCC->CFGR &= ~(0x7<<10);
256 RCC->CFGR &= ~(0x7<<10);
257 RCC->CFGR |= (uint32_t)(AHBPR<<10);
257 RCC->CFGR |= (uint32_t)(AHBPR<<10);
258 AHBPR=0;
258 AHBPR=0;
259 while((srcfreq>>AHBPR)>84000000)AHBPR++; //[5] //Thune APB2 prescaler to keep APB2 CLK below 42MHz
259 while((srcfreq>>AHBPR)>84000000)AHBPR++; //[5] //Thune APB2 prescaler to keep APB2 CLK below 42MHz
260 if(AHBPR!=0)
260 if(AHBPR!=0)
261 {
261 {
262 AHBPR-=1;
262 AHBPR-=1;
263 AHBPR|=0x4;
263 AHBPR|=0x4;
264 }
264 }
265 RCC->CFGR &= ~(0x7<<13);
265 RCC->CFGR &= ~(0x7<<13);
266 RCC->CFGR |= (uint32_t)(AHBPR<<13);
266 RCC->CFGR |= (uint32_t)(AHBPR<<13);
267 FLASH->ACR |= FLASH_ACR_LATENCY_7WS;
267 FLASH->ACR |= FLASH_ACR_LATENCY_7WS;
268 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//Switch to PLL as main clk source
268 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//Switch to PLL as main clk source
269 RCC->CFGR |= RCC_CFGR_SW_PLL;
269 RCC->CFGR |= RCC_CFGR_SW_PLL;
270 /* Wait untill the main PLL is used as system clock source */
270 /* Wait untill the main PLL is used as system clock source */
271 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
271 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
272 if(srcfreq>150000000)
272 if(srcfreq>150000000)
273 {
273 {
274 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_5WS;
274 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_5WS;
275 }
275 }
276 if((srcfreq<150000000) && (srcfreq>=120000000))
276 if((srcfreq<150000000) && (srcfreq>=120000000))
277 {
277 {
278 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_4WS;
278 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_4WS;
279 }
279 }
280 if((srcfreq<120000000) && (srcfreq>=90000000))
280 if((srcfreq<120000000) && (srcfreq>=90000000))
281 {
281 {
282 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_3WS;
282 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_3WS;
283 }
283 }
284 if((srcfreq<90000000) && (srcfreq>=60000000))
284 if((srcfreq<90000000) && (srcfreq>=60000000))
285 {
285 {
286 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_2WS;
286 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_2WS;
287 }
287 }
288 if((srcfreq<60000000) && (srcfreq>=30000000))
288 if((srcfreq<60000000) && (srcfreq>=30000000))
289 {
289 {
290 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_1WS;
290 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_1WS;
291 }
291 }
292 if(srcfreq<30000000)
292 if(srcfreq<30000000)
293 {
293 {
294 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_0WS;
294 FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_0WS;
295 }
295 }
296 return srcfreq;
296 return srcfreq;
297 }
297 }
298
298
299 void configureSysTick()
299 void configureSysTick()
300 {
300 {
301 extern uint32_t currentCpuFreq;
301 extern uint32_t currentCpuFreq;
302 uint32_t us=currentCpuFreq/(1000*10);
302 uint32_t us=currentCpuFreq/(1000*10);
303 SysTick_Config(us);
303 SysTick_Config(us);
304 }
304 }
305
305
306 int setCpuFreq(uint32_t freq)
306 int setCpuFreq(uint32_t freq)
307 {
307 {
308 extern uint32_t OSC0;
308 extern uint32_t OSC0;
309 extern uint32_t INTOSC;
309 extern uint32_t INTOSC;
310 uint8_t i=0;
310 uint8_t i=0;
311 uint32_t curentFeq = getCpuFreq();
311 uint32_t curentFeq = getCpuFreq();
312 if(curentFeq==freq)return curentFeq;
312 if(curentFeq==freq)return curentFeq;
313 if((freq>2000000) && (freq<=250000000)) //be carefull with 250MHz!!!
313 if((freq>2000000) && (freq<=250000000)) //be carefull with 250MHz!!!
314 {
314 {
315 if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
315 if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
316 {
316 {
317 return setPll(freq);
317 return setPll(freq);
318 }
318 }
319 else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
319 else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
320 {
320 {
321 if((INTOSC%freq)==0) //now check if we can directly divide HSI
321 if((INTOSC%freq)==0) //now check if we can directly divide HSI
322 {
322 {
323 if(freq==INTOSC)
323 if(freq==INTOSC)
324 {
324 {
325 RCC->CFGR &= ~(0xF<<4);
325 RCC->CFGR &= ~(0xF<<4);
326 return freq;
326 return freq;
327 }
327 }
328 for(i=1;i<8;i++)
328 for(i=1;i<8;i++)
329 {
329 {
330 if((freq<<i)==INTOSC)
330 if((freq<<i)==INTOSC)
331 {
331 {
332 RCC->CFGR &= ~(0xF<<4);
332 RCC->CFGR &= ~(0xF<<4);
333 RCC->CFGR |= ((0x8|i)<<4);
333 RCC->CFGR |= ((0x8|i)<<4);
334 return freq;
334 return freq;
335 }
335 }
336 }
336 }
337 }
337 }
338 else
338 else
339 return setPll(freq);
339 return setPll(freq);
340 }
340 }
341 else //HSE used as sys clk
341 else //HSE used as sys clk
342 {
342 {
343 if((OSC0%freq)==0) //now check if we can directly divide HSI
343 if((OSC0%freq)==0) //now check if we can directly divide HSI
344 {
344 {
345 if(freq==OSC0)
345 if(freq==OSC0)
346 {
346 {
347 RCC->CFGR &= ~(0xF<<4);
347 RCC->CFGR &= ~(0xF<<4);
348 return freq;
348 return freq;
349 }
349 }
350 for(i=1;i<8;i++)
350 for(i=1;i<8;i++)
351 {
351 {
352 if((freq<<i)==OSC0)
352 if((freq<<i)==OSC0)
353 {
353 {
354 RCC->CFGR &= ~(0xF<<4);
354 RCC->CFGR &= ~(0xF<<4);
355 RCC->CFGR |= ((0x8|i)<<4);
355 RCC->CFGR |= ((0x8|i)<<4);
356 return freq;
356 return freq;
357 }
357 }
358 }
358 }
359 }
359 }
360 else
360 else
361 return setPll(freq);
361 return setPll(freq);
362 }
362 }
363 }
363 }
364 return 0;
364 return 0;
365 }
365 }
366
366
367
367
368 void enable_FPU()
368 void enable_FPU()
369 {
369 {
370 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
370 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
371 __asm__("dsb");
371 __asm__("dsb");
372 __asm__("isb");
372 __asm__("isb");
373 }
373 }
374
374
375
375
376
376
377
377
378
378
379
379
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1 /* File: startup_ARMCM4.S
1 /* File: startup_ARMCM4.S
2 * Purpose: startup file for Cortex-M4 devices. Should use with
2 * Purpose: startup file for Cortex-M4 devices. Should use with
3 * GCC for ARM Embedded Processors
3 * GCC for ARM Embedded Processors
4 * Version: V2.0
4 * Version: V2.0
5 * Date: 16 August 2013
5 * Date: 16 August 2013
6 *
6 *
7 /* Copyright (c) 2011 - 2013 ARM LIMITED
7 /* Copyright (c) 2011 - 2013 ARM LIMITED
8
8
9 All rights reserved.
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
18 to endorse or promote products derived from this software without
19 specific prior written permission.
19 specific prior written permission.
20 *
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
32 ---------------------------------------------------------------------------*/
33 /*
33 /*
34 2013 Modified for libuc2 use by Alexis Jeandet.
34 2013 Modified for libuc2 use by Alexis Jeandet.
35 */
35 */
36 .syntax unified
36 .syntax unified
37 .cpu cortex-m4
37 .cpu cortex-m4
38 .fpu fpv4-sp-d16
38 .fpu fpv4-sp-d16
39
39
40 .section .stack
40 .section .stack
41 .align 3
41 .align 3
42 #ifdef __STACK_SIZE
42 #ifdef __STACK_SIZE
43 .equ Stack_Size, __STACK_SIZE
43 .equ Stack_Size, __STACK_SIZE
44 #else
44 #else
45 .equ Stack_Size, 0x2000
45 .equ Stack_Size, 0x7F00
46 #endif
46 #endif
47 .globl __StackTop
47 .globl __StackTop
48 .globl __StackLimit
48 .globl __StackLimit
49 __StackLimit:
49 __StackLimit:
50 .space Stack_Size
50 .space Stack_Size
51 .size __StackLimit, . - __StackLimit
51 .size __StackLimit, . - __StackLimit
52 __StackTop:
52 __StackTop:
53 .size __StackTop, . - __StackTop
53 .size __StackTop, . - __StackTop
54
54
55 .section .heap
55 .section .heap
56 .align 3
56 .align 3
57 #ifdef __HEAP_SIZE
57 #ifdef __HEAP_SIZE
58 .equ Heap_Size, __HEAP_SIZE
58 .equ Heap_Size, __HEAP_SIZE
59 #else
59 #else
60 .equ Heap_Size, 0x2000
60 .equ Heap_Size, 0x7F00
61 #endif
61 #endif
62 .globl __HeapBase
62 .globl __HeapBase
63 .globl __HeapLimit
63 .globl __HeapLimit
64 __HeapBase:
64 __HeapBase:
65 .if Heap_Size
65 .if Heap_Size
66 .space Heap_Size
66 .space Heap_Size
67 .endif
67 .endif
68 .size __HeapBase, . - __HeapBase
68 .size __HeapBase, . - __HeapBase
69 __HeapLimit:
69 __HeapLimit:
70 .size __HeapLimit, . - __HeapLimit
70 .size __HeapLimit, . - __HeapLimit
71
71
72 .section .isr_vector
72 .section .isr_vector
73 .align 2
73 .align 2
74 .globl __isr_vector
74 .globl __isr_vector
75 __isr_vector:
75 __isr_vector:
76 .long __StackTop /* Top of Stack */
76 .long __StackTop /* Top of Stack */
77 .long Reset_Handler /* Reset Handler */
77 .long Reset_Handler /* Reset Handler */
78 .long NMI_Handler /* NMI Handler */
78 .long NMI_Handler /* NMI Handler */
79 .long HardFault_Handler /* Hard Fault Handler */
79 .long HardFault_Handler /* Hard Fault Handler */
80 .long MemManage_Handler /* MPU Fault Handler */
80 .long MemManage_Handler /* MPU Fault Handler */
81 .long BusFault_Handler /* Bus Fault Handler */
81 .long BusFault_Handler /* Bus Fault Handler */
82 .long UsageFault_Handler /* Usage Fault Handler */
82 .long UsageFault_Handler /* Usage Fault Handler */
83 .long 0 /* Reserved */
83 .long 0 /* Reserved */
84 .long 0 /* Reserved */
84 .long 0 /* Reserved */
85 .long 0 /* Reserved */
85 .long 0 /* Reserved */
86 .long 0 /* Reserved */
86 .long 0 /* Reserved */
87 .long SVC_Handler /* SVCall Handler */
87 .long SVC_Handler /* SVCall Handler */
88 .long DebugMon_Handler /* Debug Monitor Handler */
88 .long DebugMon_Handler /* Debug Monitor Handler */
89 .long 0 /* Reserved */
89 .long 0 /* Reserved */
90 .long PendSV_Handler /* PendSV Handler */
90 .long PendSV_Handler /* PendSV Handler */
91 .long SysTick_Handler /* SysTick Handler */
91 .long SysTick_Handler /* SysTick Handler */
92
92
93 /* External interrupts */
93 /* External interrupts */
94 .word WWDG_IRQHandler /* Window WatchDog */
94 .word WWDG_IRQHandler /* Window WatchDog */
95 .word PVD_IRQHandler /* PVD through EXTI Line detection */
95 .word PVD_IRQHandler /* PVD through EXTI Line detection */
96 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
96 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
97 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
97 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
98 .word FLASH_IRQHandler /* FLASH */
98 .word FLASH_IRQHandler /* FLASH */
99 .word RCC_IRQHandler /* RCC */
99 .word RCC_IRQHandler /* RCC */
100 .word EXTI0_IRQHandler /* EXTI Line0 */
100 .word EXTI0_IRQHandler /* EXTI Line0 */
101 .word EXTI1_IRQHandler /* EXTI Line1 */
101 .word EXTI1_IRQHandler /* EXTI Line1 */
102 .word EXTI2_IRQHandler /* EXTI Line2 */
102 .word EXTI2_IRQHandler /* EXTI Line2 */
103 .word EXTI3_IRQHandler /* EXTI Line3 */
103 .word EXTI3_IRQHandler /* EXTI Line3 */
104 .word EXTI4_IRQHandler /* EXTI Line4 */
104 .word EXTI4_IRQHandler /* EXTI Line4 */
105 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
105 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
106 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
106 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
107 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
107 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
108 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
108 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
109 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
109 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
110 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
110 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
111 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
111 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
112 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
112 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
113 .word CAN1_TX_IRQHandler /* CAN1 TX */
113 .word CAN1_TX_IRQHandler /* CAN1 TX */
114 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
114 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
115 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
115 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
116 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
116 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
117 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
117 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
118 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
118 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
119 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
119 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
120 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
120 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
121 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
121 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
122 .word TIM2_IRQHandler /* TIM2 */
122 .word TIM2_IRQHandler /* TIM2 */
123 .word TIM3_IRQHandler /* TIM3 */
123 .word TIM3_IRQHandler /* TIM3 */
124 .word TIM4_IRQHandler /* TIM4 */
124 .word TIM4_IRQHandler /* TIM4 */
125 .word I2C1_EV_IRQHandler /* I2C1 Event */
125 .word I2C1_EV_IRQHandler /* I2C1 Event */
126 .word I2C1_ER_IRQHandler /* I2C1 Error */
126 .word I2C1_ER_IRQHandler /* I2C1 Error */
127 .word I2C2_EV_IRQHandler /* I2C2 Event */
127 .word I2C2_EV_IRQHandler /* I2C2 Event */
128 .word I2C2_ER_IRQHandler /* I2C2 Error */
128 .word I2C2_ER_IRQHandler /* I2C2 Error */
129 .word SPI1_IRQHandler /* SPI1 */
129 .word SPI1_IRQHandler /* SPI1 */
130 .word SPI2_IRQHandler /* SPI2 */
130 .word SPI2_IRQHandler /* SPI2 */
131 .word USART1_IRQHandler /* USART1 */
131 .word USART1_IRQHandler /* USART1 */
132 .word USART2_IRQHandler /* USART2 */
132 .word USART2_IRQHandler /* USART2 */
133 .word USART3_IRQHandler /* USART3 */
133 .word USART3_IRQHandler /* USART3 */
134 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
134 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
135 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
135 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
136 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
136 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
137 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
137 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
138 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
138 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
139 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
139 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
140 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
140 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
141 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
141 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
142 .word FSMC_IRQHandler /* FSMC */
142 .word FSMC_IRQHandler /* FSMC */
143 .word SDIO_IRQHandler /* SDIO */
143 .word SDIO_IRQHandler /* SDIO */
144 .word TIM5_IRQHandler /* TIM5 */
144 .word TIM5_IRQHandler /* TIM5 */
145 .word SPI3_IRQHandler /* SPI3 */
145 .word SPI3_IRQHandler /* SPI3 */
146 .word UART4_IRQHandler /* UART4 */
146 .word UART4_IRQHandler /* UART4 */
147 .word UART5_IRQHandler /* UART5 */
147 .word UART5_IRQHandler /* UART5 */
148 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
148 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
149 .word TIM7_IRQHandler /* TIM7 */
149 .word TIM7_IRQHandler /* TIM7 */
150 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
150 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
151 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
151 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
152 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
152 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
153 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
153 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
154 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
154 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
155 .word ETH_IRQHandler /* Ethernet */
155 .word ETH_IRQHandler /* Ethernet */
156 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
156 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
157 .word CAN2_TX_IRQHandler /* CAN2 TX */
157 .word CAN2_TX_IRQHandler /* CAN2 TX */
158 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
158 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
159 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
159 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
160 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
160 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
161 .word OTG_FS_IRQHandler /* USB OTG FS */
161 .word OTG_FS_IRQHandler /* USB OTG FS */
162 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
162 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
163 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
163 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
164 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
164 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
165 .word USART6_IRQHandler /* USART6 */
165 .word USART6_IRQHandler /* USART6 */
166 .word I2C3_EV_IRQHandler /* I2C3 event */
166 .word I2C3_EV_IRQHandler /* I2C3 event */
167 .word I2C3_ER_IRQHandler /* I2C3 error */
167 .word I2C3_ER_IRQHandler /* I2C3 error */
168 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
168 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
169 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
169 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
170 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
170 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
171 .word OTG_HS_IRQHandler /* USB OTG HS */
171 .word OTG_HS_IRQHandler /* USB OTG HS */
172 .word DCMI_IRQHandler /* DCMI */
172 .word DCMI_IRQHandler /* DCMI */
173 .word CRYP_IRQHandler /* CRYP crypto */
173 .word CRYP_IRQHandler /* CRYP crypto */
174 .word HASH_RNG_IRQHandler /* Hash and Rng */
174 .word HASH_RNG_IRQHandler /* Hash and Rng */
175 .word FPU_IRQHandler /* FPU */
175 .word FPU_IRQHandler /* FPU */
176
176
177
177
178 .size __isr_vector, . - __isr_vector
178 .size __isr_vector, . - __isr_vector
179
179
180 .text
180 .text
181 .thumb
181 .thumb
182 .thumb_func
182 .thumb_func
183 .align 2
183 .align 2
184 .globl Reset_Handler
184 .globl Reset_Handler
185 .type Reset_Handler, %function
185 .type Reset_Handler, %function
186 Reset_Handler:
186 Reset_Handler:
187 /* Firstly it copies data from read only memory to RAM. There are two schemes
187 /* Firstly it copies data from read only memory to RAM. There are two schemes
188 * to copy. One can copy more than one sections. Another can only copy
188 * to copy. One can copy more than one sections. Another can only copy
189 * one section. The former scheme needs more instructions and read-only
189 * one section. The former scheme needs more instructions and read-only
190 * data to implement than the latter.
190 * data to implement than the latter.
191 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
191 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
192
192
193 /* Single section scheme.
193 /* Single section scheme.
194 *
194 *
195 * The ranges of copy from/to are specified by following symbols
195 * The ranges of copy from/to are specified by following symbols
196 * __etext: LMA of start of the section to copy from. Usually end of text
196 * __etext: LMA of start of the section to copy from. Usually end of text
197 * __data_start__: VMA of start of the section to copy to
197 * __data_start__: VMA of start of the section to copy to
198 * __data_end__: VMA of end of the section to copy to
198 * __data_end__: VMA of end of the section to copy to
199 *
199 *
200 * All addresses must be aligned to 4 bytes boundary.
200 * All addresses must be aligned to 4 bytes boundary.
201 */
201 */
202 ldr r1, =__etext
202 ldr r1, =__etext
203 ldr r2, =__data_start__
203 ldr r2, =__data_start__
204 ldr r3, =__data_end__
204 ldr r3, =__data_end__
205
205
206 .L_loop1:
206 .L_loop1:
207 cmp r2, r3
207 cmp r2, r3
208 ittt lt
208 ittt lt
209 ldrlt r0, [r1], #4
209 ldrlt r0, [r1], #4
210 strlt r0, [r2], #4
210 strlt r0, [r2], #4
211 blt .L_loop1
211 blt .L_loop1
212
212
213 /* This part of work usually is done in C library startup code. Otherwise,
213 /* This part of work usually is done in C library startup code. Otherwise,
214 * define this macro to enable it in this startup.
214 * define this macro to enable it in this startup.
215 *
215 *
216 * There are two schemes too. One can clear multiple BSS sections. Another
216 * There are two schemes too. One can clear multiple BSS sections. Another
217 * can only clear one section. The former is more size expensive than the
217 * can only clear one section. The former is more size expensive than the
218 * latter.
218 * latter.
219 *
219 *
220 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
220 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
221 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
221 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
222 */
222 */
223
223
224 /* Single BSS section scheme.
224 /* Single BSS section scheme.
225 *
225 *
226 * The BSS section is specified by following symbols
226 * The BSS section is specified by following symbols
227 * __bss_start__: start of the BSS section.
227 * __bss_start__: start of the BSS section.
228 * __bss_end__: end of the BSS section.
228 * __bss_end__: end of the BSS section.
229 *
229 *
230 * Both addresses must be aligned to 4 bytes boundary.
230 * Both addresses must be aligned to 4 bytes boundary.
231 */
231 */
232 ldr r1, =__bss_start__
232 ldr r1, =__bss_start__
233 ldr r2, =__bss_end__
233 ldr r2, =__bss_end__
234
234
235 movs r0, 0
235 movs r0, 0
236 .L_loop3:
236 .L_loop3:
237 cmp r1, r2
237 cmp r1, r2
238 itt lt
238 itt lt
239 strlt r0, [r1], #4
239 strlt r0, [r1], #4
240 blt .L_loop3
240 blt .L_loop3
241
241
242 bl main
242 bl main
243
243
244
244
245 .pool
245 .pool
246 .size Reset_Handler, . - Reset_Handler
246 .size Reset_Handler, . - Reset_Handler
247
247
248 .align 1
248 .align 1
249 .thumb_func
249 .thumb_func
250 .weak Default_Handler
250 .weak Default_Handler
251 .type Default_Handler, %function
251 .type Default_Handler, %function
252 Default_Handler:
252 Default_Handler:
253 b .
253 b .
254 .size Default_Handler, . - Default_Handler
254 .size Default_Handler, . - Default_Handler
255
255
256 /* Macro to define default handlers. Default handler
256 /* Macro to define default handlers. Default handler
257 * will be weak symbol and just dead loops. They can be
257 * will be weak symbol and just dead loops. They can be
258 * overwritten by other handlers */
258 * overwritten by other handlers */
259 .macro def_irq_handler handler_name
259 .macro def_irq_handler handler_name
260 .weak \handler_name
260 .weak \handler_name
261 .set \handler_name, Default_Handler
261 .set \handler_name, Default_Handler
262 .endm
262 .endm
263
263
264 def_irq_handler NMI_Handler
264 def_irq_handler NMI_Handler
265 def_irq_handler HardFault_Handler
265 def_irq_handler HardFault_Handler
266 def_irq_handler MemManage_Handler
266 def_irq_handler MemManage_Handler
267 def_irq_handler BusFault_Handler
267 def_irq_handler BusFault_Handler
268 def_irq_handler UsageFault_Handler
268 def_irq_handler UsageFault_Handler
269 def_irq_handler SVC_Handler
269 def_irq_handler SVC_Handler
270 def_irq_handler DebugMon_Handler
270 def_irq_handler DebugMon_Handler
271 def_irq_handler PendSV_Handler
271 def_irq_handler PendSV_Handler
272 def_irq_handler SysTick_Handler
272 def_irq_handler SysTick_Handler
273 def_irq_handler DEF_IRQHandler
273 def_irq_handler DEF_IRQHandler
274
274
275 def_irq_handler WWDG_IRQHandler
275 def_irq_handler WWDG_IRQHandler
276 def_irq_handler PVD_IRQHandler
276 def_irq_handler PVD_IRQHandler
277 def_irq_handler TAMP_STAMP_IRQHandler
277 def_irq_handler TAMP_STAMP_IRQHandler
278 def_irq_handler RTC_WKUP_IRQHandler
278 def_irq_handler RTC_WKUP_IRQHandler
279 def_irq_handler FLASH_IRQHandler
279 def_irq_handler FLASH_IRQHandler
280 def_irq_handler RCC_IRQHandler
280 def_irq_handler RCC_IRQHandler
281 def_irq_handler EXTI0_IRQHandler
281 def_irq_handler EXTI0_IRQHandler
282 def_irq_handler EXTI1_IRQHandler
282 def_irq_handler EXTI1_IRQHandler
283 def_irq_handler EXTI2_IRQHandler
283 def_irq_handler EXTI2_IRQHandler
284 def_irq_handler EXTI3_IRQHandler
284 def_irq_handler EXTI3_IRQHandler
285 def_irq_handler EXTI4_IRQHandler
285 def_irq_handler EXTI4_IRQHandler
286 def_irq_handler DMA1_Stream0_IRQHandler
286 def_irq_handler DMA1_Stream0_IRQHandler
287 def_irq_handler DMA1_Stream1_IRQHandler
287 def_irq_handler DMA1_Stream1_IRQHandler
288 def_irq_handler DMA1_Stream2_IRQHandler
288 def_irq_handler DMA1_Stream2_IRQHandler
289 def_irq_handler DMA1_Stream3_IRQHandler
289 def_irq_handler DMA1_Stream3_IRQHandler
290 def_irq_handler DMA1_Stream4_IRQHandler
290 def_irq_handler DMA1_Stream4_IRQHandler
291 def_irq_handler DMA1_Stream5_IRQHandler
291 def_irq_handler DMA1_Stream5_IRQHandler
292 def_irq_handler DMA1_Stream6_IRQHandler
292 def_irq_handler DMA1_Stream6_IRQHandler
293 def_irq_handler ADC_IRQHandler
293 def_irq_handler ADC_IRQHandler
294 def_irq_handler CAN1_TX_IRQHandler
294 def_irq_handler CAN1_TX_IRQHandler
295 def_irq_handler CAN1_RX0_IRQHandler
295 def_irq_handler CAN1_RX0_IRQHandler
296 def_irq_handler CAN1_RX1_IRQHandler
296 def_irq_handler CAN1_RX1_IRQHandler
297 def_irq_handler CAN1_SCE_IRQHandler
297 def_irq_handler CAN1_SCE_IRQHandler
298 def_irq_handler EXTI9_5_IRQHandler
298 def_irq_handler EXTI9_5_IRQHandler
299 def_irq_handler TIM1_BRK_TIM9_IRQHandler
299 def_irq_handler TIM1_BRK_TIM9_IRQHandler
300 def_irq_handler TIM1_UP_TIM10_IRQHandler
300 def_irq_handler TIM1_UP_TIM10_IRQHandler
301 def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler
301 def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler
302 def_irq_handler TIM1_CC_IRQHandler
302 def_irq_handler TIM1_CC_IRQHandler
303 def_irq_handler TIM2_IRQHandler
303 def_irq_handler TIM2_IRQHandler
304 def_irq_handler TIM3_IRQHandler
304 def_irq_handler TIM3_IRQHandler
305 def_irq_handler TIM4_IRQHandler
305 def_irq_handler TIM4_IRQHandler
306 def_irq_handler I2C1_EV_IRQHandler
306 def_irq_handler I2C1_EV_IRQHandler
307 def_irq_handler I2C1_ER_IRQHandler
307 def_irq_handler I2C1_ER_IRQHandler
308 def_irq_handler I2C2_EV_IRQHandler
308 def_irq_handler I2C2_EV_IRQHandler
309 def_irq_handler I2C2_ER_IRQHandler
309 def_irq_handler I2C2_ER_IRQHandler
310 def_irq_handler SPI1_IRQHandler
310 def_irq_handler SPI1_IRQHandler
311 def_irq_handler SPI2_IRQHandler
311 def_irq_handler SPI2_IRQHandler
312 def_irq_handler USART1_IRQHandler
312 def_irq_handler USART1_IRQHandler
313 def_irq_handler USART2_IRQHandler
313 def_irq_handler USART2_IRQHandler
314 def_irq_handler USART3_IRQHandler
314 def_irq_handler USART3_IRQHandler
315 def_irq_handler EXTI15_10_IRQHandler
315 def_irq_handler EXTI15_10_IRQHandler
316 def_irq_handler RTC_Alarm_IRQHandler
316 def_irq_handler RTC_Alarm_IRQHandler
317 def_irq_handler OTG_FS_WKUP_IRQHandler
317 def_irq_handler OTG_FS_WKUP_IRQHandler
318 def_irq_handler TIM8_BRK_TIM12_IRQHandler
318 def_irq_handler TIM8_BRK_TIM12_IRQHandler
319 def_irq_handler TIM8_UP_TIM13_IRQHandler
319 def_irq_handler TIM8_UP_TIM13_IRQHandler
320 def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler
320 def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler
321 def_irq_handler TIM8_CC_IRQHandler
321 def_irq_handler TIM8_CC_IRQHandler
322 def_irq_handler DMA1_Stream7_IRQHandler
322 def_irq_handler DMA1_Stream7_IRQHandler
323 def_irq_handler FSMC_IRQHandler
323 def_irq_handler FSMC_IRQHandler
324 def_irq_handler SDIO_IRQHandler
324 def_irq_handler SDIO_IRQHandler
325 def_irq_handler TIM5_IRQHandler
325 def_irq_handler TIM5_IRQHandler
326 def_irq_handler SPI3_IRQHandler
326 def_irq_handler SPI3_IRQHandler
327 def_irq_handler UART4_IRQHandler
327 def_irq_handler UART4_IRQHandler
328 def_irq_handler UART5_IRQHandler
328 def_irq_handler UART5_IRQHandler
329 def_irq_handler TIM6_DAC_IRQHandler
329 def_irq_handler TIM6_DAC_IRQHandler
330 def_irq_handler TIM7_IRQHandler
330 def_irq_handler TIM7_IRQHandler
331 def_irq_handler DMA2_Stream0_IRQHandler
331 def_irq_handler DMA2_Stream0_IRQHandler
332 def_irq_handler DMA2_Stream1_IRQHandler
332 def_irq_handler DMA2_Stream1_IRQHandler
333 def_irq_handler DMA2_Stream2_IRQHandler
333 def_irq_handler DMA2_Stream2_IRQHandler
334 def_irq_handler DMA2_Stream3_IRQHandler
334 def_irq_handler DMA2_Stream3_IRQHandler
335 def_irq_handler DMA2_Stream4_IRQHandler
335 def_irq_handler DMA2_Stream4_IRQHandler
336 def_irq_handler ETH_IRQHandler
336 def_irq_handler ETH_IRQHandler
337 def_irq_handler ETH_WKUP_IRQHandler
337 def_irq_handler ETH_WKUP_IRQHandler
338 def_irq_handler CAN2_TX_IRQHandler
338 def_irq_handler CAN2_TX_IRQHandler
339 def_irq_handler CAN2_RX0_IRQHandler
339 def_irq_handler CAN2_RX0_IRQHandler
340 def_irq_handler CAN2_RX1_IRQHandler
340 def_irq_handler CAN2_RX1_IRQHandler
341 def_irq_handler CAN2_SCE_IRQHandler
341 def_irq_handler CAN2_SCE_IRQHandler
342 def_irq_handler OTG_FS_IRQHandler
342 def_irq_handler OTG_FS_IRQHandler
343 def_irq_handler DMA2_Stream5_IRQHandler
343 def_irq_handler DMA2_Stream5_IRQHandler
344 def_irq_handler DMA2_Stream6_IRQHandler
344 def_irq_handler DMA2_Stream6_IRQHandler
345 def_irq_handler DMA2_Stream7_IRQHandler
345 def_irq_handler DMA2_Stream7_IRQHandler
346 def_irq_handler USART6_IRQHandler
346 def_irq_handler USART6_IRQHandler
347 def_irq_handler I2C3_EV_IRQHandler
347 def_irq_handler I2C3_EV_IRQHandler
348 def_irq_handler I2C3_ER_IRQHandler
348 def_irq_handler I2C3_ER_IRQHandler
349 def_irq_handler OTG_HS_EP1_OUT_IRQHandler
349 def_irq_handler OTG_HS_EP1_OUT_IRQHandler
350 def_irq_handler OTG_HS_EP1_IN_IRQHandler
350 def_irq_handler OTG_HS_EP1_IN_IRQHandler
351 def_irq_handler OTG_HS_WKUP_IRQHandler
351 def_irq_handler OTG_HS_WKUP_IRQHandler
352 def_irq_handler OTG_HS_IRQHandler
352 def_irq_handler OTG_HS_IRQHandler
353 def_irq_handler DCMI_IRQHandler
353 def_irq_handler DCMI_IRQHandler
354 def_irq_handler CRYP_IRQHandler
354 def_irq_handler CRYP_IRQHandler
355 def_irq_handler HASH_RNG_IRQHandler
355 def_irq_handler HASH_RNG_IRQHandler
356 def_irq_handler FPU_IRQHandler
356 def_irq_handler FPU_IRQHandler
357
357
358 .end
358 .end
Show file before | Show file after | Hide comments
@@ -1,118 +1,140
1 #include <stdio.h>
1 #include <stdio.h>
2 #include <timer.h>
2 #include <timer.h>
3 #include <stm32f4xx_rcc.h>
3 #include <stm32f4xx_rcc.h>
4 #include <stm32f4xx_tim.h>
4 #include <stm32f4xx_tim.h>
5 #include <stm32f4xx_dac.h>
5 #include <stm32f4xx_dac.h>
6 #include <stm32f4xx_gpio.h>
6 #include <stm32f4xx_gpio.h>
7 #include <stm32f4xx_dma.h>
7 #include <stm32f4xx_dma.h>
8 #include <stm32f4xx.h>
8 #include <stm32f4xx.h>
9 #include <gpio.h>
9 #include <gpio.h>
10 #include <stm32f4xx.h>
10 #include <stm32f4xx.h>
11 #include <dac.h>
11 #include <dac.h>
12
12
13
13
14 #define DAC_DHR12R2_ADDRESS 0x40007414
15 #define DAC_DHR8R1_ADDRESS 0x40007410
16
17
14
18 const TIM_TypeDef* _timer_dev_table[14]={TIM1,TIM2,TIM3,TIM4,TIM5,TIM6,TIM7,
15 const TIM_TypeDef* _timer_dev_table[14]={TIM1,TIM2,TIM3,TIM4,TIM5,TIM6,TIM7,
19 TIM8,TIM9,TIM10,TIM11,TIM12,TIM13,TIM14};
16 TIM8,TIM9,TIM10,TIM11,TIM12,TIM13,TIM14};
20
17
21
18
22
19
23 int dacopen(uint32_t pin)
20 int dacopen(uint32_t pin)
24 {
21 {
25 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
22 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
26 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
23 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
27 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 , ENABLE);
24 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 , ENABLE);
28 RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
25 RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
29 gpio_t DACOUT;
26 gpio_t DACOUT;
30 DACOUT = gpioopen(pin);
27 DACOUT = gpioopen(pin);
31 DACOUT |= gpioan | gpionopulltype;
28 DACOUT |= gpioan | gpionopulltype;
32 gpiosetconfig(&DACOUT);
29 gpiosetconfig(&DACOUT);
33 return 0;
30 return 0;
34 }
31 }
35
32
36 int dacsetconfig(int timer, int buffer_size, int dac, uint32_t dac_type, uint32_t samplingFreq, void *data)
33 int dacsetconfig(int timer, int buffer_size, int dac, uint32_t dac_type, uint32_t samplingFreq, void *data)
37 {
34 {
38 #include <core.h>
35 //#include <core.h>
39 DAC_InitTypeDef DAC_InitStructure;
36 DAC_InitTypeDef DAC_InitStructure;
40 TIM_TypeDef* tim = (TIM_TypeDef*)_timer_dev_table[timer];
37 // TIM_TypeDef* tim = (TIM_TypeDef*)_timer_dev_table[timer];
38 TIM_TypeDef* tim = TIM6;
41 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
39 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
42 DMA_InitTypeDef DMA_InitStructure;
40 DMA_InitTypeDef DMA_InitStructure;
43 if(timer>=timer2 && timer <= timer7)RCC_APB1PeriphClockCmd((1<<(timer-1)), ENABLE);
41 if(timer>=timer2 && timer <= timer7)RCC_APB1PeriphClockCmd((1<<(timer-1)), ENABLE);
44 if(timer==timer8)RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
42 if(timer==timer8)RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
45 uint32_t timfreq = getCpuFreq()/2;
43 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
46 uint32_t period = timfreq/samplingFreq - 1;
44 unsigned int __inputFreq__ = 80000000;//getCpuFreq()/2;
47 uint16_t PrescalerValue=0;
45 unsigned int period = __inputFreq__/samplingFreq - 1;
48 while (period>=0x0FFFF)
46 unsigned int PrescalerValue=0;
49 {
47 // while (period>=0x0FFFF)
50 PrescalerValue++;
48 // {
51 timfreq = getCpuFreq()/(2*(PrescalerValue+1));
49 // PrescalerValue++;
52 period = (timfreq/samplingFreq) - 1;
50 // __inputFreq__ = getCpuFreq()/(2*(PrescalerValue+1));
53 }
51 // period = (__inputFreq__/samplingFreq) - 1;
54 printf("period = %d \n\r prescaler = %d \n\r",period,PrescalerValue);
52 // }
53
54 printf("period = %d \n\r prescaler = 0x%x 0x%x\n\r",period,data,__get_MSP());
55 TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
55 TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
56 TIM_TimeBaseStructure.TIM_Period = 10;
56 TIM_TimeBaseStructure.TIM_Period = 0xff;
57 TIM_TimeBaseStructure.TIM_Prescaler = 0;
57 TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)0;
58 TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
58 TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
59 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
59 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
60 TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
60 TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure);
61 TIM_SelectOutputTrigger(tim, TIM_TRGOSource_Update);
61 TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);
62 TIM_ARRPreloadConfig(tim, ENABLE);
62 // TIM_ARRPreloadConfig(tim, ENABLE);
63 TIM_Cmd(tim, ENABLE);
63 TIM_Cmd(TIM6, ENABLE);
64
64
65 if (timer == timer2)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
65 // if (timer == timer2)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
66 if (timer == timer4)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T4_TRGO;
66 // if (timer == timer4)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T4_TRGO;
67 if (timer == timer5)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T5_TRGO;
67 // if (timer == timer5)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T5_TRGO;
68 if (timer == timer6)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
68 // if (timer == timer6)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
69 if (timer == timer7)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T7_TRGO;
69 // if (timer == timer7)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T7_TRGO;
70 if (timer == timer8)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T8_TRGO;
70 // if (timer == timer8)DAC_InitStructure.DAC_Trigger = DAC_Trigger_T8_TRGO;
71 DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
72
71 DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
73 DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
72 DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
74 DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
73 if (dac == DAC1){
75 if (dac == DAC1){
76 printf("DAC1 Init ");
74 DAC_Init(DAC_Channel_1, &DAC_InitStructure);
77 DAC_Init(DAC_Channel_1, &DAC_InitStructure);
75 DMA_DeInit(DMA1_Stream5);
78 DMA_DeInit(DMA1_Stream5);
76 }
79 }
77
80
78 if (dac == DAC2){
81 if (dac == DAC2){
82 printf("DAC2 Init ");
79 DAC_Init(DAC_Channel_2, &DAC_InitStructure);
83 DAC_Init(DAC_Channel_2, &DAC_InitStructure);
80 DMA_DeInit(DMA1_Stream6);
84 DMA_DeInit(DMA1_Stream6);
81 }
85 }
82
86 if (dac == DAC1){
87 DMA_DeInit(DMA1_Stream5);
88 DMA_Cmd(DMA1_Stream5, DISABLE);
89 }
90 if (dac == DAC2){
91 DMA_DeInit(DMA1_Stream6);
92 DMA_Cmd(DMA1_Stream6, DISABLE);
93 }
83 DMA_InitStructure.DMA_Channel = DMA_Channel_7;
94 DMA_InitStructure.DMA_Channel = DMA_Channel_7;
84 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)dac_type;
95 // DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)dac_type;
96 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC1_12bit_right_align;
85 DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)data;
97 DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)data;
86 DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
98 DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
87 DMA_InitStructure.DMA_BufferSize = buffer_size;
99 DMA_InitStructure.DMA_BufferSize = buffer_size;
88 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
100 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
89 DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
90 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
101 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
91 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
102 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
92 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
103 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
93 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
104 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
94 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
105 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
95 DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
106 DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
96 DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
107 DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
97 DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
108 DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
98 DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
109 DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
110 DMA_Init(DMA1_Stream5, &DMA_InitStructure);
111 /* Enable DMA1_Stream6 */
112 DMA_Cmd(DMA1_Stream5, ENABLE);
99
113
100 if (dac == DAC1){
114 /* Enable DAC Channel2 */
101 DMA_Init(DMA1_Stream5, &DMA_InitStructure);
115 DAC_Cmd(DAC_Channel_1, ENABLE);
102 DMA_Cmd(DMA1_Stream5, ENABLE);
116
103 DAC_DMACmd(DAC_Channel_1, ENABLE);
117 /* Enable DMA for DAC Channel2 */
104 DAC_Cmd(DAC_Channel_1, ENABLE);
118 DAC_DMACmd(DAC_Channel_1, ENABLE);
105
119
106 }
120 // if (dac == DAC1){
107 if (dac == DAC2){
121 // printf("DAC1 DMA Init");
108 DMA_Init(DMA1_Stream6, &DMA_InitStructure);
122 // DMA_Init(DMA1_Stream5, &DMA_InitStructure);
109 DMA_Cmd(DMA1_Stream6, ENABLE);
123 // DMA_Cmd(DMA1_Stream5, ENABLE);
110 DAC_DMACmd(DAC_Channel_2, ENABLE);
124 // DAC_Cmd(DAC_Channel_1, ENABLE);
111 DAC_Cmd(DAC_Channel_2, ENABLE);
125 // DAC_DMACmd(DAC_Channel_1, ENABLE);
112
126
113 }
127 // }
128 // if (dac == DAC2){
129 // printf("DAC2 DMA Init");
130 // DMA_Init(DMA1_Stream6, &DMA_InitStructure);
131 // DMA_Cmd(DMA1_Stream6, ENABLE);
132 // DAC_Cmd(DAC_Channel_2, ENABLE);
133 // DAC_DMACmd(DAC_Channel_2, ENABLE);
134
135 // }
114 return 0;
136 return 0;
115
137
116 }
138 }
117
139
118
140
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