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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL;
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
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USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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ENTITY LFR_em IS
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PORT (
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clk100MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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-- TAG --------------------------------------------------------------------
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TAG1 : IN STD_ULOGIC; -- DSU rx data
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TAG3 : OUT STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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TAG2 : IN STD_ULOGIC; -- UART1 rx data
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TAG4 : OUT STD_ULOGIC; -- UART1 tx data
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-- RAM --------------------------------------------------------------------
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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-- SPW --------------------------------------------------------------------
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spw1_din : IN STD_LOGIC;
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spw1_sin : IN STD_LOGIC;
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spw1_dout : OUT STD_LOGIC;
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spw1_sout : OUT STD_LOGIC;
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spw2_din : IN STD_LOGIC;
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spw2_sin : IN STD_LOGIC;
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spw2_dout : OUT STD_LOGIC;
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spw2_sout : OUT STD_LOGIC;
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-- ADC --------------------------------------------------------------------
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bias_fail_sw : OUT STD_LOGIC;
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ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ADC_smpclk : OUT STD_LOGIC;
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ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
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---------------------------------------------------------------------------
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TAG8 : OUT STD_LOGIC;
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led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
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);
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END LFR_em;
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ARCHITECTURE beh OF LFR_em IS
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SIGNAL clk_50_s : STD_LOGIC := '0';
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SIGNAL clk_25 : STD_LOGIC := '0';
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SIGNAL clk_24 : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-- CONSTANTS
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CONSTANT CFG_PADTECH : INTEGER := inferred;
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CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
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CONSTANT NB_AHB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
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SIGNAL apbi_ext : apb_slv_in_type;
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SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
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SIGNAL ahbi_s_ext : ahb_slv_in_type;
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SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
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SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
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SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
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-- Spacewire signals
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SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL spw_rxtxclk : STD_ULOGIC;
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SIGNAL spw_rxclkn : STD_ULOGIC;
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SIGNAL spw_clk : STD_LOGIC;
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SIGNAL swni : grspw_in_type;
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SIGNAL swno : grspw_out_type;
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--GPIO
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SIGNAL gpioi : gpio_in_type;
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SIGNAL gpioo : gpio_out_type;
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-- AD Converter ADS7886
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SIGNAL sample : Samples14v(7 DOWNTO 0);
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SIGNAL sample_s : Samples(7 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL ADC_nCS_sig : STD_LOGIC;
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SIGNAL ADC_CLK_sig : STD_LOGIC;
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SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL rstn : STD_LOGIC;
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SIGNAL ADC_smpclk_s : STD_LOGIC;
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BEGIN -- beh
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-----------------------------------------------------------------------------
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-- CLK
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-----------------------------------------------------------------------------
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rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
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PROCESS(clk100MHz)
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BEGIN
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IF clk100MHz'EVENT AND clk100MHz = '1' THEN
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clk_50_s <= NOT clk_50_s;
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END IF;
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END PROCESS;
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PROCESS(clk_50_s)
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BEGIN
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IF clk_50_s'EVENT AND clk_50_s = '1' THEN
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clk_25 <= NOT clk_25;
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END IF;
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END PROCESS;
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PROCESS(clk49_152MHz)
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BEGIN
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IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
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clk_24 <= NOT clk_24;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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PROCESS (clk_25, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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led(0) <= '0';
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led(1) <= '0';
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led(2) <= '0';
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ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
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led(0) <= '0';
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led(1) <= '1';
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led(2) <= '1';
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END IF;
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END PROCESS;
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--
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leon3_soc_1 : leon3_soc
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GENERIC MAP (
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fabtech => apa3e,
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memtech => apa3e,
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padtech => inferred,
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clktech => inferred,
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disas => 0,
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dbguart => 0,
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pclow => 2,
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clk_freq => 25000,
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NB_CPU => 1,
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ENABLE_FPU => 1,
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FPU_NETLIST => 0,
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ENABLE_DSU => 1,
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ENABLE_AHB_UART => 1,
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ENABLE_APB_UART => 1,
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ENABLE_IRQMP => 1,
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ENABLE_GPT => 1,
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NB_AHB_MASTER => NB_AHB_MASTER,
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NB_AHB_SLAVE => NB_AHB_SLAVE,
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NB_APB_SLAVE => NB_APB_SLAVE)
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PORT MAP (
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clk => clk_25,
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reset => rstn,
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errorn => OPEN,
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ahbrxd => TAG1,
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ahbtxd => TAG3,
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urxd1 => TAG2,
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utxd1 => TAG4,
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address => address,
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data => data,
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nSRAM_BE0 => nSRAM_BE0,
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nSRAM_BE1 => nSRAM_BE1,
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nSRAM_BE2 => nSRAM_BE2,
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nSRAM_BE3 => nSRAM_BE3,
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nSRAM_WE => nSRAM_WE,
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nSRAM_CE => nSRAM_CE,
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nSRAM_OE => nSRAM_OE,
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apbi_ext => apbi_ext,
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apbo_ext => apbo_ext,
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ahbi_s_ext => ahbi_s_ext,
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ahbo_s_ext => ahbo_s_ext,
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ahbi_m_ext => ahbi_m_ext,
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ahbo_m_ext => ahbo_m_ext);
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-------------------------------------------------------------------------------
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-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
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-------------------------------------------------------------------------------
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apb_lfr_time_management_1 : apb_lfr_time_management
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GENERIC MAP (
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pindex => 6,
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paddr => 6,
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pmask => 16#fff#,
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FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
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NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
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PORT MAP (
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clk25MHz => clk_25,
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clk24_576MHz => clk_24, -- 49.152MHz/2
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resetn => rstn,
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grspw_tick => swno.tickout,
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apbi => apbi_ext,
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apbo => apbo_ext(6),
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coarse_time => coarse_time,
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fine_time => fine_time);
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-----------------------------------------------------------------------
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--- SpaceWire --------------------------------------------------------
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-----------------------------------------------------------------------
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-- SPW_EN <= '1';
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spw_clk <= clk_50_s;
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spw_rxtxclk <= spw_clk;
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spw_rxclkn <= NOT spw_rxtxclk;
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-- PADS for SPW1
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spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
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PORT MAP (spw1_din, dtmp(0));
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spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
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PORT MAP (spw1_sin, stmp(0));
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spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (spw1_dout, swno.d(0));
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spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (spw1_sout, swno.s(0));
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-- PADS FOR SPW2
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spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
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PORT MAP (spw2_sin, dtmp(1));
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spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
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PORT MAP (spw2_din, stmp(1));
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spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (spw2_dout, swno.d(1));
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spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (spw2_sout, swno.s(1));
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-- GRSPW PHY
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--spw1_input: if CFG_SPW_GRSPW = 1 generate
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spw_inputloop : FOR j IN 0 TO 1 GENERATE
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spw_phy0 : grspw_phy
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GENERIC MAP(
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tech => apa3e,
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rxclkbuftype => 1,
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scantest => 0)
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PORT MAP(
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rxrst => swno.rxrst,
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di => dtmp(j),
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si => stmp(j),
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rxclko => spw_rxclk(j),
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do => swni.d(j),
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ndo => swni.nd(j*5+4 DOWNTO j*5),
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dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
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END GENERATE spw_inputloop;
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-- SPW core
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sw0 : grspwm GENERIC MAP(
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tech => apa3e,
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hindex => 1,
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pindex => 5,
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paddr => 5,
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pirq => 11,
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sysfreq => 25000, -- CPU_FREQ
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rmap => 1,
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rmapcrc => 1,
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fifosize1 => 16,
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fifosize2 => 16,
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rxclkbuftype => 1,
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rxunaligned => 0,
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rmapbufs => 4,
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ft => 0,
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netlist => 0,
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ports => 2,
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--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
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memtech => apa3e,
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destkey => 2,
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spwcore => 1
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--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
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--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
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--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
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)
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PORT MAP(rstn, clk_25, spw_rxclk(0),
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spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
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ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
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swni, swno);
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swni.tickin <= '0';
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swni.rmapen <= '1';
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swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
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swni.tickinraw <= '0';
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swni.timein <= (OTHERS => '0');
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swni.dcrstval <= (OTHERS => '0');
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swni.timerrstval <= (OTHERS => '0');
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-------------------------------------------------------------------------------
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-- LFR ------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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lpp_lfr_1 : lpp_lfr
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GENERIC MAP (
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Mem_use => use_RAM,
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nb_data_by_buffer_size => 32,
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nb_word_by_buffer_size => 30,
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nb_snapshot_param_size => 32,
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delta_vector_size => 32,
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delta_vector_size_f0_2 => 7, -- log2(96)
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pindex => 15,
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paddr => 15,
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pmask => 16#fff#,
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pirq_ms => 6,
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pirq_wfp => 14,
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hindex => 2,
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top_lfr_version => X"010118") -- aa.bb.cc version
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-- AA : BOARD NUMBER
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-- 0 => MINI_LFR
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-- 1 => EM
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PORT MAP (
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clk => clk_25,
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rstn => rstn,
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sample_B => sample_s(2 DOWNTO 0),
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sample_E => sample_s(7 DOWNTO 3),
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sample_val => sample_val,
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apbi => apbi_ext,
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apbo => apbo_ext(15),
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ahbi => ahbi_m_ext,
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ahbo => ahbo_m_ext(2),
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coarse_time => coarse_time,
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fine_time => fine_time,
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data_shaping_BW => bias_fail_sw,
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observation_vector_0 => OPEN,
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observation_vector_1 => OPEN,
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observation_reg => observation_reg);
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all_sample: FOR I IN 7 DOWNTO 0 GENERATE
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sample_s(I) <= sample(I) & '0' & '0';
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END GENERATE all_sample;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
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GENERIC MAP (
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ChanelCount => 8,
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ncycle_cnv_high => 13,
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ncycle_cnv => 25)
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PORT MAP (
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cnv_clk => clk_24,
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cnv_rstn => rstn,
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cnv => ADC_smpclk_s,
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clk => clk_25,
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rstn => rstn,
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ADC_data => ADC_data,
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ADC_nOE => ADC_OEB_bar_CH,
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|
sample => sample,
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sample_val => sample_val);
|
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|
|
|
|
|
|
|
|
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|
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|
--top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
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-- GENERIC MAP (
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-- ChanelCount => 8,
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-- ncycle_cnv_high => 40, -- TODO : 79
|
|
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-- ncycle_cnv => 250) -- TODO : 500
|
|
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-- PORT MAP (
|
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-- cnv_clk => clk_24, -- TODO : 49.152
|
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-- cnv_rstn => rstn, -- ok
|
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-- cnv => ADC_smpclk_s, -- ok
|
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|
-- clk => clk_25, -- ok
|
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-- rstn => rstn, -- ok
|
|
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-- ADC_data => ADC_data, -- ok
|
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|
-- ADC_nOE => ADC_OEB_bar_CH, -- ok
|
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|
-- sample => sample, -- ok
|
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-- sample_val => sample_val); -- ok
|
|
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|
ADC_smpclk <= ADC_smpclk_s;
|
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|
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|
TAG8 <= ADC_smpclk_s;
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END beh;
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|
