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HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Update AD CONV for RHF1401 (LFR-EM) with filter
pellion -
r420:51a6c45e7a0e JC
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@@ -53,6 +53,8 PACKAGE lpp_ad_conv IS
53
53
54 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
54 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
55
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56 SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
57
56 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
58 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
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58 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
60 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
@@ -64,6 +66,8 PACKAGE lpp_ad_conv IS
64 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
66 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
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66 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
68 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
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70 TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
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68 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
72 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
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@@ -43,7 +43,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
43 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
43 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
44
44
45 SIGNAL ADC_data_selected : Samples14;
45 SIGNAL ADC_data_selected : Samples14;
46 SIGNAL ADC_data_result : Samples14;
46 SIGNAL ADC_data_result : Samples15;
47
47
48 SIGNAL sample_counter : INTEGER;
48 SIGNAL sample_counter : INTEGER;
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@@ -146,14 +146,14 BEGIN
146 sample_val <= '0';
146 sample_val <= '0';
147
147
148 CASE channel_counter IS
148 CASE channel_counter IS
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result;
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1);
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result;
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1);
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result;
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1);
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result;
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1);
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result;
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1);
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result;
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1);
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result;
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1);
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result;
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1);
157 IF sample_counter = 9 THEN
157 IF sample_counter = 9 THEN
158 sample_counter <= 0 ;
158 sample_counter <= 0 ;
159 sample_val <= '1';
159 sample_val <= '1';
@@ -179,7 +179,7 BEGIN
179 sample_reg(7) WHEN OTHERS ;
179 sample_reg(7) WHEN OTHERS ;
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182 ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) / 2);
182 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
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183
184 sample <= sample_reg;
184 sample <= sample_reg;
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