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New lfr_time_management (lib/lpp/lfr_time_management)...
pellion -
r329:f3e0ce954a57 JC
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
6
7 ##VHDLSYNFILES= TB.vhd
8
9 ##LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
10 ## tmtc openchip hynix ihp gleichmann micron usbhc
11
12 ##DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
13 ## pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
14 ## ./amba_lcd_16x2_ctrlr \
15 ## ./general_purpose/lpp_AMR \
16 ## ./general_purpose/lpp_balise \
17 ## ./general_purpose/lpp_delay \
18 ## ./dsp/lpp_fft \
19 ## ./lpp_bootloader \
20 ## ./lpp_cna \
21 ## ./lpp_demux \
22 ## ./lpp_matrix \
23 ## ./lpp_uart \
24 ## ./lpp_usb \
25 ## ./lpp_Header \
26
27 ##FILESKIP =lpp_lfr_ms.vhd \x
28 ## i2cmst.vhd \
29 ## APB_MULTI_DIODE.vhd \
30 ## APB_SIMPLE_DIODE.vhd \
31 ## Top_MatrixSpec.vhd \
32 ## APB_FFT.vhd
33
34 ##include $(GRLIB)/bin/Makefile
35 ##include $(GRLIB)/software/leon3/Makefile
36
37 CMD_VLIB=vlib
38 CMD_VMAP=vmap
39 CMD_VCOM=@vcom -quiet -93 -work
40
41 ################## project specific targets ##########################
42
43 all:
44 @echo "make vsim"
45 @echo "make libs"
46 @echo "make clean"
47 @echo "make vcom_grlib vcom_lpp vcom_tb"
48
49 run:
50 @vsim work.TB -do run.do
51
52 vsim: libs vcom run
53
54 libs:
55 @$(CMD_VLIB) modelsim
56 @$(CMD_VMAP) modelsim modelsim
57 @$(CMD_VLIB) modelsim/grlib
58 @$(CMD_VMAP) grlib modelsim/grlib
59 @$(CMD_VLIB) modelsim/work
60 @$(CMD_VMAP) work modelsim/work
61 @$(CMD_VLIB) modelsim/lpp
62 @$(CMD_VMAP) lpp modelsim/lpp
63 @echo "libs done"
64
65
66 clean:
67 @rm -Rf modelsim
68 @rm -Rf modelsim.ini
69 @rm -Rf *~
70 @rm -Rf transcript
71 @rm -Rf wlft*
72 @rm -Rf *.wlf
73 @rm -Rf vish_stacktrace.vstf
74 @rm -Rf libs.do
75
76 vcom: vcom_grlib vcom_lpp vcom_tb
77
78 vcom_tb:
79 $(CMD_VCOM) work TB.vhd
80 @echo "vcom work done"
81
82 vcom_grlib:
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
101 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
102 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
103 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
104 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
105 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
106 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
107 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
108 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
109 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
110 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
111 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
112 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
113 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
114 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
115 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
116 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
117 @echo "vcom grlib done"
118
119 vcom_lpp:
120 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
121 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
122 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
123 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
124 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
125 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
126 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
127 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
128 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
129 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
130 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
131 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
132 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
133 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
134 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
135 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
136 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
137 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
138 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
139 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
140 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
141 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
142 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
143 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
144 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
145 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd
146 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
147 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
148 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
149 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
150 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
151 @echo "vcom lpp done"
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_time_management.ALL;
34
35 ENTITY TB IS
36
37 PORT (
38 SIM_OK : OUT STD_LOGIC
39 );
40
41 END TB;
42
43
44 ARCHITECTURE beh OF TB IS
45
46 SIGNAL clk25MHz : STD_LOGIC := '0';
47 SIGNAL clk24_576MHz : STD_LOGIC := '0';
48 SIGNAL resetn : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
50 SIGNAL apbi : apb_slv_in_type;
51 SIGNAL apbo : apb_slv_out_type;
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 SIGNAL tick_ongoing : STD_LOGIC;
62
63 SIGNAL ASSERTION_1 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
66
67 BEGIN -- beh
68
69 apb_lfr_time_management_1: apb_lfr_time_management
70 GENERIC MAP (
71 pindex => 0,
72 paddr => 0,
73 pmask => 16#fff#,
74 FIRST_DIVISION => 20,
75 NB_SECOND_DESYNC => 4)
76 PORT MAP (
77 clk25MHz => clk25MHz,
78 clk24_576MHz => clk24_576MHz,
79 resetn => resetn,
80 grspw_tick => grspw_tick,
81 apbi => apbi,
82 apbo => apbo,
83 coarse_time => coarse_time,
84 fine_time => fine_time);
85
86 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
87 clk24_576MHz <= NOT clk24_576MHz AFTER 20345 ps;
88
89
90
91
92 PROCESS
93 BEGIN -- PROCESS
94 WAIT UNTIL clk25MHz = '1';
95 TB_string <= "RESET ";
96
97 resetn <= '0';
98
99 apbi.psel(0) <= '0';
100 apbi.pwrite <= '0';
101 apbi.penable <= '0';
102 apbi.paddr <= (OTHERS => '0');
103 apbi.pwdata <= (OTHERS => '0');
104 grspw_tick <= '0';
105 WAIT UNTIL clk25MHz = '1';
106 WAIT UNTIL clk25MHz = '1';
107 resetn <= '1';
108 WAIT FOR 60 ms;
109 ---------------------------------------------------------------------------
110 -- DESYNC TO SYNC
111 ---------------------------------------------------------------------------
112 WAIT UNTIL clk25MHz = '1';
113 TB_string <= "TICK 1 ";
114 grspw_tick <= '1';------------------------------------------------------1
115 WAIT UNTIL clk25MHz = '1';
116 grspw_tick <= '0';
117 WAIT FOR 53333 us;
118 WAIT UNTIL clk25MHz = '1';
119 TB_string <= "TICK 2 ";
120 grspw_tick <= '1';------------------------------------------------------2
121 WAIT UNTIL clk25MHz = '1';
122 grspw_tick <= '0';
123 WAIT FOR 56000 us;
124 WAIT UNTIL clk25MHz = '1';
125 TB_string <= "TICK 3 ";
126 grspw_tick <= '1';------------------------------------------------------3
127 WAIT UNTIL clk25MHz = '1';
128 grspw_tick <= '0';
129 WAIT FOR 200 ms;
130 WAIT UNTIL clk25MHz = '1';
131 TB_string <= "CT new ";
132 -- WRITE NEW COARSE_TIME
133 apbi.psel(0) <= '1';
134 apbi.pwrite <= '1';
135 apbi.penable <= '1';
136 apbi.paddr <= X"00000004";
137 apbi.pwdata <= X"00001234";
138 WAIT UNTIL clk25MHz = '1';
139 apbi.psel(0) <= '0';
140 apbi.pwrite <= '0';
141 apbi.penable <= '0';
142 apbi.paddr <= (OTHERS => '0');
143 apbi.pwdata <= (OTHERS => '0');
144 WAIT UNTIL clk25MHz = '1';
145
146 WAIT FOR 10 ms;
147 WAIT UNTIL clk25MHz = '1';
148 TB_string <= "TICK 4 ";
149 grspw_tick <= '1';------------------------------------------------------3
150 WAIT UNTIL clk25MHz = '1';
151 grspw_tick <= '0';
152
153
154
155
156 WAIT FOR 750 ms;
157
158 REPORT "*** END simulation ***" SEVERITY failure;
159 WAIT;
160
161 END PROCESS;
162
163
164 global_time <= coarse_time & fine_time;
165
166 PROCESS (clk25MHz, resetn)
167 BEGIN -- PROCESS
168 IF resetn = '0' THEN -- asynchronous reset (active low)
169 coarse_time_reg <= (OTHERS => '0');
170 fine_time_reg <= (OTHERS => '0');
171 global_time_reg <= (OTHERS => '0');
172 tick_ongoing <= '0';
173 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
174 global_time_reg <= global_time;
175 coarse_time_reg <= coarse_time;
176 fine_time_reg <= fine_time;
177 IF grspw_tick ='1' THEN
178 tick_ongoing <= '1';
179 ELSIF tick_ongoing = '1' THEN
180 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
181 tick_ongoing <= '0';
182 END IF;
183 END IF;
184
185 END IF;
186 END PROCESS;
187
188 -----------------------------------------------------------------------------
189 -- ASSERTION 1 :
190 -- Coarse_time "changed" => FINE_TIME = 0
191 -- False after a TRANSITION !
192 -----------------------------------------------------------------------------
193 PROCESS (clk25MHz, resetn)
194 BEGIN -- PROCESS
195 IF resetn = '0' THEN -- asynchronous reset (active low)
196 ASSERTION_1 <= '1';
197 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
198 IF coarse_time /= coarse_time_reg THEN
199 IF fine_time /= X"0000" THEN
200 IF fine_time /= X"0041" THEN
201 ASSERTION_1 <= '0';
202 ELSE
203 ASSERTION_1 <= 'U';
204 END IF;
205 ELSE
206 ASSERTION_1 <= '1';
207 END IF;
208 END IF;
209 END IF;
210 END PROCESS;
211
212 -----------------------------------------------------------------------------
213 -- ASSERTION 2 :
214 -- tick => next(FINE_TIME) = 0
215 -----------------------------------------------------------------------------
216 PROCESS (clk25MHz, resetn)
217 BEGIN -- PROCESS
218 IF resetn = '0' THEN -- asynchronous reset (active low)
219 ASSERTION_2 <= '1';
220 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
221 IF tick_ongoing = '1' THEN
222 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
223 IF fine_time /= X"0000" THEN
224 ASSERTION_2 <= '0';
225 END IF;
226 END IF;
227 END IF;
228 END IF;
229 END PROCESS;
230
231 -----------------------------------------------------------------------------
232 -- ASSERTION 3 :
233 -- next(TIME) > TIME
234 -- false if resynchro, or new coarse_time
235 -----------------------------------------------------------------------------
236 PROCESS (clk25MHz, resetn)
237 BEGIN -- PROCESS
238 IF resetn = '0' THEN -- asynchronous reset (active low)
239 ASSERTION_3 <= '1';
240 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
241 ASSERTION_3 <= '1';
242 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
243 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
244 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
245 ELSE
246 ASSERTION_3 <= '0';
247 END IF;
248 END IF;
249 END IF;
250 END PROCESS;
251
252
253 END beh;
254
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1 log -R *
2 do wave.do
3 run -all No newline at end of file
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /tb/tb_string
4 add wave -noupdate /tb/assertion_1
5 add wave -noupdate /tb/assertion_2
6 add wave -noupdate /tb/assertion_3
7 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/state
8 add wave -noupdate -format Analog-Step -height 74 -max 66000.0 -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time
9 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time_new
10 add wave -noupdate -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time
11 add wave -noupdate /tb/apb_lfr_time_management_1/grspw_tick
12 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time
13 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time
14 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new
15 TreeUpdate [SetDefaultTree]
16 WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {369333380000 ps} 0} {TRANSITION {169333245705 ps} 1}
17 configure wave -namecolwidth 512
18 configure wave -valuecolwidth 139
19 configure wave -justifyvalue left
20 configure wave -signalnamewidth 0
21 configure wave -snapdistance 10
22 configure wave -datasetprefix 0
23 configure wave -rowmargin 4
24 configure wave -childrowmargin 2
25 configure wave -gridoffset 0
26 configure wave -gridperiod 1
27 configure wave -griddelta 40
28 configure wave -timeline 0
29 configure wave -timelineunits ps
30 update
31 WaveRestoreZoom {0 ps} {243152392641 ps}
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.std_logic_arith.ALL;
4 USE IEEE.std_logic_unsigned.ALL;
5
6 ENTITY counter IS
7
8 GENERIC (
9 CYCLIC : STD_LOGIC := '1';
10 NB_BITS_COUNTER : INTEGER := 9
11 );
12
13 PORT (
14 clk : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
16 --
17 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
18 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
19 --
20 set : IN STD_LOGIC;
21 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
22 add1 : IN STD_LOGIC;
23 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
24 );
25
26 END counter;
27
28 ARCHITECTURE beh OF counter IS
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
30
31 BEGIN -- beh
32
33 PROCESS (clk, rstn)
34 BEGIN -- PROCESS
35 IF rstn = '0' THEN -- asynchronous reset (active low)
36 counter_s <= RST_VALUE;
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF set = '1' THEN
39 counter_s <= set_value;
40 ELSIF add1 = '1' THEN
41 IF counter_s < MAX_VALUE THEN
42 counter_s <= counter_s + 1;
43 ELSE
44 IF CYCLIC = '1' THEN
45 counter_s <= (OTHERS => '0');
46 END IF;
47 END IF;
48 END IF;
49 END IF;
50 END PROCESS;
51
52 counter <= counter_s;
53
54 END beh;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
7
8 ENTITY coarse_time_counter IS
9 GENERIC (
10 NB_SECOND_DESYNC : INTEGER := 60);
11
12 PORT (
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15
16 tick : IN STD_LOGIC;
17 set_TCU : IN STD_LOGIC;
18 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 CT_add1 : IN STD_LOGIC;
20 fsm_desync : IN STD_LOGIC;
21 FT_max : IN STD_LOGIC;
22
23 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
24 coarse_time_new : OUT STD_LOGIC
25
26 );
27
28 END coarse_time_counter;
29
30 ARCHITECTURE beh OF coarse_time_counter IS
31
32 SIGNAL add1_bit31 : STD_LOGIC;
33 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
34 SIGNAL coarse_time_new_counter : STD_LOGIC;
35 SIGNAL coarse_time_31 : STD_LOGIC;
36 SIGNAL coarse_time_31_reg : STD_LOGIC;
37
38 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
39 BEGIN -- beh
40
41 counter_1 : counter
42 GENERIC MAP (
43 CYCLIC => '1',
44 NB_BITS_COUNTER => 31)
45 PORT MAP (
46 clk => clk,
47 rstn => rstn,
48 RST_VALUE => (OTHERS => '0'),
49 MAX_VALUE => "111" & X"FFFFFFF" ,
50 set => set_TCU,
51 set_value => set_TCU_value,
52 add1 => CT_add1,
53 counter => coarse_time(30 DOWNTO 0));
54
55
56 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
57
58 counter_2 : counter
59 GENERIC MAP (
60 CYCLIC => '0',
61 NB_BITS_COUNTER => 6)
62 PORT MAP (
63 clk => clk,
64 rstn => rstn,
65 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
66 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
67 set => tick,
68 set_value => (OTHERS => '0'),
69 add1 => add1_bit31,
70 counter => nb_second_counter);
71
72 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
73 coarse_time(31) <= coarse_time_31;
74 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
75
76 PROCESS (clk, rstn)
77 BEGIN -- PROCESS
78 IF rstn = '0' THEN -- asynchronous reset (active low)
79 coarse_time_new_counter <= '0';
80 coarse_time_31_reg <= '0';
81 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
82 coarse_time_31_reg <= coarse_time_31;
83 IF set_TCU = '1' OR CT_add1 = '1' THEN
84 coarse_time_new_counter <= '1';
85 ELSE
86 coarse_time_new_counter <= '0';
87 END IF;
88 END IF;
89 END PROCESS;
90
91 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,93
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
7
8 ENTITY fine_time_counter IS
9
10 GENERIC (
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
12 FIRST_DIVISION : INTEGER := 374
13 );
14
15 PORT (
16 clk : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
18 --
19 tick : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
21
22 FT_max : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 fine_time_new : OUT STD_LOGIC
27 );
28
29 END fine_time_counter;
30
31 ARCHITECTURE beh OF fine_time_counter IS
32
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 SIGNAL new_ft : STD_LOGIC;
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
38
39 BEGIN -- beh
40
41
42
43 counter_1 : counter
44 GENERIC MAP (
45 CYCLIC => '1',
46 NB_BITS_COUNTER => 9)
47 PORT MAP (
48 clk => clk,
49 rstn => rstn,
50 RST_VALUE => (OTHERS => '0'),
51 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
52 set => tick,
53 set_value => (OTHERS => '0'),
54 add1 => '1',
55 counter => new_ft_counter);
56
57 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
58
59 counter_2 : counter
60 GENERIC MAP (
61 CYCLIC => '1',
62 NB_BITS_COUNTER => 16)
63 PORT MAP (
64 clk => clk,
65 rstn => rstn,
66 RST_VALUE => (OTHERS => '0'),
67 MAX_VALUE => X"FFFF",
68 set => tick,
69 set_value => (OTHERS => '0'),
70 add1 => new_ft,
71 counter => fine_time_counter);
72
73 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
74 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
75 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
76
77 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
78
79 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 fine_time_new <= '0';
83 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
84 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
85 fine_time_new <= '1';
86 ELSE
87 fine_time_new <= '0';
88 END IF;
89 END IF;
90 END PROCESS;
91
92 END beh;
93
Show file before | Show file after | Hide comments
@@ -27,12 +27,26
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
30
31
31
32
32
33
33 PACKAGE general_purpose IS
34 PACKAGE general_purpose IS
34
35
35
36 COMPONENT counter
37 GENERIC (
38 CYCLIC : STD_LOGIC;
39 NB_BITS_COUNTER : INTEGER);
40 PORT (
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 set : IN STD_LOGIC;
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 add1 : IN STD_LOGIC;
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 END COMPONENT;
36
50
37 COMPONENT Clk_divider IS
51 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
Show file before | Show file after | Hide comments
@@ -22,3 +22,4 lpp_front_detection.vhd
22 lpp_front_positive_detection.vhd
22 lpp_front_positive_detection.vhd
23 SYNC_VALID_BIT.vhd
23 SYNC_VALID_BIT.vhd
24 RR_Arbiter_4.vhd
24 RR_Arbiter_4.vhd
25 counter.vhd
Show file before | Show file after | Hide comments
@@ -32,21 +32,23 USE lpp.lpp_lfr_time_management.ALL;
32 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
33
33
34 GENERIC(
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 FIRST_DIVISION : INTEGER := 374;
39 nb_wait_pediod : INTEGER := 375
39 NB_SECOND_DESYNC : INTEGER := 60
40 );
40 );
41
41
42 PORT (
42 PORT (
43 clk25MHz : IN STD_LOGIC; --! Clock
43 clk25MHz : IN STD_LOGIC; --! Clock
44 clk49_152MHz : IN STD_LOGIC; --! secondary clock
44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 resetn : IN STD_LOGIC; --! Reset
45 resetn : IN STD_LOGIC; --! Reset
46
46
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 apbi : IN apb_slv_in_type; --! APB slave input signals
48
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
49 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : OUT apb_slv_out_type; --! APB slave output signals
51
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52 );
54 );
@@ -57,63 +59,44 ARCHITECTURE Behavioral OF apb_lfr_time_
57
59
58 CONSTANT REVISION : INTEGER := 1;
60 CONSTANT REVISION : INTEGER := 1;
59 CONSTANT pconfig : apb_config_type := (
61 CONSTANT pconfig : apb_config_type := (
60 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
61 1 => apb_iobar(paddr, pmask)
63 1 => apb_iobar(paddr, pmask)
62 );
64 );
63
65
64 TYPE apb_lfr_time_management_Reg IS RECORD
66 TYPE apb_lfr_time_management_Reg IS RECORD
65 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 ctrl : STD_LOGIC;
66 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 END RECORD;
71 END RECORD;
70
71 SIGNAL r : apb_lfr_time_management_Reg;
72 SIGNAL r : apb_lfr_time_management_Reg;
73
72 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL force_tick : STD_LOGIC;
75 SIGNAL force_tick : STD_LOGIC;
74 SIGNAL previous_force_tick : STD_LOGIC;
76 SIGNAL previous_force_tick : STD_LOGIC;
75 SIGNAL soft_tick : STD_LOGIC;
77 SIGNAL soft_tick : STD_LOGIC;
76
78
77 SIGNAL irq1 : STD_LOGIC;
78 SIGNAL irq2 : STD_LOGIC;
79
80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
82
81
83 SIGNAL coarse_time_new : STD_LOGIC;
82 --SIGNAL coarse_time_new : STD_LOGIC;
84 SIGNAL coarse_time_new_49 : STD_LOGIC;
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
85 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 --SIGNAL fine_time_new : STD_LOGIC;
88 --SIGNAL fine_time_new_temp : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL tick : STD_LOGIC;
93 SIGNAL new_timecode : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
87
95
88 SIGNAL fine_time_new : STD_LOGIC;
96 SIGNAL time_new_49 : STD_LOGIC;
89 SIGNAL fine_time_new_temp : STD_LOGIC;
97 SIGNAL time_new : STD_LOGIC;
90 SIGNAL fine_time_new_49 : STD_LOGIC;
91 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 SIGNAL tick : STD_LOGIC;
94 SIGNAL new_timecode : STD_LOGIC;
95 SIGNAL new_coarsetime : STD_LOGIC;
96
98
97 BEGIN
99 BEGIN
98 -----------------------------------------------------------------------------
99 -- TODO
100 -- IRQ 1 & 2
101 -----------------------------------------------------------------------------
102 irq2 <= '0';
103 irq1 <= '0';
104
105
106 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
107 --irq1_gen : IF I = pirq GENERATE
108 apbo.pirq(pirq) <= irq1;
109 --END GENERATE irq1_gen;
110 --irq2_gen : IF I = pirq+1 GENERATE
111 apbo.pirq(pirq+1) <= irq2;
112 -- END GENERATE irq2_gen;
113 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
114 -- apbo.pirq(I) <= '0';
115 -- END GENERATE others_irq;
116 --END GENERATE all_irq_gen;
117
100
118 PROCESS(resetn, clk25MHz)
101 PROCESS(resetn, clk25MHz)
119 BEGIN
102 BEGIN
@@ -121,7 +104,7 BEGIN
121 IF resetn = '0' THEN
104 IF resetn = '0' THEN
122 Rdata <= (OTHERS => '0');
105 Rdata <= (OTHERS => '0');
123 r.coarse_time_load <= x"80000000";
106 r.coarse_time_load <= x"80000000";
124 r.ctrl <= x"00000000";
107 r.ctrl <= '0';
125 force_tick <= '0';
108 force_tick <= '0';
126 previous_force_tick <= '0';
109 previous_force_tick <= '0';
127 soft_tick <= '0';
110 soft_tick <= '0';
@@ -131,7 +114,7 BEGIN
131 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
114 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
132 coarsetime_reg_updated <= '0';
115 coarsetime_reg_updated <= '0';
133
116
134 force_tick <= r.ctrl(0);
117 force_tick <= r.ctrl;
135 previous_force_tick <= force_tick;
118 previous_force_tick <= force_tick;
136 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
119 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
137 soft_tick <= '1';
120 soft_tick <= '1';
@@ -143,28 +126,28 BEGIN
143 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
126 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
144 CASE apbi.paddr(7 DOWNTO 2) IS
127 CASE apbi.paddr(7 DOWNTO 2) IS
145 WHEN "000000" =>
128 WHEN "000000" =>
146 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
129 r.ctrl <= apbi.pwdata(0);
147 WHEN "000001" =>
130 WHEN "000001" =>
148 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
149 coarsetime_reg_updated <= '1';
132 coarsetime_reg_updated <= '1';
150 WHEN OTHERS =>
133 WHEN OTHERS =>
151 END CASE;
134 END CASE;
152 ELSIF r.ctrl(0) = '1' THEN
135 ELSIF r.ctrl = '1' THEN
153 r.ctrl(0) <= '0';
136 r.ctrl <= '0';
154 END IF;
137 END IF;
155
138
156 --APB READ OP
139 --APB READ OP
157 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
140 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
158 CASE apbi.paddr(7 DOWNTO 2) IS
141 CASE apbi.paddr(7 DOWNTO 2) IS
159 WHEN "000000" =>
142 WHEN "000000" =>
160 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
143 Rdata(0) <= r.ctrl;
161 WHEN "000001" =>
144 WHEN "000001" =>
162 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
145 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
163 WHEN "000010" =>
146 WHEN "000010" =>
164 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
147 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
165 WHEN "000011" =>
148 WHEN "000011" =>
166 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
149 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
167 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
150 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
168 WHEN OTHERS =>
151 WHEN OTHERS =>
169 Rdata(31 DOWNTO 0) <= x"00000000";
152 Rdata(31 DOWNTO 0) <= x"00000000";
170 END CASE;
153 END CASE;
@@ -173,25 +156,24 BEGIN
173 END IF;
156 END IF;
174 END PROCESS;
157 END PROCESS;
175
158
176 apbo.prdata <= Rdata;
159 apbo.prdata <= Rdata;
177 apbo.pconfig <= pconfig;
160 apbo.pconfig <= pconfig;
178 apbo.pindex <= pindex;
161 apbo.pindex <= pindex;
179
162
180 coarse_time <= r.coarse_time;
163 -----------------------------------------------------------------------------
181 fine_time <= r.fine_time;
164 -- IN
165 coarse_time <= r.coarse_time;
166 fine_time <= r.fine_time;
167 coarsetime_reg <= r.coarse_time_load;
182 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
183
169
184 coarsetime_reg <= r.coarse_time_load;
170 -----------------------------------------------------------------------------
171 -- OUT
185 r.coarse_time <= coarse_time_s;
172 r.coarse_time <= coarse_time_s;
186 r.fine_time <= fine_time_s;
173 r.fine_time <= fine_time_s;
187 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
188 -- IN coarsetime_reg_updated
189 -- IN coarsetime_reg
190
175
191 -- OUT coarse_time_s -- ok
192 -- OUT fine_time_s -- ok
193 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
194
195 tick <= grspw_tick OR soft_tick;
177 tick <= grspw_tick OR soft_tick;
196
178
197 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
179 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
@@ -199,7 +181,7 BEGIN
199 NB_FF_OF_SYNC => 2)
181 NB_FF_OF_SYNC => 2)
200 PORT MAP (
182 PORT MAP (
201 clk_in => clk25MHz,
183 clk_in => clk25MHz,
202 clk_out => clk49_152MHz,
184 clk_out => clk24_576MHz,
203 rstn => resetn,
185 rstn => resetn,
204 sin => tick,
186 sin => tick,
205 sout => new_timecode);
187 sout => new_timecode);
@@ -209,57 +191,61 BEGIN
209 NB_FF_OF_SYNC => 2)
191 NB_FF_OF_SYNC => 2)
210 PORT MAP (
192 PORT MAP (
211 clk_in => clk25MHz,
193 clk_in => clk25MHz,
212 clk_out => clk49_152MHz,
194 clk_out => clk24_576MHz,
213 rstn => resetn,
195 rstn => resetn,
214 sin => coarsetime_reg_updated,
196 sin => coarsetime_reg_updated,
215 sout => new_coarsetime);
197 sout => new_coarsetime);
198 ----------------------------------------------------------------------------
216
199
217 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
200 -----------------------------------------------------------------------------
201 --SYNC_FF_1 : SYNC_FF
218 -- GENERIC MAP (
202 -- GENERIC MAP (
219 -- NB_FF_OF_SYNC => 2)
203 -- NB_FF_OF_SYNC => 2)
220 -- PORT MAP (
204 -- PORT MAP (
221 -- clk_in => clk49_152MHz,
205 -- clk => clk25MHz,
206 -- rstn => resetn,
207 -- A => fine_time_new_49,
208 -- A_sync => fine_time_new_temp);
209
210 --lpp_front_detection_1 : lpp_front_detection
211 -- PORT MAP (
212 -- clk => clk25MHz,
213 -- rstn => resetn,
214 -- sin => fine_time_new_temp,
215 -- sout => fine_time_new);
216
217 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
218 -- GENERIC MAP (
219 -- NB_FF_OF_SYNC => 2)
220 -- PORT MAP (
221 -- clk_in => clk24_576MHz,
222 -- clk_out => clk25MHz,
222 -- clk_out => clk25MHz,
223 -- rstn => resetn,
223 -- rstn => resetn,
224 -- sin => 9,
224 -- sin => coarse_time_new_49,
225 -- sout => );
225 -- sout => coarse_time_new);
226
227 SYNC_FF_1: SYNC_FF
228 GENERIC MAP (
229 NB_FF_OF_SYNC => 2)
230 PORT MAP (
231 clk => clk25MHz,
232 rstn => resetn,
233 A => fine_time_new_49,
234 A_sync => fine_time_new_temp);
235
226
236 lpp_front_detection_1: lpp_front_detection
227 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
237 PORT MAP (
238 clk => clk25MHz,
239 rstn => resetn,
240 sin => fine_time_new_temp,
241 sout => fine_time_new);
242
228
243 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
229 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
244 GENERIC MAP (
230 GENERIC MAP (
245 NB_FF_OF_SYNC => 2)
231 NB_FF_OF_SYNC => 2)
246 PORT MAP (
232 PORT MAP (
247 clk_in => clk49_152MHz,
233 clk_in => clk24_576MHz,
248 clk_out => clk25MHz,
234 clk_out => clk25MHz,
249 rstn => resetn,
235 rstn => resetn,
250 sin => coarse_time_new_49,
236 sin => time_new_49,
251 sout => coarse_time_new);
237 sout => time_new);
238
252
239
240
253 PROCESS (clk25MHz, resetn)
241 PROCESS (clk25MHz, resetn)
254 BEGIN -- PROCESS
242 BEGIN -- PROCESS
255 IF resetn = '0' THEN -- asynchronous reset (active low)
243 IF resetn = '0' THEN -- asynchronous reset (active low)
256 fine_time_s <= (OTHERS => '0');
244 fine_time_s <= (OTHERS => '0');
257 coarse_time_s <= (OTHERS => '0');
245 coarse_time_s <= (OTHERS => '0');
258 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
246 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
259 IF fine_time_new = '1' THEN
247 IF time_new = '1' THEN
260 fine_time_s <= fine_time_49;
248 fine_time_s <= fine_time_49;
261 END IF;
262 IF coarse_time_new = '1' THEN
263 coarse_time_s <= coarse_time_49;
249 coarse_time_s <= coarse_time_49;
264 END IF;
250 END IF;
265 END IF;
251 END IF;
@@ -270,19 +256,19 BEGIN
270 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
271 lfr_time_management_1 : lfr_time_management
257 lfr_time_management_1 : lfr_time_management
272 GENERIC MAP (
258 GENERIC MAP (
273 nb_time_code_missing_limit => 60,
259 FIRST_DIVISION => FIRST_DIVISION,
274 nb_wait_pediod => 375)
260 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
275 PORT MAP (
261 PORT MAP (
276 clk => clk49_152MHz,
262 clk => clk24_576MHz,
277 rstn => resetn,
263 rstn => resetn,
278
264
279 new_timecode => new_timecode,
265 tick => new_timecode,
280 new_coarsetime => new_coarsetime,
266 new_coarsetime => new_coarsetime,
281 coarsetime_reg => coarsetime_reg,
267 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
282
268
283 fine_time => fine_time_49,
269 fine_time => fine_time_49,
284 fine_time_new => fine_time_new_49,
270 fine_time_new => fine_time_new_49,
285 coarse_time => coarse_time_49,
271 coarse_time => coarse_time_49,
286 coarse_time_new => coarse_time_new_49);
272 coarse_time_new => coarse_time_new_49);
287
273
288 END Behavioral; No newline at end of file
274 END Behavioral;
Show file before | Show file after | Hide comments
@@ -25,16 +25,16 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 nb_time_code_missing_limit : INTEGER := 60;
28 FIRST_DIVISION : INTEGER := 374;
29 nb_wait_pediod : INTEGER := 375
29 NB_SECOND_DESYNC : INTEGER := 60);
30 );
31 PORT (
30 PORT (
32 clk : IN STD_LOGIC;
31 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
34
33
35 new_timecode : IN STD_LOGIC; -- transition signal information
34 tick : IN STD_LOGIC; -- transition signal information
35
36 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
38
38
39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 fine_time_new : OUT STD_LOGIC;
40 fine_time_new : OUT STD_LOGIC;
@@ -45,68 +45,129 END lfr_time_management;
45
45
46 ARCHITECTURE Behavioral OF lfr_time_management IS
46 ARCHITECTURE Behavioral OF lfr_time_management IS
47
47
48 SIGNAL counter_clear : STD_LOGIC;
48 SIGNAL FT_max : STD_LOGIC;
49 SIGNAL counter_full : STD_LOGIC;
49 SIGNAL FT_half : STD_LOGIC;
50 SIGNAL FT_wait : STD_LOGIC;
51
52 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
53 SIGNAL state : state_fsm_time_management;
50
54
51 SIGNAL nb_time_code_missing : INTEGER;
55 SIGNAL fsm_desync : STD_LOGIC;
52 SIGNAL coarse_time_s : INTEGER;
56 SIGNAL fsm_transition : STD_LOGIC;
53
57
54 SIGNAL new_coarsetime_s : STD_LOGIC;
58 SIGNAL set_TCU : STD_LOGIC;
55
59 SIGNAL CT_add1 : STD_LOGIC;
60
61 SIGNAL new_coarsetime_reg : STD_LOGIC;
62
56 BEGIN
63 BEGIN
57
58 lpp_counter_1 : lpp_counter
59 GENERIC MAP (
60 nb_wait_period => nb_wait_pediod,
61 nb_bit_of_data => 16)
62 PORT MAP (
63 clk => clk,
64 rstn => rstn,
65 clear => counter_clear,
66 full => counter_full,
67 data => fine_time,
68 new_data => fine_time_new);
69
64
65 -----------------------------------------------------------------------------
66 --
67 -----------------------------------------------------------------------------
70 PROCESS (clk, rstn)
68 PROCESS (clk, rstn)
71 BEGIN -- PROCESS
69 BEGIN -- PROCESS
72 IF rstn = '0' THEN -- asynchronous reset (active low)
70 IF rstn = '0' THEN -- asynchronous reset (active low)
73 nb_time_code_missing <= 0;
71 new_coarsetime_reg <= '0';
74 counter_clear <= '0';
72 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
75 coarse_time_s <= 0;
76 coarse_time_new <= '0';
77 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
78 IF new_coarsetime = '1' THEN
73 IF new_coarsetime = '1' THEN
79 new_coarsetime_s <= '1';
74 new_coarsetime_reg <= '1';
80 ELSIF new_timecode = '1' THEN
75 ELSIF tick = '1' THEN
81 new_coarsetime_s <= '0';
76 new_coarsetime_reg <= '0';
82 END IF;
77 END IF;
83
78 END IF;
84 IF new_timecode = '1' THEN
79 END PROCESS;
85 coarse_time_new <= '1';
80
86 IF new_coarsetime_s = '1' THEN
81 -----------------------------------------------------------------------------
87 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
82 -- FINE_TIME
88 ELSE
83 -----------------------------------------------------------------------------
89 coarse_time_s <= coarse_time_s + 1;
84 fine_time_counter_1: fine_time_counter
90 END IF;
85 GENERIC MAP (
91 nb_time_code_missing <= 0;
86 WAITING_TIME => X"0040",
92 counter_clear <= '1';
87 FIRST_DIVISION => FIRST_DIVISION)
93 ELSE
88 PORT MAP (
94 coarse_time_new <= '0';
89 clk => clk,
95 counter_clear <= '0';
90 rstn => rstn,
96 IF counter_full = '1' THEN
91 tick => tick,
97 coarse_time_new <= '1';
92 fsm_transition => fsm_transition, -- todo
98 coarse_time_s <= coarse_time_s + 1;
93 FT_max => FT_max,
99 IF nb_time_code_missing = nb_time_code_missing_limit THEN
94 FT_half => FT_half,
100 nb_time_code_missing <= nb_time_code_missing_limit;
95 FT_wait => FT_wait,
101 ELSE
96 fine_time => fine_time,
102 nb_time_code_missing <= nb_time_code_missing + 1;
97 fine_time_new => fine_time_new);
98
99 -----------------------------------------------------------------------------
100 -- COARSE_TIME
101 -----------------------------------------------------------------------------
102 coarse_time_counter_1: coarse_time_counter
103 GENERIC MAP(
104 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
105 PORT MAP (
106 clk => clk,
107 rstn => rstn,
108 tick => tick,
109 set_TCU => set_TCU, -- todo
110 set_TCU_value => coarsetime_reg, -- todo
111 CT_add1 => CT_add1, -- todo
112 fsm_desync => fsm_desync, -- todo
113 FT_max => FT_max,
114 coarse_time => coarse_time,
115 coarse_time_new => coarse_time_new);
116
117 -----------------------------------------------------------------------------
118 -- FSM
119 -----------------------------------------------------------------------------
120 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
121 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
122
123 PROCESS (clk, rstn)
124 BEGIN -- PROCESS
125 IF rstn = '0' THEN -- asynchronous reset (active low)
126 state <= DESYNC;
127 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
128 --CT_add1 <= '0';
129 set_TCU <= '0';
130 CASE state IS
131 WHEN DESYNC =>
132 IF tick = '1' THEN
133 state <= SYNC;
134 set_TCU <= new_coarsetime_reg;
135 --IF new_coarsetime = '0' AND FT_half = '1' THEN
136 -- CT_add1 <= '1';
137 --END IF;
138 --ELSIF FT_max = '1' THEN
139 -- CT_add1 <= '1';
103 END IF;
140 END IF;
104 END IF;
141 WHEN TRANSITION =>
105 END IF;
142 IF tick = '1' THEN
143 state <= SYNC;
144 set_TCU <= new_coarsetime_reg;
145 --IF new_coarsetime = '0' THEN
146 -- CT_add1 <= '1';
147 --END IF;
148 ELSIF FT_wait = '1' THEN
149 --CT_add1 <= '1';
150 state <= DESYNC;
151 END IF;
152 WHEN SYNC =>
153 IF tick = '1' THEN
154 set_TCU <= new_coarsetime_reg;
155 --IF new_coarsetime = '0' THEN
156 -- CT_add1 <= '1';
157 --END IF;
158 ELSIF FT_max = '1' THEN
159 state <= TRANSITION;
160 END IF;
161 WHEN OTHERS => NULL;
162 END CASE;
106 END IF;
163 END IF;
107 END PROCESS;
164 END PROCESS;
108
165
109 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
166
110 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
167 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
111
168 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
169 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
170 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
171 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
172 '0';
112 END Behavioral;
173 END Behavioral;
Show file before | Show file after | Hide comments
@@ -31,15 +31,14 PACKAGE lpp_lfr_time_management IS
31
31
32 COMPONENT apb_lfr_time_management IS
32 COMPONENT apb_lfr_time_management IS
33 GENERIC(
33 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0;
37 FIRST_DIVISION : INTEGER;
38 nb_wait_pediod : INTEGER := 375
38 NB_SECOND_DESYNC : INTEGER);
39 );
40 PORT (
39 PORT (
41 clk25MHz : IN STD_LOGIC; --! Clock
40 clk25MHz : IN STD_LOGIC; --! Clock
42 clk49_152MHz : IN STD_LOGIC; --! secondary clock
41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
43 resetn : IN STD_LOGIC; --! Reset
42 resetn : IN STD_LOGIC; --! Reset
44 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45 apbi : IN apb_slv_in_type; --! APB slave input signals
44 apbi : IN apb_slv_in_type; --! APB slave input signals
@@ -51,33 +50,52 PACKAGE lpp_lfr_time_management IS
51
50
52 COMPONENT lfr_time_management
51 COMPONENT lfr_time_management
53 GENERIC (
52 GENERIC (
54 nb_time_code_missing_limit : INTEGER;
53 FIRST_DIVISION : INTEGER;
55 nb_wait_pediod : INTEGER := 375);
54 NB_SECOND_DESYNC : INTEGER);
55 PORT (
56 clk : IN STD_LOGIC;
57 rstn : IN STD_LOGIC;
58 tick : IN STD_LOGIC;
59 new_coarsetime : IN STD_LOGIC;
60 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 fine_time_new : OUT STD_LOGIC;
63 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 coarse_time_new : OUT STD_LOGIC);
65 END COMPONENT;
66
67 COMPONENT coarse_time_counter
68 GENERIC (
69 NB_SECOND_DESYNC : INTEGER );
70 PORT (
71 clk : IN STD_LOGIC;
72 rstn : IN STD_LOGIC;
73 tick : IN STD_LOGIC;
74 set_TCU : IN STD_LOGIC;
75 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
76 CT_add1 : IN STD_LOGIC;
77 fsm_desync : IN STD_LOGIC;
78 FT_max : IN STD_LOGIC;
79 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 coarse_time_new : OUT STD_LOGIC);
81 END COMPONENT;
82
83 COMPONENT fine_time_counter
84 GENERIC (
85 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
86 FIRST_DIVISION : INTEGER );
56 PORT (
87 PORT (
57 clk : IN STD_LOGIC;
88 clk : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
89 rstn : IN STD_LOGIC;
59 new_timecode : IN STD_LOGIC;
90 tick : IN STD_LOGIC;
60 new_coarsetime : IN STD_LOGIC;
91 fsm_transition : IN STD_LOGIC;
61 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 FT_max : OUT STD_LOGIC;
93 FT_half : OUT STD_LOGIC;
94 FT_wait : OUT STD_LOGIC;
62 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
95 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
63 fine_time_new : OUT STD_LOGIC;
96 fine_time_new : OUT STD_LOGIC);
64 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 coarse_time_new : OUT STD_LOGIC
66 );
67 END COMPONENT;
97 END COMPONENT;
68
98
69 COMPONENT lpp_counter
99
70 GENERIC (
71 nb_wait_period : INTEGER;
72 nb_bit_of_data : INTEGER);
73 PORT (
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 clear : IN STD_LOGIC;
77 full : OUT STD_LOGIC;
78 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
79 new_data : OUT STD_LOGIC );
80 END COMPONENT;
81
82 END lpp_lfr_time_management;
100 END lpp_lfr_time_management;
83
101
Show file before | Show file after | Hide comments
@@ -1,4 +1,5
1 lpp_lfr_time_management.vhd
1 apb_lfr_time_management.vhd
2 apb_lfr_time_management.vhd
2 lpp_counter.vhd
3 lfr_time_management.vhd
3 lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
4 fine_time_counter.vhd
5 coarse_time_counter.vhd
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
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